CN111341749A - 半导体模块 - Google Patents

半导体模块 Download PDF

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CN111341749A
CN111341749A CN201911303208.XA CN201911303208A CN111341749A CN 111341749 A CN111341749 A CN 111341749A CN 201911303208 A CN201911303208 A CN 201911303208A CN 111341749 A CN111341749 A CN 111341749A
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semiconductor
semiconductor chip
main terminal
diode
semiconductor substrate
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CN111341749B (zh
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杉浦秀和
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Denso Corp
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Abstract

本发明抑制浪涌电流引起的SiC晶体的劣化。提供一种半导体模块，其具有：第一半导体芯片，其具备第一半导体基板，该第一半导体基板具备场效应晶体管且由SiC制成；第二半导体芯片，其具备第二半导体基板，该第二半导体基板具备二极管；第一引线框架，其具备第一主端子；以及第二引线框架，其具备第二主端子。第一引线框架与第一半导体芯片的漏电极和第二半导体芯片的阴极电极连接。第二引线框架与第一半导体芯片的源电极和第二半导体芯片的阳极电极连接。从第二主端子经由第一半导体芯片至第一主端子的第一电流路径，与从第二主端子经由第二半导体芯片至第一主端子的第二电流路径相比更长。

Description

半导体模块
技术领域
本说明书公开的技术涉及半导体模块。
背景技术
专利文献1中公开了一种半导体模块。该半导体模块具备场效应晶体管(以下称为FET)和二极管(以下称为主二极管)。FET设置在由SiC(碳化硅)制成的半导体基板上。FET的漏极和主二极管的阴极与共同的端子(以下称为第一端子)连接，FET的源极和主二极管的阳极与共同的端子(以下称为第二端子)连接。在FET内部以寄生形式形成体二极管。体二极管的阳极与FET的源极(即第二端子)连接，体二极管的阴极与FET的漏极(即第一端子)连接。因此，主二极管和体二极管在第一端子与第二端子之间并联连接。如果第二端子的电位变得高于第一端子的电位，则主二极管沿正向被施加电压，从而主二极管导通。此时，由于体二极管也被施加正向电压，因此体二极管有可能导通。如果电流流过体二极管，则设置有FET的半导体基板的SiC晶体劣化。针对该问题，在专利文献1的技术中，通过设定主二极管的导通电压低于体二极管的起始通电电压，从而抑制体二极管的导通。由此，抑制SiC晶体的劣化。
专利文献1：日本特开2007-305836号公报
发明内容
如专利文献1所述，在主二极管和体二极管并联连接的电路中，由于电路中的电感的影响，有时浪涌电流会沿正向流过主二极管和体二极管。专利文献1的技术也不能抑制浪涌电流流过体二极管。因此，设置有FET的半导体基板的SiC晶体由于浪涌电流而劣化。在本说明书中，提出了一种抑制浪涌电流引起的SiC晶体的劣化的技术。
本说明书公开的半导体模块具有第一半导体芯片、第二半导体芯片、第一引线框架以及第二引线框架。所述第一半导体芯片具备：第一半导体基板，其具备场效应晶体管且由SiC制成；漏电极，其设置在所述第一半导体基板的一侧表面上；以及源电极，其设置在所述第一半导体基板的另一侧表面上。所述第二半导体芯片具备：第二半导体基板，其具备二极管；阴极电极，其设置在所述第二半导体基板的一侧表面上；以及阳极电极，其设置在所述第二半导体基板的另一侧表面上。所述第一引线框架具备第一主端子，与所述漏电极和所述阴极电极连接。所述第二引线框架具备第二主端子，与所述源电极和所述阳极电极连接。从所述第二主端子经由所述第一半导体芯片至所述第一主端子的第一电流路径，与从所述第二主端子经由所述第二半导体芯片至所述第一主端子的第二电流路径相比更长。
在该半导体模块中，当第二主端子的电位相对于第一主端子的电位急剧上升时，浪涌电流流过第一电流路径(即，第一半导体芯片的场效应晶体管的体二极管)和第二电流路径(即，第二半导体芯片的二极管)。由于第一电流路径比第二电流路径长，因此第一电流路径的寄生电感比第二电流路径的寄生电感大。与寄生电感较小的第二电流路径相比，在寄生电感较大的第一电流路径中，进一步抑制电流的增加。因此，与第一电流路径相比，浪涌电流更多地流过第二电流路径。因此，抑制第一半导体芯片的场效应晶体管的体二极管中流过的浪涌电流。从而，抑制第一半导体基板的SiC晶体的劣化。
附图说明
图1是具有实施方式的半导体模块的逆变电路的电路图。
图2是实施方式的半导体模块的电路图。
图3是实施方式的半导体模块的俯视图。
图4是沿图3的IV-IV线的剖视图。
图5是示出实施方式的半导体模块的寄生电感的电路图。
图6是示出流过实施方式的半导体模块的浪涌电流的曲线图。
图7是示出流过对比例的半导体模块的浪涌电流的曲线图。
图8是第一变形例的半导体模块的电路图。
图9是第二变形例的半导体模块的俯视图。
图10是沿图9的X-X线的剖视图。
图11是具有第三变形例的半导体模块的逆变电路的电路图。
图12是第三变形例的半导体模块的俯视图。
图13是沿图12的XIII-XIII线的剖视图。
图14是具有实施方式的半导体模块的DC-DC转换电路的电路图。
具体实施方式
图1示出了具备实施方式的半导体模块10的逆变电路。逆变电路具备高电位配线90、低电位配线92以及三条输出配线94、96、98。在高电位配线90与低电位配线92之间，通过未图示的电源施加直流电压。输出配线94、96、98与L负载88(例如三相电动机)连接。高电位配线90与输出配线94之间连接有一个半导体模块10。高电位配线90与输出配线96之间连接有一个半导体模块10。高电位配线90与输出配线98之间连接有一个半导体模块10。低电位配线92与输出配线94之间连接有一个半导体模块10。低电位配线92与输出配线96之间连接有一个半导体模块10。低电位配线92与输出配线98之间连接有一个半导体模块10。通过各个半导体模块10的MOSFET 12进行整流，三相交流电经由输出配线94、96、98供给至L负载88。
图2示出了半导体模块10的电路图。如图2所示，半导体模块10具有场效应晶体管12和二极管16。在本实施方式中，使用MOSFET(metal oxide semiconductor field effecttransistor，金属氧化物半导体场效应晶体管)作为场效应晶体管12。MOSFET 12的漏极与主端子20连接，MOSFET 12的源极与主端子22连接。此外，MOSFET 12具有体二极管14。体二极管14是在MOSFET 12的内部以寄生形式形成的pn二极管。体二极管14的阴极与主端子20连接，体二极管14的阳极与主端子22连接。二极管16可以是pn二极管，也可以是肖特基势垒二极管。二极管16的阴极与主端子20连接，二极管16的阳极与主端子22连接。如图1所示，在上臂的半导体模块10中，主端子20与高电位配线90连接，主端子22与输出配线94、96、98中的其中一条连接。在下臂的半导体模块10中，主端子20与输出配线94、96和98中的其中一条连接，主端子22与低电位配线92连接。
图3和图4示出了半导体模块10的构造。如图3和图4所示，半导体模块10具有半导体芯片30、半导体芯片32、引线框架34、引线框架36以及绝缘树脂40。图2的MOSFET 12以及体二极管14设置在半导体芯片32内，图2的二极管16设置在半导体芯片30内。如图4所示，引线框架34上配置有半导体芯片30、32。半导体芯片30、32上配置有引线框架36。
如图4所示，半导体芯片32具有半导体基板32a、漏电极32b以及源电极32c。半导体基板32a由SiC制成。半导体基板32a的内部设置有MOSFET 12以及体二极管14。漏电极32b设置在半导体基板32a的下表面。漏电极32b是MOSFET 12的漏电极，同时也是体二极管14的阴极电极。漏电极32b通过软钎焊与引线框架34连接。源电极32c设置在半导体基板32a的上表面。源电极32c是MOSFET 12的源电极，同时也是体二极管14的阳极电极。源电极32c通过软钎焊与引线框架36连接。如图3所示，半导体基板32a的上表面设置有多个信号电极32d。信号电极32d包括MOSFET 12的栅电极和开尔文源电极。每个信号电极32d通过键合线与对应的信号端子38连接。
如图4所示，半导体芯片30具有半导体基板30a、阴极电极30b、以及阳极电极30c。半导体基板30可以由硅制成，也可以由SiC制成。半导体基板30a的内部设置有二极管16。阴极电极30b设置在半导体基板30a的下表面。阴极电极30b通过软钎焊与引线框架34连接。阳极电极30c设置在半导体基板30a的上表面。阳极电极30c通过软钎焊与引线框架36连接。
绝缘树脂40覆盖半导体芯片30、32及其周围的引线框架34、36的表面。
如图3所示，在引线框架34的局部设置有主端子20。主端子20从绝缘树脂40向外侧凸出。此外，在引线框架36的局部设置有主端子22。主端子22从绝缘树脂40向外侧凸出。主端子20和主端子22大致平行地延伸，从绝缘树脂40的同一个侧面向外侧凸出。如图3所示，当沿着层叠方向观察引线框架34、半导体芯片30、32、以及引线框架36时，半导体芯片30与半导体芯片32相比配置在更靠近主端子20、22的位置。
二极管16的正向电压(基准电流流过时的正向电压降)比体二极管14的正向电压低。因此，在二极管16和体二极管14的并联电路中沿正向稳定地施加直流电压的状态下，在二极管16中电流流过，但体二极管14中几乎没有电流流过。即，在稳定地施加使主端子22的电位高于主端子20的电位的直流电压的状态下，在二极管16中电流流过，但体二极管14中几乎没有电流流过。这样，在稳定状态下，体二极管14中几乎没有电流流过。另一方面，有时主端子22的电位相对于主端子20的电位急剧上升。在该情况下，由于电路的电感的影响，浪涌电流流过二极管16和体二极管14这两者。下面，对浪涌电流进行说明。
在图1中，如果下臂的半导体模块10b的MOSFET 12导通、上臂的半导体模块10a的MOSFET 12关断，则如箭头102所示，电流从输出配线94经由下臂的MOSFET 12流向低电位配线92。之后，如果下臂的MOSFET 12关断，则L负载88的感应电动势导致输出配线94的电位上升。结果，上臂的半导体模块10a的主端子22的电位急剧上升至比高电位配线90的电位更高的电位。因此，浪涌电流流过上臂的半导体模块10a的体二极管14和二极管16。
此外，在图1中，如果上臂的半导体模块10a的MOSFET 12导通、下臂的半导体模块10b的MOSFET 12关断，则如箭头104所示，电流从高电位配线90经由上臂的MOSFET 12流向输出配线94。之后，如果上臂的MOSFET 12关断，则L负载88的感应电动势导致输出配线94的电位下降。结果，下臂的半导体模块10b的主端子20的电位急剧下降至比低电位配线92的电位更低的电位。即，在下臂的半导体模块10b中，主端子22的电位相对于主端子20的电位急剧上升。因此，浪涌电流流过下臂的半导体模块10b的体二极管14和二极管16。
这样，在上臂的半导体模块10和下臂的半导体模块10的任一个中，浪涌电流都流过体二极管14和二极管16。然而，如以下说明所示，利用实施方式的半导体模块10，能够减少流过体二极管14的浪涌电流。
图3的箭头110、112示出了浪涌电流的电流路径。电流路径110是流过半导体芯片30(即二极管16)的浪涌电流的电流路径，电流路径112是流过半导体芯片32(即体二极管14)的浪涌电流的电流路径。通过电流路径110，浪涌电流从主端子22在引线框架36内流动至半导体芯片30的上部。然后，浪涌电流沿厚度方向流过半导体芯片30内之后，在引线框架34内流动至主端子20。通过电流路径112，浪涌电流从主端子22在引线框架36内流动至半导体芯片32的上部。然后，浪涌电流沿厚度方向流过半导体芯片32内之后，在引线框架34内流动至主端子20。
从图3可以明显看出，电流路径112比电流路径110长。因此，电流路径112的寄生电感比电流路径110的寄生电感大。图5是在图2的电路图中添加寄生电感而示出的。图5的电感L1是半导体芯片32与主端子20之间的路径的寄生电感，图5的电感L2是半导体芯片32与主端子22之间的路径的寄生电感，图5的电感L3是半导体芯片30与主端子20之间的路径的寄生电感，图5的电感L4是半导体芯片30与主端子22之间的路径的寄生电感。如上所述，由于电流路径112比电流路径110长，因此寄生电感L1比寄生电感L3大，寄生电感L2比寄生电感L4大。因此，当主端子22的电位相对于主端子20的电位急剧上升时，与二极管16相比，体二极管14中更不易流过浪涌电流。
图6示出了流过本实施方式的半导体模块10的浪涌电流。此外，作为对比例，图7示出了二极管16和体二极管14的电流路径的长度大致相等的半导体模块中流过的浪涌电流。在图6和图7中，均在主端子22的电位急剧上升的时刻t1处，流过二极管16的电流I16急剧上升，同时流过体二极管14的电流I14也急剧上升。即，在二极管16中流过浪涌电流Is16，同时在体二极管14中流过浪涌电流Is14。在时刻t1之后，正向电压较高的体二极管14中的电流逐渐降低至大致为零，正向电压较低的二极管16中的电流逐渐身高至恒定值Ia。在对比例的半导体模块中，由于二极管16和体二极管14的电流路径的长度大致相等(即，寄生电感相等)，因此如图7所示，流过二极管16的浪涌电流Is16和流过体二极管14的浪涌电流Is14大致相等。与此相对，在本实施方式的半导体模块10中，由于体二极管14侧的电流路径的寄生电感比二极管16侧的电流路径的寄生电感大，因此如图6所示，流过体二极管14的浪涌电流Is14比流过二极管16的浪涌电流Is16小。因此，图6中示出的浪涌电流Is14比图7中示出的浪涌电流Is14小。这样，根据本实施方式的半导体模块10，能够抑制流过体二极管14的浪涌电流。
SiC晶体的内部存在基面位错。如果电流流过SiC晶体，则由于基面位错而堆垛层错生长，从而SiC晶体劣化。如果SiC晶体劣化，则SiC晶体的电阻变高。如上所述，根据实施方式的半导体模块10，能够抑制流过体二极管14的浪涌电流。因此，能够抑制构成体二极管14的半导体基板32a(即SiC晶体)的劣化。由此，能够抑制MOSFET 12的导通电阻增加。
另外，在上述实施方式中，半导体芯片30仅具有二极管16。然而，如图8所示，半导体芯片30也可以还具有与二极管16并联连接的绝缘栅双极晶体管18(以下称为IGBT(insulated gate bipolar transistor))。在该结构中，IGBT 18形成在半导体基板30a(参照图4)内。IGBT 18的集电极与阴极电极30b(参照图4)连接，IGBT 18的发射极与阳极电极30c(参照图4)连接。根据该结构，能够通过导通IGBT 18使电流从主端子20流向主端子22。
此外，如图9和图10所示，半导体模块可以还具有半导体芯片35。半导体芯片35具有半导体基板35a、集电极35b、发射极35c、以及信号电极35d。半导体基板35a由硅制成。半导体基板35a中设置有IGBT。集电极35b设置在半导体基板35a的下表面。发射极35c和信号电极35d设置在半导体基板35a的上表面。集电极35b通过软钎焊与引线框架34连接。发射极电极35c通过软钎焊与引线框架36连接。信号电极35d包括IGBT的栅电极以及开尔文发射极。各个信号电极35d经由键合线与对应的信号端子38连接。如图9所示，当沿层叠方向观察引线框架34、半导体芯片30、32、35以及引线框架36时，半导体芯片35配置在半导体芯片30与半导体芯片32之间。通过如上配置半导体芯片35，经由半导体芯片32的电流路径112的长度与经由半导体芯片30的电流路径110的长度之差变得更大。因此，电流路径112的寄生电感相对于电流路径110的寄生电感变得更大。因此，能够进一步抑制流过体二极管14的浪涌电流，从而能够进一步抑制SiC晶体的劣化。
此外，也可以如图11所示，将上臂和下臂集成在一个半导体模块200中。在该情况下，作为半导体模块200，例如，可以采用图12和图13所示的构造。如图12和图13所示，半导体模块200具有引线框架114、116、118、半导体芯片130、132、134、136。引线框架114上连接有半导体芯片130(上臂的二极管16)和半导体芯片132(上臂的MOSFET 12)，半导体芯片130、132上连接有引线框架116的第一部分116a。引线框架116的一部分弯曲，引线框架116的第二部分116b位于与引线框架114大致相同的高度。引线框架116的第二部分116b上连接有半导体芯片134(下臂的二极管16)和半导体芯片136(下臂的MOSFET 12)，半导体芯片134、136上连接有引线框架118。主端子120从引线框架114延伸，主端子122从引线框架116的第二部分116b延伸，主端子124从引线框架118延伸。主端子120、122、124大致平行地延伸，从绝缘树脂40的同一侧面向外侧凸出。从主端子122经由半导体芯片132至主端子120的电流路径的长度与从主端子122经由半导体芯片130至主端子120的电流路径的长度相比更长。因此，在半导体芯片132(即上臂的体二极管14)中不易流过浪涌电流。此外，从主端子124经由半导体芯片136至主端子122的电流路径的长度与从主端子124经由半导体芯片134至主端子122的电流路径的长度相比更长。因此，在半导体芯片136(即下臂的体二极管14)中不易流过浪涌电流。
此外，在上述实施方式中，对逆变电路中使用的半导体模块进行了说明，但也可以将本说明书中公开的技术应用于DC-DC转换电路中使用的半导体模块。图14示出了将半导体模块10用于DC-DC转换电路的例子。图14的DC-DC转换电路具有高电位输入配线300、高电位输出配线302、低电位配线304、以及连接配线306。通过未图示的电源在高电位输入配线300和低电位配线304之间施加直流电压。高电位输入配线300与连接配线306之间连接有电抗器310。高电位输出配线302与连接配线306之间连接有一个半导体模块10。连接配线306与低电位配线304连接有一个半导体模块10。通过各个半导体模块10的MOSFET 12进行整流，高电位输入配线300的电位升压后电位输出到高电位输出配线302。这样，可以将半导体模块10用于DC-DC转换电路。在该情况下，也能够抑制浪涌电流流过体二极管14。
下面对上述实施方式的构成要素与权利要求的构成要素之间的关系进行说明。实施方式的半导体基板32a是权利要求的第一半导体基板的一个例子。实施方式的半导体基板30a是权利要求的第二半导体基板的一个例子。实施方式的电流路径112是权利要求的第一电流路径的一个例子。实施方式的电流路径110是权利要求的第二电流路径的一个例子。实施方式的半导体基板35a是权利要求的第三半导体基板的一个例子。
以下列出本发明公开的技术要素。另外，以下各技术要素能够各自独立地应用。
在本说明书公开的一个例子的半导体模块中，第二半导体基板可以还具备绝缘栅双极晶体管。绝缘栅双极晶体管的集电极可以与阴极电极连接。绝缘栅双极晶体管的发射极可以与阳极电极连接。
本说明书公开的另一个例子的半导体模块可以还具有第三半导体芯片，其具备：第三半导体基板，其具备绝缘栅双极晶体管；集电极，其设置在第三半导体基板的一侧表面上；以及发射极，其设置在第三半导体基板的另一侧表面上。第一引线框架可以与集电极连接。第二引线框架可以与发射极连接。第三半导体芯片可以配置在第一半导体芯片与第二半导体芯片之间。
这样，可以在第一半导体芯片以及第二半导体芯片之外，另行设置具备绝缘栅双极晶体管的第三半导体芯片。此外，根据该结构，由于第三半导体芯片配置在第一半导体芯片与第二半导体芯片之间，因此能够使第一电流路径的长度与第二电流路径的长度之差增大。因此，能够使第一电流路径的寄生电感相对于第二电流路径的寄生电感更大。由此，能够进一步减小流过场效应晶体管的体二极管的浪涌电流。
以上对实施方式进行了详细说明，但其仅为例示，并不限定权利要求书保护的范围。权利要求书所记载的技术包括将以上所例示的具体例进行各种变形、变更后的内容。本说明书或说明书附图中所说明的技术要素能够单独或者通过各种组合而发挥其技术效用，并不限定于申请时权利要求记载的组合。另外，本说明书或说明书附图所例示的技术同时实现了多个目的，但对于仅实现其中一个目的这一点而言也具有技术效果。
标号的说明
10：半导体模块
12：MOSFET
14：体二极管
16：二极管
20：主端子
22：主端子
30：半导体芯片
30a：半导体基板
30b：漏电极
30c：源电极
32：半导体芯片
32a：半导体基板
32b：阴极电极
32c：阳极电极
32d：信号电极
34：引线框架
36：引线框架
38：信号端子
40：绝缘树脂

Claims (3)

1.一种半导体模块，其特征在于，具有：
第一半导体芯片，其具备具有场效应晶体管且由SiC制成的第一半导体基板、设置在所述第一半导体基板的一侧表面上的漏电极、和设置在所述第一半导体基板的另一侧表面上的源电极；
第二半导体芯片，其具备具有二极管的第二半导体基板、设置在所述第二半导体基板的一侧表面上的阴极电极、和设置在所述第二半导体基板的另一侧表面上的阳极电极；
第一引线框架，其具备第一主端子，与所述漏电极和所述阴极电极连接；以及
第二引线框架，其具备第二主端子，与所述源电极和所述阳极电极连接，
从所述第二主端子经由所述第一半导体芯片至所述第一主端子的第一电流路径，与从所述第二主端子经由所述第二半导体芯片至所述第一主端子的第二电流路径相比更长。
2.根据权利要求1所述的半导体模块，其特征在于，所述第二半导体基板还具备绝缘栅双极晶体管，
所述绝缘栅双极晶体管的集电极与所述阴极电极连接，
所述绝缘栅双极晶体管的发射极与所述阳极电极连接。
3.根据权利要求1所述的半导体模块，其特征在于，还具有第三半导体芯片，其具备：第三半导体基板，其具备绝缘栅双极晶体管；集电极，其设置在第三半导体基板的一侧表面上；以及发射极，其设置在第三半导体基板的另一侧表面上，
所述第一引线框架与所述集电极连接，
所述第二引线框架与所述发射极连接，
所述第三半导体芯片配置在所述第一半导体芯片与所述第二半导体芯片之间。
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Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007969A (ja) * 2001-06-27 2003-01-10 Toshiba Corp 半導体モジュール及び電力変換装置
CN101350618A (zh) * 2007-05-31 2009-01-21 富士电机电子技术株式会社 电平移动电路和半导体器件
DE102012209284A1 (de) * 2011-06-03 2012-12-06 Mitsubishi Electric Corp. Halbleitervorrichtung
US20130187627A1 (en) * 2012-01-24 2013-07-25 Fujitsu Limited Semiconductor device and power supply device
JP2013149730A (ja) * 2012-01-18 2013-08-01 Mitsubishi Electric Corp パワー半導体モジュールおよびその製造方法
CN104241259A (zh) * 2013-06-14 2014-12-24 瑞萨电子株式会社 半导体器件和电子器件
CN105359269A (zh) * 2013-07-03 2016-02-24 株式会社电装 半导体装置
CN106449608A (zh) * 2015-08-13 2017-02-22 富士电机株式会社 半导体模块
CN106575645A (zh) * 2014-08-25 2017-04-19 瑞萨电子株式会社 半导体器件及电子装置
CN107112294A (zh) * 2014-11-21 2017-08-29 株式会社电装 半导体装置以及功率模块
JP2018022846A (ja) * 2016-08-05 2018-02-08 株式会社デンソー 半導体装置
CN107851637A (zh) * 2015-07-09 2018-03-27 三菱电机株式会社 功率半导体模块
JP2018186302A (ja) * 2018-08-20 2018-11-22 三菱電機株式会社 半導体装置およびそれを備える半導体モジュール

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305836A (ja) 2006-05-12 2007-11-22 Mitsubishi Electric Corp 電力変換回路
WO2010147202A1 (ja) * 2009-06-19 2010-12-23 株式会社安川電機 電力変換装置
JP5995435B2 (ja) * 2011-08-02 2016-09-21 ローム株式会社 半導体装置およびその製造方法
US9240371B2 (en) * 2011-08-10 2016-01-19 Denso Corporation Semiconductor module, semiconductor device having semiconductor module, and method of manufacturing semiconductor module
JP2016100442A (ja) * 2014-11-20 2016-05-30 日産自動車株式会社 半導体モジュール及び半導体装置
JP6394489B2 (ja) * 2015-05-11 2018-09-26 株式会社デンソー 半導体装置
JP6409733B2 (ja) 2015-10-16 2018-10-24 トヨタ自動車株式会社 半導体装置
JP6690252B2 (ja) * 2016-01-22 2020-04-28 富士電機株式会社 半導体装置
JP6586970B2 (ja) * 2017-03-09 2019-10-09 トヨタ自動車株式会社 半導体装置
JP6760156B2 (ja) * 2017-03-20 2020-09-23 株式会社デンソー 電力変換装置

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007969A (ja) * 2001-06-27 2003-01-10 Toshiba Corp 半導体モジュール及び電力変換装置
CN101350618A (zh) * 2007-05-31 2009-01-21 富士电机电子技术株式会社 电平移动电路和半导体器件
DE102012209284A1 (de) * 2011-06-03 2012-12-06 Mitsubishi Electric Corp. Halbleitervorrichtung
JP2013149730A (ja) * 2012-01-18 2013-08-01 Mitsubishi Electric Corp パワー半導体モジュールおよびその製造方法
US20130187627A1 (en) * 2012-01-24 2013-07-25 Fujitsu Limited Semiconductor device and power supply device
CN104241259A (zh) * 2013-06-14 2014-12-24 瑞萨电子株式会社 半导体器件和电子器件
CN105359269A (zh) * 2013-07-03 2016-02-24 株式会社电装 半导体装置
CN106575645A (zh) * 2014-08-25 2017-04-19 瑞萨电子株式会社 半导体器件及电子装置
CN107112294A (zh) * 2014-11-21 2017-08-29 株式会社电装 半导体装置以及功率模块
CN107851637A (zh) * 2015-07-09 2018-03-27 三菱电机株式会社 功率半导体模块
CN106449608A (zh) * 2015-08-13 2017-02-22 富士电机株式会社 半导体模块
JP2018022846A (ja) * 2016-08-05 2018-02-08 株式会社デンソー 半導体装置
JP2018186302A (ja) * 2018-08-20 2018-11-22 三菱電機株式会社 半導体装置およびそれを備える半導体モジュール

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