CN111081687A - 一种堆叠式芯片封装结构及其封装方法 - Google Patents
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Abstract
本发明公开了一种堆叠式芯片封装结构及其封装方法,该堆叠式芯片封装结构封装方法包括:在将Wafer研磨和切割成单颗Die之后,使用重新布线层工艺将芯片的顶部焊盘延伸至侧面以生成侧面焊盘;使用固晶胶依次将芯片贴装堆叠至封装基板上以实现粘结固化;使用焊线将各层芯片的侧面焊盘以及封装基板的焊盘相连。本发明实现了不需要通过FOW方式进行芯片之间的粘结固化,从而减薄了封装体的厚度,还可以取消芯片之间错位阶梯上升形式,实现了减少封装体整体封装面积,具有广阔的市场应用前景。
Description
技术领域
本发明涉及芯片封装技术领域,尤其涉及一种堆叠式芯片封装结构及其封装方法。
背景技术
封装技术是一种将集成电路用绝缘的塑料或陶瓷材料打包的技术。以CPU为例,实际看到的体积和外观并不是真正的CPU内核的大小和面貌,而是CPU内核等元件经过封装后的产品。封装技术对于芯片来说是必须的,也是至关重要的。因为芯片必须与外界隔离,以防止空气中的杂质对芯片电路的腐蚀而造成电气性能下降。另一方面,封装后的芯片也更便于安装和运输。由于封装技术的好坏还直接影响到芯片自身性能的发挥和与之连接的PCB(印制电路板)的设计和制造,因此它是至关重要的。
目前,传统的芯片封装方法主要包括两种方式:第一种为第一层使用普通DAF(一种固晶胶)连接Flash/Dram和Substrate(封装基板),从第二层开始对位上升垂直堆叠,为避免下层线体受到影响,通过使用FOW(Film on wire)方式将线体埋入FOW(Film onwire),同时达到各层Flash/Dram与基板相连目的。这种方法由于FOW存在,导致整个芯片封装厚度增加。
第二种为各层均使用普通DAF将Flash/Dram和Substrate(封装基板)连接,但需要采用各层Flash/Dram,DAF位置错开阶梯上升形式以完成焊线。这种方法由于阶梯错位上升,导致芯片封装面积较大。此外,上述两种封装结构的焊线较长且工艺较为复杂。
发明内容
基于此,有必要针对上述技术问题,提供一种可以实现减薄整体封装厚度以及减少芯片封装面积的堆叠式芯片封装结构及其封装方法。
一种堆叠式芯片封装结构,其特征在于,所述堆叠式芯片封装结构包括:
封装基板以及多个芯片,所述多个芯片依次堆叠于所述封装基板上;
所述封装基板与所述多个芯片中的底层芯片通过固晶胶粘结固化;
所述多个芯片之间分别通过固晶胶粘结固化;
其中,所述芯片的顶部焊盘延伸至所述芯片的侧面形成侧面焊盘,所述基板的焊盘与所述芯片的侧面焊盘通过焊线连接。
在其中一个实施例中,所述多个芯片垂直堆叠于所述封装基板上,且所述多个基板之间在垂直方向上无相对移位。
在其中一个实施例中,相邻芯片的侧面焊盘分别依次通过焊线连接,所述封装基板的焊盘与所述底层芯片的侧面焊盘通过焊线连接。
在其中一个实施例中,所述堆叠式芯片封装结构还包括:表面贴装器件,所述表面贴装器件焊接与所述封装基板上。
在其中一个实施例中,所述堆叠式芯片封装结构还包括:controller,所述controller的焊盘与所述封装基板的焊盘通过焊线连接。
一种堆叠式芯片封装结构封装方法,所述方法用于封装如上述任一项所述的堆叠式芯片封装结构包括:
在将Wafer研磨和切割成单颗Die之后,使用重新布线层工艺将芯片的顶部焊盘延伸至侧面以生成侧面焊盘;
使用固晶胶依次将芯片贴装堆叠至封装基板上以实现粘结固化;
使用焊线将各层芯片的侧面焊盘以及封装基板的焊盘相连。
在其中一个实施例中,在所述使用固晶胶依次将芯片贴装堆叠至封装基板上以实现粘结固化的步骤之前还包括:
将表面贴装器件以及controller贴装在所述封装基板上。
在其中一个实施例中,在所述使用焊线将各层芯片的侧面焊盘以及封装基板的焊盘相连的步骤之后还包括:
对封装后的芯片进行封胶。
本发明提供的堆叠式芯片封装结构,通过将芯片的顶部焊盘延伸至侧面,将焊线的位置从顶部转移至侧面,不需要通过FOW方式进行芯片之间的粘结固化,从而减薄了封装体的厚度。此外,还可以取消芯片之间错位阶梯上升形式,实现了减少封装体整体封装面积,具有广阔的市场应用前景。
本发明提供的堆叠式芯片封装结构封装方法,通过使用重新布线层工艺将芯片的顶部焊盘延伸至侧面以生成侧面焊盘,实现了不需要通过FOW方式进行芯片之间的粘结固化,从而减薄了封装体的厚度,还可以取消芯片之间错位阶梯上升形式,实现了减少封装体整体封装面积。此外,该工艺进行封装的过程中焊线较短,工艺流程与传统技术相比更加简便。
附图说明
为了更清楚地说明本发明实施例技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为传统技术中堆叠式芯片封装结构的结构示意图;
图2为传统技术中另一堆叠式芯片封装结构的结构示意图;
图3为一实施例中堆叠式芯片封装结构的结构示意图;
图4为一实施例中堆叠式芯片封装结构封装方法的流程示意图;
图5为另一实施例中堆叠式芯片封装结构封装方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图,对实施例中的技术方案进行清楚、完整地描述,附图中类似的组件标号代表类似的组件。
应当理解,当在本说明书和所附权利要求书中使用时,术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在,但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解,在此本发明实施例说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本发明实施例。如在本发明实施例说明书和所附权利要求书中所使用的那样,除非上下文清楚地指明其它情况,否则单数形式的“一”、“一个”及“该”意在包括复数形式。
在现有技术中,芯片封装方法主要包括以下两种方式:
具体地,以4层存储芯片封装为例,如图1所示,第一种为第一层使用普通DAF(一种固晶胶)(14)连接Flash/Dram(15)和Substrate(封装基板)(11),从第二层开始对位上升垂直堆叠,为避免下层线体(17)受到影响,使用FOW(Film onwire)(16)方式,将线体埋入FOW(Film on wire)(16),同时达到各层Flash/Dram(15)与基板(11)相连目的。
如图2所示,第二种为各层均使用普通DAF(14)将Flash/Dram(15)和Substrate(封装基板)(11)连接,但需要采用各层Flash/Dram(15),DAF(14)位置错开阶梯上升形式以完成焊线(17)。
然而,第一种封装方式由于FOW(16)存在,导致整个芯片封装厚度增加;第二种封装方式由于阶梯错位上升,导致封装面积较大;此外,两种封装结构的焊线较长且工艺较复杂。基于此,本发明提出一种新的堆叠式芯片封装结构及其封装方法,旨在可以实现减薄整体封装厚度以及减少芯片封装面积。
在一个实施例中,提供了一种堆叠式芯片封装结构,所述堆叠式芯片封装结构包括:
封装基板以及多个芯片,所述多个芯片依次堆叠于所述封装基板上;
所述封装基板与所述多个芯片中的底层芯片通过固晶胶粘结固化;
所述多个芯片之间分别通过固晶胶粘结固化;
其中,所述芯片的顶部焊盘延伸至所述芯片的侧面形成侧面焊盘,所述基板的焊盘与所述芯片的侧面焊盘通过焊线连接。
需要说明的是,本实施例中提供的封装结构包含但不限于存储类芯片封装,任何采用此方法实现堆叠的芯片封装都包含在本结构之内,具体地,参考图3以Flash/Dram芯片进行举例说明。
在一个实施例中,所述多个芯片垂直堆叠于所述封装基板上,且所述多个基板之间在垂直方向上无相对移位。
具体地,每个Flash/Dram芯片依次堆叠在封装基板上。例如:图3中所示包括4个Flash/Dram芯片,这4个Flash/Dram芯片依次垂直堆叠在封装基板上,彼此对齐且在垂直方向上无相对移位,这样可以保证最后的封装面积最小。各个芯片之间通过普通DAF粘结固化,最底层的芯片也是通过普通DAF粘结固化在封装基板上。
在每个Flash/Dram芯片上,通过使用RDL(重新布线层)(33)工艺将顶部焊线PAD(32)延伸至侧面,生成侧面焊线PAD(34)。这种封装结构可以将FOW全部取代成普通DAF从而减薄封装体厚度。具体地,(FOW厚度-普通DAF厚度)x(N-1),N=Flash/Dram(15)层数,以4层封装,FOW为60um,DAF10um为例,可减薄整体封装厚度150um。此外,将Flash/Dram(15)顶部焊线PAD延伸至侧面,将焊线位置从顶部转移到侧面,针对图2封装结构可以取消错位阶梯上升形式,减少封装体整体封装面积。
在上述实施例中,通过将芯片的顶部焊盘延伸至侧面,将焊线的位置从顶部转移至侧面,不需要通过FOW方式进行芯片之间的粘结固化,从而减薄了封装体的厚度。此外,还可以取消芯片之间错位阶梯上升形式,实现了减少封装体整体封装面积,具有广阔的市场应用前景。
在一个实施例中,相邻芯片的侧面焊盘分别依次通过焊线连接,所述封装基板的焊盘与所述底层芯片的侧面焊盘通过焊线连接。
具体地,结合图3所示,分别将相邻的Flash/Dram(15)上的侧面焊线PAD(34)通过焊线连接,然后最底层的Flash/Dram(15)上的侧面焊线PAD(34)通过焊线与封装基板的焊盘连接。这种连接方式的焊线最短,且工艺更加简便。
在一个实施例中,所述堆叠式芯片封装结构还包括:表面贴装器件,所述表面贴装器件焊接与所述封装基板上。
在一个实施例中,所述堆叠式芯片封装结构还包括:controller,所述controller的焊盘与所述封装基板的焊盘通过焊线连接。
具体地,结合图3所示,分别将SMD(12)和Controller(13)贴装在封装基板上,已完成整个封装结构的封装。
在一个实施例中,如图4所示,提供了一种堆叠式芯片封装结构封装方法,所述方法用于封装如上述任一项所述的堆叠式芯片封装结构包括:
步骤402,在将Wafer研磨和切割成单颗Die之后,使用重新布线层工艺将芯片的顶部焊盘延伸至侧面以生成侧面焊盘;
步骤404,使用固晶胶依次将芯片贴装堆叠至封装基板上以实现粘结固化;
步骤406,使用焊线将各层芯片的侧面焊盘以及封装基板的焊盘相连。
具体地,在本实施例中,首先在将Wafer研磨和切割成单颗Die之后,使用重新布线层工艺将芯片的顶部焊盘延伸至侧面以生成侧面焊盘。接着,使用固晶胶依次将芯片贴装堆叠至封装基板上以实现粘结固化。最后,使用焊线将各层芯片的侧面焊盘以及封装基板的焊盘相连。本实施例实现了不需要通过FOW方式进行芯片之间的粘结固化,从而减薄了封装体的厚度,还可以取消芯片之间错位阶梯上升形式,实现了减少封装体整体封装面积。此外,该工艺进行封装的过程中焊线较短,工艺流程与传统技术相比更加简便。
在一个实施例中,如图5所示,提供了一种堆叠式芯片封装结构封装方法,所述方法用于封装如上述任一项所述的堆叠式芯片封装结构包括:
步骤502,在将Wafer研磨和切割成单颗Die之后,使用重新布线层工艺将芯片的顶部焊盘延伸至侧面以生成侧面焊盘;
步骤504,将表面贴装器件以及controller贴装在封装基板上;
步骤506,使用固晶胶依次将芯片贴装堆叠至封装基板上以实现粘结固化;
步骤508,使用焊线将各层芯片的侧面焊盘以及封装基板的焊盘相连。
步骤510,对封装后的芯片进行封胶。
具体地,结合参考图3所示的封装结构,本实施例提供的封装方法具体包括:
1.在将Wafer研磨和切割成单颗Die之后,使用RDL(重新布线层)(33)工艺将顶部焊线PAD(32)延伸至侧面,生成侧面焊线PAD(34)。
2.SMD(12)和Controller(13)贴装。
3.使用普通DAF(14)代替FOW(16)将Flash/Dram(15)和Substrate(封装基板)(11)连接固化,使用焊线(35)将各层侧面焊线PAD(34)以及基板焊线PAD相连。
4.针对图2使用Flash/Dram(15)+DAF(14)位置错开阶梯上升封装,可取消错位,采用对位上升使用焊线(35)将各层侧面焊线PAD(34)以及基板焊线PAD相连。
5.此封装结构和方法可减薄芯片封装厚度或封装面积,达到轻薄短小目的,另外焊线(35)长度缩短,节约焊线成本。
需要说明的是,此封装工艺包含但不限于对存储类芯片进行封装,任何采用此方法实现堆叠的芯片封装都包含在本方法之内。
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详细描述的部分,可以参见其他实施例的相关描述。
以上所述,为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到各种等效的修改或替换,这些修改或替换都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以权利要求的保护范围为准。
Claims (8)
1.一种堆叠式芯片封装结构,其特征在于,所述堆叠式芯片封装结构包括:
封装基板以及多个芯片,所述多个芯片依次堆叠于所述封装基板上;
所述封装基板与所述多个芯片中的底层芯片通过固晶胶粘结固化;
所述多个芯片之间分别通过固晶胶粘结固化;
其中,所述芯片的顶部焊盘延伸至所述芯片的侧面形成侧面焊盘,所述基板的焊盘与所述芯片的侧面焊盘通过焊线连接。
2.如权利要求1所述的堆叠式芯片封装结构,其特征在于,所述多个芯片垂直堆叠于所述封装基板上,且所述多个基板之间在垂直方向上无相对移位。
3.如权利要求1所述的堆叠式芯片封装结构,其特征在于,相邻芯片的侧面焊盘分别依次通过焊线连接,所述封装基板的焊盘与所述底层芯片的侧面焊盘通过焊线连接。
4.如权利要求1所述的堆叠式芯片封装结构,其特征在于,所述堆叠式芯片封装结构还包括:表面贴装器件,所述表面贴装器件焊接与所述封装基板上。
5.如权利要求4所述的堆叠式芯片封装结构,其特征在于,所述堆叠式芯片封装结构还包括:controller,所述controller的焊盘与所述封装基板的焊盘通过焊线连接。
6.一种堆叠式芯片封装结构封装方法,其特征在于,所述方法用于封装如权利要求1-5任一项所述的堆叠式芯片封装结构包括:
在将Wafer研磨和切割成单颗Die之后,使用重新布线层工艺将芯片的顶部焊盘延伸至侧面以生成侧面焊盘;
使用固晶胶依次将芯片贴装堆叠至封装基板上以实现粘结固化;
使用焊线将各层芯片的侧面焊盘以及封装基板的焊盘相连。
7.如权利要求6所述的堆叠式芯片封装结构封装方法,其特征在于,在所述使用固晶胶依次将芯片贴装堆叠至封装基板上以实现粘结固化的步骤之前还包括:
将表面贴装器件以及controller贴装在所述封装基板上。
8.如权利要求7所述的堆叠式芯片封装结构封装方法,其特征在于,在所述使用焊线将各层芯片的侧面焊盘以及封装基板的焊盘相连的步骤之后还包括:
对封装后的芯片进行封胶。
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