CN110993585A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN110993585A
CN110993585A CN201910890865.2A CN201910890865A CN110993585A CN 110993585 A CN110993585 A CN 110993585A CN 201910890865 A CN201910890865 A CN 201910890865A CN 110993585 A CN110993585 A CN 110993585A
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China
Prior art keywords
connection
layers
layer
redistribution
semiconductor package
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CN201910890865.2A
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English (en)
Inventor
陈韩娜
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110993585A publication Critical patent/CN110993585A/zh
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Abstract

本发明提供了一种半导体封装件，所述半导体封装件包括：连接结构，具有彼此背对的第一表面和第二表面，并且包括多个绝缘层、多个重新分布层以及多个连接过孔；至少一个半导体芯片，位于所述第一表面上并且具有电连接到所述多个重新分布层的连接垫；包封剂，位于所述第一表面上并且包封所述至少一个半导体芯片；以及UBM层，包括位于所述第二表面上的UBM垫以及连接重新分布层和所述UBM垫的UBM过孔。与所述第一表面相邻的至少一个连接过孔具有朝向所述第二表面变窄的渐缩结构，并且其他连接过孔和所述UBM过孔具有朝向所述第一表面变窄的渐缩结构。

Description

半导体封装件
本申请要求于2018年10月2日在韩国知识产权局提交的第10-2018-0117697号韩国专利申请的优先权的权益，该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本公开涉及一种半导体封装件。
背景技术
随着装置的规格的改进和高带宽存储器(HBM)的使用，中介体市场已经增长。目前，硅主要用作中介体的材料，但为了增大面积并且降低成本，已经进行了玻璃或有机方法的开发。
此外，中介体封装件通过执行将裸片附着到中介体并且对裸片进行模制的封装工艺来制造，并且在安装半导体芯片之前制造将要用作中介体并且具有重新分布层的连接结构。然而，在用于这种连接结构的重新分布层的构建工艺中，可能发生严重的起伏。特别是，难以保持随后将要形成的重新分布层的关键尺寸。结果，封装件的可靠性可能显著下降。
发明内容
本公开的一方面可提供一种半导体封装件，在所述半导体封装件中可解决在连接结构的构建工艺中出现的起伏问题。
根据本公开的一方面，一种半导体封装件可包括：连接结构，具有彼此背对的第一表面和第二表面，并且包括多个绝缘层、分别设置在所述多个绝缘层上的多个重新分布层以及分别穿透所述多个绝缘层并且连接到所述多个重新分布层的多个连接过孔；至少一个半导体芯片，设置在所述连接结构的所述第一表面上，并且具有电连接到所述多个重新分布层的连接垫；包封剂，设置在所述连接结构的所述第一表面上并且包封所述至少一个半导体芯片；以及凸块下金属(UBM)层，包括设置在所述连接结构的所述第二表面上的UBM垫以及将所述UBM垫和所述多个重新分布层之中的与所述连接结构的所述第二表面相邻的重新分布层彼此连接的UBM过孔。所述多个连接过孔之中的与所述第一表面相邻的至少一个连接过孔可具有朝向所述第二表面变窄的渐缩结构，并且所述多个连接过孔中的其他连接过孔和所述UBM过孔可具有朝向所述第一表面变窄的渐缩结构。
根据本公开的另一方面，一种半导体封装件可包括：连接结构，具有彼此背对的第一表面和第二表面，并且包括多个绝缘层、分别设置在所述多个绝缘层上的多个重新分布层以及分别穿透所述多个绝缘层并且连接到所述多个重新分布层的多个连接过孔；至少一个半导体芯片，设置在所述连接结构的所述第一表面上，并且具有电连接到所述多个重新分布层的连接垫；包封剂，设置在所述连接结构的所述第一表面上并且包封所述至少一个半导体芯片；UBM层，设置在所述连接结构的所述第二表面上并且电连接到所述多个重新分布层；以及钝化层，设置在所述连接结构的所述第二表面上并且使所述UBM层的至少一部分嵌入。所述多个绝缘层可包括相同的绝缘材料，所述多个连接过孔之中的与所述第一表面相邻的至少一个连接过孔可具有朝向所述第二表面变窄的渐缩结构，并且所述多个连接过孔中的其他连接过孔可具有朝向所述第一表面变窄的渐缩结构。
根据本公开的另一方面，一种半导体封装件可包括：连接结构，包括绝缘层、分别设置在所述绝缘层上的重新分布层以及分别穿透所述绝缘层并且连接到所述重新分布层的连接过孔层；以及半导体芯片，设置在所述连接结构上并且具有电连接到所述重新分布层的连接垫。所述连接过孔层之中的第一连接过孔层和所述连接过孔层之中的第二连接过孔层可以在相反方向上渐缩。
附图说明
通过下面结合附图进行的详细描述，本公开的以上和其他方面、特征和优点将被更清楚地理解，在附图中：
图1是示出电子装置系统的示例的示意性框图；
图2是示出电子装置的示例的示意性透视图；
图3是示出三维(3D)球栅阵列(BGA)封装件安装在电子装置的主板上的情况的示意性截面图；
图4是示出2.5D硅中介体封装件安装在主板上的情况的示意性截面图；
图5是示出2.5D有机中介体封装件安装在主板上的情况的示意性截面图；
图6是示出根据本公开中的示例性实施例的半导体封装件的示意性截面图；
图7是沿着图6的半导体封装件的I-I'线截取的平面图；
图8是图6的半导体封装件的“A”部分的放大截面图；
图9A至图9F是用于描述在制造图6中所示的半导体封装件的方法中的制造连接结构的主要工艺的截面图；
图10A至图10C是用于描述在制造图6中所示的半导体封装件的方法中的安装半导体芯片的主要工艺的截面图；
图11是示出根据本公开中的另一示例性实施例的半导体封装件的示意性截面图；并且
图12是沿着图11的半导体封装件的II-II'线截取的平面图。
具体实施方式
在下文中，将参照附图描述本公开中的示例性实施例。在附图中，为了清楚起见，可夸大或缩小组件的形状、尺寸等。
这里，为了方便起见，下侧、下部、下表面等用于指相对于附图的截面的向下的方向，而上侧、上部、上表面等用于指与向下的方向相反的方向。然而，这些方向是为了便于解释而定义的，并且权利要求不受如上所述定义的方向的具体限制，并且上部和下部的概念可彼此互换。
在说明书中，组件与另一组件的“连接”的含义在概念上包括两个组件之间通过粘合层的间接连接以及两个组件之间的直接连接。此外，“电连接”在概念上包括物理连接和物理断开。可理解的是，当使用诸如“第一”和“第二”的术语来提及元件时，该元件不由此受限。术语可仅用于将该元件与其他元件相区分的目的，并且可不限制元件的顺序或重要性。在一些情况下，在不脱离这里阐述的权利要求的范围的情况下，第一元件可被称为第二元件，类似地，第二元件也可被称为第一元件。
这里使用的术语“示例性实施例”不指同一示例性实施例，而是被提供来突出与另一示例性实施例的特征或特性不同的特定特征或特定特性。然而，这里提供的示例性实施例被认为能够通过彼此全部或部分组合来实现。例如，除非在其中提供相反或矛盾的描述，否则在特定示例性实施例中描述的一个元件即使未在另一示例性实施例中描述，其也可被理解为与另一示例性实施例相关的描述。
这里使用的术语仅用于描述示例性实施例而不限制本公开。在这种情况下，除非在上下文中另有解释，否则单数形式包括复数形式。
电子装置
图1是示出电子装置系统的示例的示意性框图。
参照图1，电子装置1000可将主板1010容纳在其中。主板1010可包括物理连接或者电连接到其的芯片相关组件1020、网络相关组件1030、其他组件1040等。这些组件可通过各种信号线1090连接到以下将描述的其他组件。
芯片相关组件1020可包括：存储器芯片，诸如易失性存储器(例如，动态随机存取存储器(DRAM))、非易失性存储器(例如，只读存储器(ROM))、闪存等；应用处理器芯片，诸如中央处理器(例如，中央处理单元(CPU))、图形处理器(例如，图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等；以及逻辑芯片，诸如模拟数字转换器(ADC)、专用集成电路(ASIC)等。然而，芯片相关组件1020不限于此，而是还可包括其他类型的芯片相关组件。此外，芯片相关组件1020可彼此组合。
网络相关组件1030可包括被指定为根据诸如以下的协议操作的组件：无线保真(Wi-Fi)(电气和电子工程师协会(IEEE)802.11族等)、全球微波接入互操作性(WiMAX)(IEEE 802.16族等)、IEEE 802.20、长期演进(LTE)、演进数据最优化(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入+(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任意其他无线协议和有线协议。然而，网络相关组件1030不限于此，而是还可包括被指定为根据各种其他无线标准或协议或者有线标准或协议操作的组件。此外，网络相关组件1030可与上述芯片相关组件1020一起彼此组合。
其他组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而，其他组件1040不限于此，而是还可包括用于各种其他目的的无源组件等。此外，其他组件1040可与上述芯片相关组件1020或网络相关组件1030一起彼此组合。
根据电子装置1000的类型，电子装置1000可包括可物理连接或电连接到主板1010或者可不物理连接或电连接到主板1010的其他组件。这些其他组件可包括例如相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储单元(例如，硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)、数字通用光盘(DVD)驱动器(未示出)等。然而，这些其他组件不限于此，而是还可根据电子装置1000的类型等而包括用于各种目的的其他组件。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字摄像机、数码相机、网络系统、计算机、监视器、平板PC、膝上型PC、上网本PC、电视机、视频游戏机、智能手表、汽车组件等。然而，电子装置1000不限于此，而可以是处理数据的任意其他电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2，半导体装置可在如上所述的各种电子装置1000中用于各种目的。例如，母板1110可容纳在智能电话1100的主体1101中，并且各种电子组件1120可物理连接或者电连接到母板1110。此外，可物理连接或电连接到母板1110或者可不物理连接或电连接到母板1110的其他组件(诸如，相机模块1130)可容纳在主体1101中。电子组件1120中的一些可以是芯片相关组件，芯片相关组件中的一些可以是半导体装置100。此外，电子装置不必然地局限于智能电话1100，而可以是其他电子装置。
半导体装置(或半导体封装件)
通常，半导体芯片中集成了大量的微电子电路。然而，半导体芯片本身可能无法用作成品的半导体产品，并且可能由于外部的物理冲击或者化学冲击而损坏。因此，半导体芯片本身不被使用，而是被封装并且在封装的状态下在电子装置等中使用。
需要半导体封装的原因在于：就电连接而言，半导体芯片和电子装置的主板之间的电路宽度存在差异。详细地，半导体芯片的连接垫(pad，或称为“焊盘”或“焊垫”)的尺寸和半导体芯片的连接垫之间的间距非常细小，而在电子装置中使用的主板的组件安装垫的尺寸和主板的组件安装垫之间的间距显著大于半导体芯片的连接垫的尺寸和半导体芯片的连接垫之间的间距。因此，可能难以将半导体芯片直接安装在主板上，因此需要用于缓解半导体芯片和主板之间的电路宽度的差异的封装技术。
在下文中，将参照附图更详细地描述通过上述封装技术制造的半导体装置。
图3是示出三维(3D)球栅阵列(BGA)封装件安装在电子装置的主板上的情况的示意性截面图。
半导体芯片之中的诸如图形处理单元(GPU)的专用集成电路(ASIC)非常昂贵，因此以高良率对ASIC执行封装非常重要。为此目的，在安装半导体芯片之前，准备可使数千至数十万个连接垫重新分布的球栅阵列(BGA)基板2210等，并且通过表面安装技术(SMT)等将诸如GPU 2220的昂贵的半导体芯片安装并且封装在BGA基板2210上，然后，将诸如GPU 2220的昂贵的半导体芯片最终安装在主板2110上。
此外，在GPU 2220的情况下，需要使GPU 2220与诸如高带宽存储器(HBM)的存储器之间的信号路径显著减小。为此，使用了诸如HBM 2240的半导体芯片安装并随后封装在中介体2230上然后按照叠层封装(POP)形式堆叠在其中安装有GPU 2220的封装件上的产品。然而，在这种情况下，装置的厚度过度增加，并且在使信号路径显著减小方面存在限制。
图4是示出2.5D硅中介体封装件安装在主板上的情况的示意性截面图。
作为用于解决上述问题的方法，可考虑通过将诸如GPU 2220的第一半导体芯片和诸如HBM 2240的第二半导体芯片彼此并排地表面安装在硅中介体2250上并且对其进行封装的2.5D中介体技术来制造半导体装置2310。在这种情况下，具有数千至数十万个连接垫的GPU 2220和HBM 2240可通过硅中介体2250重新分布并且可以以最短路径彼此电连接。此外，当半导体装置2310再次安装在BGA基板2210等上并且重新分布时，半导体装置2310可最终安装在主板2110上。然而，非常难以在硅中介体2250中形成硅通孔(TSV)，并且用于制造硅中介体2250所需的成本非常高，因此硅中介体2250不利于增大面积和降低成本。
图5是示出2.5D有机中介体封装件安装在主板上的情况的示意性截面图。
作为用于解决上述问题的方法，可考虑使用有机中介体2260代替硅中介体2250。例如，可考虑通过将诸如GPU 2220的第一半导体芯片和诸如HBM 2240的第二半导体芯片彼此并排地表面安装在有机中介体2260上然后对其进行封装的2.5D中介体技术来制造半导体装置2320。在这种情况下，具有数千至数十万个连接垫的GPU 2220和HBM 2240可通过有机中介体2260重新分布，并且可以以最短路径彼此电连接。此外，当半导体装置2320再次安装在BGA基板2210等上并且重新分布时，半导体装置2320可最终安装在主板2110上。此外，有机中介体可有利于增大面积和降低成本。
此外，这种半导体装置2320通过执行在有机中介体2260上安装芯片2220和2240并对芯片进行模制的封装工艺来制造。原因在于，当没有执行模制工艺时，半导体装置没有被处理，使得半导体装置可能无法连接到BGA基板2210等。因此，通过模制保持半导体装置的刚性。然而，当执行模制工艺时，由于如上所述的有机中介体2260的热膨胀系数(CTE)与芯片2220和2240的模制材料的热膨胀系数(CTE)之间不匹配，因此可能发生半导体装置的翘曲，可能使底部填充树脂的填充性劣化，并且有机中介体2260与芯片2220和2240的模制材料之间可能出现裂纹。
在下文中，将参照附图详细地描述本公开中的各种示例性实施例。
图6是示出根据本公开中的示例性实施例的半导体封装件的示意性截面图，并且图7是沿着图6的半导体封装件的I-I'线截取的平面图。
参照图6和图7，根据本示例性实施例的半导体封装件100A可包括：连接结构120，具有彼此背对的第一表面120A和第二表面120B；第一半导体芯片111、第二半导体芯片112和第三半导体芯片113，设置在连接结构120的第一表面120A上；以及包封剂160，设置在连接结构120的第一表面120A上并且包封第一半导体芯片111、第二半导体芯片112和第三半导体芯片113。
连接结构120可用作封装半导体芯片的中介体，以将半导体封装件100A安装在主板上。连接结构120可包括：多个绝缘层121；多个重新分布层122，分别设置在多个绝缘层121中的相应绝缘层上；以及多个连接过孔123，分别穿透多个绝缘层121中的相应绝缘层并且分别连接到多个重新分布层122中的相应重新分布层。多个重新分布层122之中的位于连接结构的第一表面上的连接重新分布层122”可被设置为连接到第一半导体芯片111的连接垫111P、第二半导体芯片112的连接垫112P和第三半导体芯片113的连接垫113P中的每个的连接布线层。连接重新分布层122”的厚度可大于其他重新分布层122中的每个的厚度。
第一半导体芯片111的连接垫111P、第二半导体芯片112的连接垫112P和第三半导体芯片113的连接垫113P可利用连接构件135分别电连接到多个重新分布层122中的连接重新分布层122”。连接构件135中的每个可利用诸如锡(Sn)的低熔点金属或包括锡(Sn)的合金形成。
此外，半导体封装件100A可包括底部填充树脂170，底部填充树脂170设置在第一半导体芯片111的其上形成有连接垫111P的表面(在下文中，称为有效表面)、第二半导体芯片112的其上形成有连接垫112P的表面(在下文中，称为有效表面)和第三半导体芯片113的其上形成有连接垫113P的表面(在下文中，称为有效表面)与连接结构120的第一表面120A之间。底部填充树脂170可将第一半导体芯片111、第二半导体芯片112和第三半导体芯片113稳定地固定到连接结构120上。例如，底部填充树脂170可以是诸如环氧树脂等的热固性树脂。
包封剂160可形成为使得第一半导体芯片111的上表面、第二半导体芯片112的上表面和第三半导体芯片113的上表面通过包封剂160的上表面暴露。热可通过暴露的上表面容易地散发。半导体芯片111、112和113的上表面以及包封剂160的上表面可通过抛光工艺彼此基本共面。半导体封装件100A不限于此，并且可被修改为具有另外引入散热板(参见图11)或围绕半导体芯片的其他加强构件的各种形式。
凸块下金属(UBM)层145可包括设置在连接结构120的第二表面120B上的UBM垫(pad，或称为“焊盘”或“焊垫”)142以及将多个重新分布层122之中的与连接结构120的第二表面120B相邻的重新分布层122'和UBM垫142彼此连接的UBM过孔143。
图8是图6的半导体封装件的“A”部分的放大截面图。
参照图6和图8，在本示例性实施例中使用的多个连接过孔123可关于一个中间重新分布层122P(在下文中，称为“中间重新分布层122P”)具有不同的形成方向。详细地，多个连接过孔123之中的与第一表面120A相邻的连接过孔123”可具有其朝向第二表面120B变窄的渐缩结构，而多个连接过孔123中的其他连接过孔123'可具有其朝向第一表面120A变窄的渐缩结构。换句话说，与第一表面120A相邻的连接过孔123”可被表示为具有比上部直径(或上部宽度)db小的下部直径(或下部宽度)da，而其他连接过孔123'可被表示为具有比上部直径(或上部宽度)d2大的下部直径(或下部宽度)d1。
此外，类似于其他连接过孔123'，UBM过孔143也可具有其朝向第一表面120A变窄的渐缩结构。
朝向第二表面120B变窄的连接过孔123”可以是连接到连接重新分布层122”的最上方的连接过孔，并且举例说明了仅一个层的连接过孔123”在同一方向上渐缩的情况，但是与第一表面120A相邻的两个或更多个层的连接过孔可具有使其朝向第二表面120B变窄的渐缩结构。然而，为了充分地缓解起伏，变为朝向第二表面120B渐缩的连接过孔123”可被设计为具有的层数与其他连接过孔123'的层数相同或比其他连接过孔123'的层数少。
连接过孔123'和123”的不同的形成方向可通过在重新分布层122的构建工艺中利用附加载体基板引入转移工艺来实现(见图9A至图9F)。在将所得结构转移到附加载体基板之前执行的主重新分布层的构建工艺中，UBM垫142可设置在最上方的高度上，因此与UBM垫142位于构建结构下方的高度的情况相比，可显著缓解起伏问题。此外，由于多个绝缘层121中的每个包括有机材料，因此当在构建工艺中UBM垫142位于重新分布层122下方的高度上时，可能发生起伏问题，并且如图8中所示，UBM垫142的厚度t0可大于重新分布层122的厚度t1。因此，这种问题可能发生地更严重。然而，根据本示例性实施例的结构可被理解为显著缓解这种起伏问题的工艺(即，在初始构建工艺中在最上方的高度上形成UBM垫142的工艺)的所得结构。
在本示例性实施例中，UBM过孔143的下部的直径(或宽度)d0可大于多个连接过孔123中的每个的下部的直径(或宽度)d1。然而，UBM过孔143的下部的直径(或宽度)d0不限于此。在一些示例性实施例中，即使UBM过孔143的下部的直径(或宽度)d0不大于多个连接过孔122中的每个的下部的直径(或宽度)d1，并且UBM过孔143的下部的直径(或宽度)d0与多个连接过孔122中的每个的下部的直径(或宽度)d1相同或比多个连接过孔122中的每个的下部的直径(或宽度)d1小，也可形成与一个UBM垫相关联的多个UBM过孔。
在本示例性实施例中使用的UBM垫142可与UBM过孔143具有一体化结构。位于连接结构120的第一表面120A上的连接重新分布层122”可同与其相邻的连接过孔123”具有一体化结构。
在本说明书中，术语“一体化结构”并不意味着两个组件彼此简单地接触，而是指两个组件使用相同材料通过同一工艺彼此一体地形成的结构。例如，当通过同一镀覆工艺一起形成图案(重新分布层或垫)和过孔时，过孔和图案可被称为一体化结构。
根据本示例性实施例的半导体封装件100A可包括钝化层141，钝化层141设置在连接结构120的第二表面120B上并且使UBM垫142的至少一部分嵌入。
钝化层141可围绕UBM垫142的侧表面，以使UBM垫142的一个表面被暴露。详细地，如图6所示，钝化层141可使UBM垫142的下表面被暴露，并且在这种情况下，UBM垫142的下表面可与钝化层141的下表面基本上彼此共面。在另一示例性实施例中，钝化层141可形成为使得UBM垫142的与UBM垫142的暴露的一个表面相邻的侧表面也部分地暴露(参见图11)。钝化层141可保护连接结构120免受外部的物理损坏或化学损坏。
在下文中，将更详细地描述包括在根据本示例性实施例的半导体封装件100A中的各个组件。
连接结构120可使第一半导体芯片111的连接垫111P、第二半导体芯片112的连接垫112P和第三半导体芯片113的连接垫113P重新分布。第一半导体芯片111的具有各种功能的数千至数十万个连接垫111P、第二半导体芯片112的具有各种功能的数千至数十万个连接垫112P以及第三半导体芯片113的具有各种功能的数千至数十万个连接垫113P可通过连接结构120重新分布，并且可根据功能通过电连接金属件150物理连接到或电连接到外部。此外，第一半导体芯片111的连接垫111P、第二半导体芯片112的连接垫112P和第三半导体芯片113的连接垫113P可通过连接结构120以最短路径彼此电连接。连接结构120可包括：多个绝缘层121；重新分布层122，形成在多个绝缘层121上或形成在多个绝缘层121中；以及连接过孔123，穿透绝缘层121并且将形成在不同层上的重新分布层122彼此电连接。连接结构120的层数可多于附图中所示的层数或者小于附图中所示的层数。具有这种形式的连接结构120可用作2.5D型有机中介体。
多个绝缘层121可用作连接结构120的介电层，并且绝缘层121中的每个的材料可以是诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、热固性树脂或热塑性树脂与无机填料混合的树脂(例如，诸如ABF(Ajinomoto Build-up Film)的有机绝缘材料)。在一些示例性实施例中，热固性树脂或热塑性树脂与无机填料一起浸在诸如玻璃纤维(或玻璃布或玻璃织物)的芯材料中的树脂(例如，半固化片等)也可用作绝缘层121中的每个的材料。
在一些示例性实施例中，诸如感光电介质(PID)树脂的光敏绝缘材料可用作绝缘层121中的每个的材料。由于如在本示例性实施例中多个绝缘层121可基于工艺而彼此一体化，因此绝缘层121之间的边界可以不明显。由于多个绝缘层121均包括有机材料，因此多个绝缘层121可能经受起伏问题。在本示例性实施例中使用的多个绝缘层121可使用相同的绝缘材料形成。
钝化层141的材料没有特别限制，并且可以是例如上述多个绝缘层121的绝缘材料。在一些示例性实施例中，钝化层141的材料可与多个绝缘层121的材料不同。例如，钝化层141可包括ABF，多个绝缘层121可利用PID形成。
多个重新分布层122可使连接垫111P、112P和113P重新分布，并且用于根据信号、电力等将连接垫111P、112P和113P彼此连接。重新分布层122中的每个可包括例如诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料。重新分布层122可根据相应层的设计执行各种功能。例如，重新分布层122可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。这里，信号(S)图案可包括除接地(GND)图案、电力(PWR)图案等之外的各种信号图案，诸如数据信号图案等。此外，重新分布层122可包括过孔垫、电连接金属垫等。表面处理层P可形成在重新分布层122的用作用于安装第一半导体芯片111的垫、第二半导体芯片112的垫和第三半导体芯片113的垫的图案的表面上。表面处理层P没有特别限制，只要其是现有技术中已知的即可，并且表面处理层P可通过例如电解镀金、无电镀金、有机可焊性保护剂(OSP)或无电镀锡、无电镀银、无电镀镍/置换镀金、直接浸金(DIG)镀覆、热风整平(HASL)等形成，但不限于此。
多个连接过孔123可将形成在不同层上的重新分布层122彼此电连接，从而在连接结构120中形成电路径。连接过孔123中的每个可包括例如诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料。连接过孔123可使用导电材料完全地填充，但不限于此。如上所述，多个连接过孔123可具有在不同方向上渐缩的结构，并且多个连接过孔123中的每个的截面形状可理解为图6和图8中的大体梯形形状或倒梯形形状。
第一半导体芯片111、第二半导体芯片112和第三半导体芯片113中的每个可以是按照数百至数百万或更多数量的元件集成在单个芯片中而提供的集成电路(IC)。在这种情况下，第一半导体芯片至第三半导体芯片中的每个的主体的基体材料可以是硅(Si)、锗(Ge)、砷化镓(GaAs)等。各种电路可形成在主体中的每个上。例如，连接垫111P、112P和113P中的每个可利用诸如铝(Al)等的导电材料形成。使连接垫111P、112P和113P暴露的钝化层可形成在相应的主体上，并且可以是氧化物层、氮化物层等或者氧化物层和氮化物层的双层。绝缘层等可进一步设置在所需的位置。在一些示例性实施例中，半导体封装件还可包括重新分布层(未示出)，该重新分布层(未示出)以晶圆级形成在第一半导体芯片111的有效表面、第二半导体芯片112的有效表面和第三半导体芯片113的有效表面上。此外，第一半导体芯片111、第二半导体芯片112和第三半导体芯片113可分别具有凸块111B、112B和113B，凸块111B、112B和113B分别连接到连接垫111P、112P和113P。凸块111B、112B和113B中的每个可利用金属或焊料形成。第一半导体芯片111、第二半导体芯片112和第三半导体芯片113可通过连接垫111P、112P和113P和/或凸块111B、112B和113B以及诸如焊料等的连接构件135连接到连接结构120的暴露的上部的连接重新分布层122”。如上所述，第一半导体芯片111、第二半导体芯片112和第三半导体芯片113中的每个可通过底部填充树脂170固定到连接结构120。
在一些示例性实施例中，第一半导体芯片111可以是诸如GPU的ASIC。多个第二半导体芯片112和第三半导体芯片113(举例说明了第二半导体芯片112和第三半导体芯片113中的每个的数量是两个的情况)可以是诸如HBM的存储器。也就是说，第一半导体芯片111、第二半导体芯片112和第三半导体芯片113中的每个可以是具有数十万或更多个输入/输出(I/O)端子的昂贵的芯片，但不限于此。例如，两个第二半导体芯片(HBM)112可在第一半导体芯片(诸如GPU等的ASIC)111的一侧处彼此并排设置，两个第三半导体芯片(HBM)113可在第一半导体芯片(诸如GPU等的ASIC)111的另一侧处彼此并排设置。在本示例性实施例中可使用的半导体芯片的组合不限于此，而是可包括从各种逻辑元件和各种存储器元件之中选择的至少一种，并且可适当地选择半导体芯片的数量。
凸块下金属(UBM)层145可改善电连接金属件150的连接可靠性，从而提高半导体封装件100A的可靠性。UBM层145可形成在钝化层141的开口中，并且可电连接到连接结构120的重新分布层122。UBM层145可通过任何已知的金属化方法形成。例如，UBM层145中的每个可包括诸如铜(Cu)的金属。
电连接金属件150可将半导体封装件100A物理连接或电连接到外部。例如，半导体封装件100A可通过电连接金属件150安装在BGA基板上。电连接金属件150中的每个可利用诸如低熔点金属(诸如锡(Sn)或包括锡(Sn)的合金)的导电材料形成。更详细地，电连接金属件150中每个可利用焊料等形成。电连接金属件150中的每个可以是垫、焊球、引脚等。电连接金属件150可形成为多层结构或单层结构。当电连接金属件150形成为多层结构时，电连接金属件150可包括铜(Cu)柱和焊料。当电连接金属件150形成为单层结构时，电连接金属件150可包括锡-银焊料或铜(Cu)。然而，这仅是示例，并且电连接金属件150不限于此。电连接金属件150的数量、间距、布置形式等没有特别限制，并且本领域技术人员可根据设计细节进行充分修改。例如，根据连接垫111P、112P和113P的数量，电连接金属件150可以以数千至数十万的数量设置，或者可以以数千至数十万或更多或者数千至数十万或更少的数量设置。
在下文中，将详细描述根据本示例性实施例的制造半导体封装件的方法的示例。制造图6中所示的半导体封装件100A的方法将被分成并描述为形成连接结构的工艺(图9A至图9F)和制造半导体封装件的工艺(图10A至图10C)。
图9A至图9F是用于描述制造根据本公开中的示例性实施例的半导体封装件的方法中的形成连接结构的主要工艺的截面图。
参照图9A，可准备用于形成连接结构的第一载体基板210。
第一载体基板210可包括芯层211和分别形成在芯层的背对表面上的金属层212。芯层211可利用绝缘树脂(例如，包括无机填料和/或玻璃纤维的绝缘树脂(例如，半固化片))形成，并且金属层212可以是利用铜(Cu)形成的金属层。第一载体基板210可包括形成在其一个表面上的离型层213。可对第一载体基板的这种结构和离型层的使用进行各种修改。
然后，参照图9B，可在第一载体基板210上形成绝缘层121和中间重新分布层122P。
中间重新分布层122P可设置为图案，而不包括与其一体化的连接过孔。在本工艺中，可在离型层213上形成一个绝缘层121，可在一个绝缘层121上形成不包括连接过孔的中间重新分布层122P，然后可形成另一绝缘层121以覆盖中间重新分布层122P。在本工艺中形成的中间重新分布层122P可以是多个重新分布层122中的一个，并且设置在中间重新分布层122P上方和下方的连接过孔123'可具有不同的形成方向。可通过层压绝缘膜的形式或者涂覆并硬化液相绝缘材料的形式来形成绝缘层121。
然后，参照图9C，可形成重新分布层122'和连接到中间重新分布层122P的连接过孔123'。
在本工艺中，可通过如下步骤使重新分布层122'与连接过孔123'一起形成：在绝缘层121中形成连接到中间重新分布层122P的孔，形成具有期望图案的干膜，并且使用干膜执行镀覆工艺。当绝缘层121利用PID形成时，可通过光刻工艺形成绝缘层121的孔，并且可实现精细节距的孔阵列。
然后，参照图9D，可重复执行形成绝缘层121的工艺以及形成连接过孔123'和重新分布层122'的工艺，并且可在位于连接结构的上部处的绝缘层121上形成UBM层145。
类似于参照图9C描述的工艺，可根据需要重复执行多次形成绝缘层121的工艺以及形成连接过孔123'和重新分布层122'的工艺。UBM垫142和连接到与其相邻的重新分布层122'的UBM过孔143可形成在位于连接结构的上部处的绝缘层121上和形成在位于连接结构的上部处的绝缘层121中，以形成期望的UBM层145。
可在与形成连接过孔123'和重新分布层122'的工艺的生产线相同的生产线连续地执行形成UBM层145的工艺。通过相同的镀覆工艺形成的连接过孔123'和重新分布层122'以及UBM过孔143和UBM垫142可分别形成为具有一体化结构。
此外，如上所述，UBM垫142的厚度可大于重新分布层122'的厚度。例如，UBM垫142的厚度可以是重新分布层122'的厚度的三倍或更多倍。在形成如图9C和9D中所示的一系列重新分布层122'的工艺之前将相对厚的UBM垫142引入并使其位于连接结构的下部处的情况下，随着层数增加，可能发生严重的起伏问题。然而，如图9D中所示的UBM垫142可在整个构建工艺中设置在最上方的高度上，因此可显著减少起伏问题。
然后，参照图9E，可在UBM垫142附近形成钝化层141，并且可将第二载体基板220附着到钝化层141。
在钝化层141形成为覆盖UBM垫142的情况下，可在后续工艺中应用去除(Descum)或蚀刻工艺以使UBM垫142暴露。然而，在本工艺中，钝化层141可形成为围绕UBM垫142的侧表面，同时使UBM垫142的一个表面从钝化层141暴露。在这种情况下，在后续工艺中可省略用于使UBM垫142暴露的使用等离子体等的去除工艺或蚀刻工艺，但是本工艺不限于此。类似于第一载体基板210，第二载体基板220可包括形成在结合表面上的离型层223，但是不限于此。
然后，参照图9F，可去除第一载体基板210，然后可在暴露的绝缘层121上形成另外的连接过孔123”和连接重新分布层122”。
由于在将所得结构转移到第二载体基板220之后形成连接重新分布层122”和连接过孔123”，因此连接过孔123”的形成方向可与在转移工艺之前形成的连接到重新分布层122'的连接过孔123'的形成方向相反。在本工艺中形成的连接过孔123”可具有其朝向第二载体基板220(或中间重新分布层122P)变窄的渐缩结构，而在本工艺之前形成的其他连接过孔123'可具有其朝向中间重新分布层122P变窄的渐缩结构。
在本示例性实施例中，在将所得结构转移到第二载体基板220之后，形成在绝缘层121的暴露表面上的连接重新分布层122”可以是将要连接到半导体芯片的连接垫的连接重新分布层。这里，举例说明了在转移工艺之后形成一个连接重新分布层122”的形式，但是在一些示例性实施例中，可在本工艺中形成两个或更多个重新分布层和连接过孔。
图10A至图10C示出了作为制造根据本公开中的示例性实施例的半导体封装件的方法的一部分的使用图9F中所示的连接结构制造半导体封装件的工艺。
参照图10A，可在连接结构120上安装第一半导体芯片111、第二半导体芯片112和第三半导体芯片113。
可使用诸如焊料等的连接构件135来执行本安装工艺。另外，可通过底部填充树脂170使半导体芯片111、112和113更稳定地固定。然后，可在连接结构120上形成包封半导体芯片111、112和113的包封剂160。可通过层压绝缘膜的形式或者涂覆并硬化液相绝缘材料的形式来形成包封剂160。
然后，参照图10B，可研磨包封剂160，以使第一半导体芯片111的表面、第二半导体芯片112的表面和第三半导体芯片113的表面暴露。
第一半导体芯片111的上表面、第二半导体芯片112的上表面和第三半导体芯片113的上表面可通过本研磨工艺设置在相同的高度上，并且可与包封剂的上表面基本上共面。由于半导体芯片的在研磨工艺中被部分去除的部分是无效区域，因此它们可能与功能无关，并且半导体芯片暴露在包封剂的外部，因此可改善散热效果。
然后，参照图10C，可从连接结构120去除第二载体基板220，并且可在暴露的UBM层145上形成电连接金属件150。
在去除第二载体基板220之后并且在形成电连接金属件150之前，可通过去除工艺或蚀刻工艺去除钝化层141的部分，以允许UBM垫142从钝化层的下表面突出(参见图11)。
可使用具有大面积的面板结构来执行上述一系列工艺，并且当在完成一系列工艺之后执行切割工艺时，可通过执行一次工艺来制造多个半导体封装件100A。
图11是示出根据本公开中的另一示例性实施例的半导体封装件的示意性截面图，图12是沿着图11的半导体封装件的II-II'线截取的平面图。
参照图11和图12，可理解的是，除了在转移工艺之后形成不同数量的(两个)重新分布层、另外使用另一阵列的半导体芯片和散热板以及UBM垫的侧表面的一部分被暴露之外，根据本示例性实施例的半导体封装件100B具有与图6至图8中所示的结构类似的结构。除非另有明确描述，否则根据本示例性实施例的组件可参照与用于图6至图8中所示的半导体封装件100A的相同或相似组件的描述来理解。
在根据本示例性实施例的半导体封装件100B中，本示例性实施例中使用的多个连接过孔123可关于中间重新分布层122P具有不同的形成方向。详细地，多个连接过孔123之中的与第一表面120A相邻的两个连接过孔123”可具有其朝向第二表面120B变窄的渐缩结构，而另外两个连接过孔123'和UBM过孔143可具有其朝向第一表面120A变窄的渐缩结构。在转移工艺之后形成的连接过孔123”(即，与第一表面120A相邻并且具有不同的形成方向的连接过孔123”)可按照与所有连接过孔123中的一些相对应的各种数量设计。
如图11和图12中所示，与前一示例性实施例不同，根据本示例性实施例的半导体封装件100B可包括设置在一个第一半导体芯片111的一侧处的两个第二半导体芯片112。如上所述，可在连接结构120上布置各种类型和各种数量的半导体芯片。
导热材料层191可设置在散热板195与第一半导体芯片111和第二半导体芯片112之间，并且可与第一半导体芯片111的上表面和第二半导体芯片112的上表面接触。导热材料层191可帮助从第一半导体芯片111和第二半导体芯片112产生的热顺利地散发到散热板195。导热材料层191可利用热界面材料(TIM)形成。例如，导热材料层191可利用绝缘材料形成，或者利用可包括绝缘材料的材料形成，以保持电绝缘特性。导热材料层191可包括例如环氧树脂。
散热板195可设置在导热材料层191上。散热板195可以是例如散热片、散热器、热管或液体冷却致冷板。
在本示例性实施例中，钝化层141可部分地围绕UBM垫142的侧表面，以使UBM垫142的一个表面和UBM垫142的侧表面的与UBM垫142的所述一个表面相邻的部分e暴露。如上所述，可通过去除工艺或蚀刻工艺去除钝化层141的部分，以允许UBM垫142从钝化层141的下表面突出。
如上所述，根据本公开中的示例性实施例，可在重新分布层的构建工艺中引入使用附加载体基板的转移工艺，使得可显著减少由于UBM层导致的起伏问题，并且连接过孔在最终结构中可具有不同的形成方向。此外，可通过去除起伏来满足精细电路的关键尺寸。在一些示例性实施例中，可省略用于使UBM垫暴露的附加工艺。
虽然上面已经示出和描述了示例性实施例，但是对于本领域技术人员来说将显而易见的是，在不脱离由所附权利要求限定的本发明的范围的情况下，可进行修改和变形。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
连接结构，具有彼此背对的第一表面和第二表面，并且包括多个绝缘层、分别设置在所述多个绝缘层上的多个重新分布层以及分别穿透所述多个绝缘层并且连接到所述多个重新分布层的多个连接过孔；
至少一个半导体芯片，设置在所述连接结构的所述第一表面上，并且具有电连接到所述多个重新分布层的连接垫；
包封剂，设置在所述连接结构的所述第一表面上并且包封所述至少一个半导体芯片；以及
凸块下金属层，包括设置在所述连接结构的所述第二表面上的凸块下金属垫以及将所述凸块下金属垫和所述多个重新分布层之中的与所述连接结构的所述第二表面相邻的重新分布层彼此连接的凸块下金属过孔，
其中，所述多个连接过孔之中的与所述第一表面相邻的至少一个连接过孔具有朝向所述第二表面变窄的渐缩结构，并且所述多个连接过孔中的其他连接过孔和所述凸块下金属过孔具有朝向所述第一表面变窄的渐缩结构。
2.如权利要求1所述的半导体封装件，其中，所述凸块下金属垫的厚度大于所述多个重新分布层中的每个的厚度。
3.如权利要求1所述的半导体封装件，其中，所述凸块下金属过孔的宽度大于所述多个连接过孔中的每个的宽度。
4.如权利要求1所述的半导体封装件，其中，所述凸块下金属垫具有与所述凸块下金属过孔的一体化结构。
5.如权利要求1所述的半导体封装件，所述半导体封装件还包括钝化层，所述钝化层设置在所述连接结构的所述第二表面上并且将所述凸块下金属垫的至少一部分嵌入。
6.如权利要求5所述的半导体封装件，其中，所述钝化层部分地围绕所述凸块下金属垫的侧表面，使得所述凸块下金属垫的一个表面和所述凸块下金属垫的所述侧表面的与所述一个表面相邻的部分从所述钝化层暴露。
7.如权利要求5所述的半导体封装件，其中，所述凸块下金属垫的所述一个表面和所述钝化层的下表面基本上彼此共面。
8.如权利要求5所述的半导体封装件，其中，所述钝化层包括与所述多个绝缘层中的每个的材料不同的材料。
9.如权利要求1所述的半导体封装件，其中，所述至少一个连接过孔包括两个或更多个连接过孔，所述两个或更多个连接过孔分别设置在与所述第一表面相邻的两个或更多个绝缘层中。
10.如权利要求1所述的半导体封装件，其中，所述多个重新分布层包括连接重新分布层，所述连接重新分布层设置在所述连接结构的所述第一表面上并且连接到所述至少一个半导体芯片的所述连接垫。
11.如权利要求10所述的半导体封装件，其中，所述连接重新分布层通过连接构件连接到所述至少一个半导体芯片的所述连接垫。
12.如权利要求10所述的半导体封装件，其中，所述连接重新分布层具有与所述多个连接过孔之中的同所述连接重新分布层接触的连接过孔的一体化结构。
13.如权利要求1所述的半导体封装件，其中，所述多个绝缘层中的每个包括感光电介质。
14.如权利要求1所述的半导体封装件，其中，所述至少一个半导体芯片的上表面从所述包封剂的上表面暴露，并且所述至少一个半导体芯片的所述上表面和所述包封剂的所述上表面基本上彼此共面。
15.如权利要求1所述的半导体封装件，其中，所述多个绝缘层中的每个包括有机材料。
16.如权利要求1所述的半导体封装件，其中，所述多个重新分布层中的与所述连接结构的所述第一表面相邻的所述重新分布层比其他重新分布层中的每个厚。
17.一种半导体封装件，所述半导体封装件包括：
连接结构，具有彼此背对的第一表面和第二表面，并且包括多个绝缘层、分别设置在所述多个绝缘层上的多个重新分布层以及分别穿透所述多个绝缘层并且连接到所述多个重新分布层的多个连接过孔；
至少一个半导体芯片，设置在所述连接结构的所述第一表面上，并且具有电连接到所述多个重新分布层的连接垫；
包封剂，设置在所述连接结构的所述第一表面上并且包封所述至少一个半导体芯片；
凸块下金属层，设置在所述连接结构的所述第二表面上并且电连接到所述多个重新分布层；以及
钝化层，设置在所述连接结构的所述第二表面上并且将所述凸块下金属层的至少一部分嵌入，
其中，所述多个绝缘层包括相同的绝缘材料，所述多个连接过孔之中的与所述第一表面相邻的至少一个连接过孔具有朝向所述第二表面变窄的渐缩结构，并且所述多个连接过孔中的其他连接过孔具有朝向所述第一表面变窄的渐缩结构。
18.如权利要求17所述的半导体封装件，其中，所述凸块下金属层包括：凸块下金属垫，设置在所述连接结构的所述第二表面上并且被所述钝化层至少部分地围绕；以及凸块下金属过孔，将所述凸块下金属垫和所述多个重新分布层之中的同所述连接结构的所述第二表面相邻的重新分布层彼此连接，并且
所述凸块下金属垫的厚度大于所述多个重新分布层中的每个的厚度，并且所述凸块下金属过孔具有朝向所述第一表面变窄的渐缩结构。
19.一种半导体封装件，所述半导体封装件包括：
连接结构，包括绝缘层、分别设置在所述绝缘层上的重新分布层以及分别穿透所述绝缘层并且连接到所述重新分布层的连接过孔层；以及
半导体芯片，设置在所述连接结构上并且具有电连接到所述重新分布层的连接垫，
其中，所述连接过孔层之中的第一连接过孔层和所述连接过孔层之中的第二连接过孔层在相反方向上渐缩。
20.如权利要求19所述的半导体封装件，其中，所述第一连接过孔层设置在所述半导体芯片和所述第二连接过孔层之间，并且
所述连接过孔层之中的在与所述第一连接过孔层相同的方向上渐缩的连接过孔层的数量小于所述连接过孔层之中的在与所述第二连接过孔层相同的方向上渐缩的连接过孔层的数量。
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