CN110931422B - 一种介质层的沉积方法 - Google Patents

一种介质层的沉积方法 Download PDF

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CN110931422B
CN110931422B CN201911110095.1A CN201911110095A CN110931422B CN 110931422 B CN110931422 B CN 110931422B CN 201911110095 A CN201911110095 A CN 201911110095A CN 110931422 B CN110931422 B CN 110931422B
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annealing
dielectric layer
chemical vapor
vapor deposition
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CN110931422A (zh
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王桥
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Yuteng (Tongchuan) Semiconductor Co.,Ltd.
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour

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Abstract

本发明提供了一种一种介质层的沉积方法,其包括通过可流动化学气相沉积逐层沉积并退火形成介质层,能够实现对于不同深宽比跨度的结构能够进行均匀填充,介质层不产生孔洞,并且,介质层具有较高的膜密度,能够形成具有均匀介电常数的电介质。

Description

一种介质层的沉积方法
技术领域
本发明涉及半导体制造装领域,具体涉及一种介质层的沉积方法,以及一种半导体器件的制造方法。
背景技术
现有技术中形成半导体器件的介质层是半导体器件工艺过程中重要的工艺步骤,对于半导体器件而言,介质层是器件间电隔离的重要保证,而现有技术中,形成介质层时,对于具有不同深宽比跨度的结构而言,会产生填充的不均匀,而通常采用可流动化学气相沉积的沉积方法形成介质层,然而,可流动性化学气相沉积所形成的介质膜的膜密度通常较小,介电系数通常达不到设计要求。
发明内容
基于解决上述问题,本发明提供了一种介质层的沉积方法,其特征在于,所述介质层包括氧化硅、氮氧化硅、碳氧化硅的一种或多种,所述沉积方法包括:步骤1)提供半导体衬底,所述半导体衬底为表面形成有器件的晶圆;步骤2)通过可流动化学气相沉积沉积第一层介质层,所述第一层介质层的厚度为大于或等器件高度的最大值Hmax,50nm≤Hmax≤100nm;步骤3)在Ar或He气氛下退火,所述退火为快速光热退火,退火温度为950-1000℃,退火时间为30秒~500秒;步骤4)通过可流动化学气相沉积沉积第二层介质层,所述第二层介质层的厚度为200~350nm;步骤5)在Ar或He气氛下退火,所述退火为普通退火,退火温度从室温到800℃,升温速率为50℃/小时;步骤6)通过可流动化学气相沉积沉积第三层介质层,所述第二层介质层的厚度为300~550nm;步骤7)在Ar或He气氛下退火,所述退火为普通退火,退火温度800~850℃,退火时间为1-3个小时;步骤8)进行后续工艺步骤。
本发明还提供了一种半导体器件的制造方法,包括使用本发明提出的介质层的沉积方法,用于形成半导体器件。
根据本发明的实施例,所述晶圆上的器件具有孔和槽,所述孔和槽具有不同的深宽比。
根据本发明的实施例,所述孔的深宽比为10:1~15:1,槽的深宽比为2:1~5:1。
根据本发明的实施例,所述可流动化学气相沉积沉积时的压强为10~200torr。
根据本发明的实施例,所述可流动化学气相沉积沉积氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮。
根据本发明的实施例,所述可流动化学气相沉积沉积氮氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮,含氮气体为氨气。
根据本发明的实施例,所述可流动化学气相沉积沉积碳氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮,含碳气体为甲烷。
本发明的优点如下:
(1)本申请提供的方法,能够对于不同深宽比跨度的结构能够进行均匀填充;
(2)本申请提供的方法,形成的介质层不产生孔洞;
(3)本申请提供的方法,形成的介质层具有较高的膜密度,能够形成具有均匀介电常数的电介质。
附图说明
图1为半导体衬底上形成电介质层的示意图;
图2为半导体衬底上具有不同深宽比跨度的结构经过电介质填充后结构图。
具体实施方式
第一实施例
如图1所示,半导体衬底上形成电介质层的示意图,其特征在于,所述介质层包括氧化硅、氮氧化硅、碳氧化硅的一种或多种,所述沉积方法包括:步骤1)提供半导体衬底1,所述半导体衬底为表面形成有器件的晶圆;步骤2)通过可流动化学气相沉积沉积第一层介质层2,所述第一层介质层2的厚度为大于或等器件高度的最大值Hmax,50nm≤Hmax≤100nm;步骤3)在Ar或He气氛下退火,所述退火为快速光热退火,退火温度为950-1000℃,退火时间为30秒~500秒,形成处理后的第一层介质层2’;步骤4)通过可流动化学气相沉积沉积第二层介质层3,所述第二层介质层的厚度为200~350nm;步骤5)在Ar或He气氛下退火,所述退火为普通退火,退火温度从室温到800℃,升温速率为50℃/小时,形成处理后的第二层介质层3’;步骤6)通过可流动化学气相沉积沉积第三层介质层4,所述第三层介质层的厚度为300~550nm;步骤7)在Ar或He气氛下退火,所述退火为普通退火,退火温度800~850℃,退火时间为1-3个小时,形成处理后的第三层介质层4’;步骤8)进行后续工艺步骤。
其中,所述可流动化学气相沉积沉积时的优选的沉积压强为10~200torr;所述可流动化学气相沉积沉积氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮;所述可流动化学气相沉积氮氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮,含氮气体为氨气;所述可流动化学气相沉积碳氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮,含碳气体为甲烷。
其中,所述晶圆上的器件具有孔和槽,所述孔和槽具有不同的深宽比,如图2所示,形成了高深宽比的填充结构5和低深宽比的填充结构6。其中,所述孔的深宽比为10:1~15:1,所述槽的深宽比为2:1~5:1。
第二实施例
一种半导体器件的制造方法,包括使用第一实施例的介质层的沉积方法,用于形成半导体器件。
最后应说明的是:显然,上述实施例仅仅是为清楚地说明本发明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。

Claims (7)

1.一种介质层的沉积方法,用于沉积介质层,其特征在于,所述介质层包括氧化硅、氮氧化硅、碳氧化硅的一种或多种,所述沉积方法包括:步骤1)提供半导体衬底,所述半导体衬底为表面形成有器件的晶圆;步骤2)通过可流动化学气相沉积沉积第一层介质层,所述第一层介质层的厚度大于或等于器件高度的最大值Hmax,50nm≤Hmax≤100nm;步骤3)在Ar或He气氛下退火,所述退火为快速光热退火,退火温度为950-1000℃,退火时间为30秒~500秒;步骤4)通过可流动化学气相沉积沉积第二层介质层,所述第二层介质层的厚度为200~350nm;步骤5)在Ar或He气氛下退火,所述退火为普通退火,退火温度从室温到800℃,升温速率为50℃/小时;步骤6)通过可流动化学气相沉积沉积第三层介质层,所述第三层介质层的厚度为300~550nm;步骤7)在Ar或He气氛下退火,所述退火为普通退火,退火温度800~850℃,退火时间为1-3个小时;步骤8)进行后续工艺步骤。
2.根据权利要求1介质层的沉积方法,其特征在于:所述晶圆上的器件具有孔和槽,所述孔和槽具有不同的深宽比。
3.根据权利要求1或2所述的沉积方法,其特征在于:孔的深宽比为10:1~15:1,槽的深宽比为2:1~5:1。
4.根据权利要求1或2所述的沉积方法,其特征在于:可流动化学气相沉积沉积时的压强为10~200torr。
5.根据权利要求1或2所述的沉积方法,其特征在于:可流动化学气相沉积沉积氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮。
6.根据权利要求1所述的沉积方法,其特征在于:可流动化学气相沉积沉积氮氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮,含氮气体为氨气。
7.根据权利要求1所述的沉积方法,其特征在于:可流动化学气相沉积沉积碳氧化硅时的氧化气体为臭氧、氧气、水蒸气或一氧化二氮,含碳气体为甲烷。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090043360A (ko) * 2007-10-29 2009-05-06 주식회사 티지솔라 태양전지 제조방법
CN108987248A (zh) * 2017-06-01 2018-12-11 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
CN109166787A (zh) * 2018-08-26 2019-01-08 合肥安德科铭半导体科技有限公司 一种氧化硅薄膜的可流动化学气相沉积方法
CN110391285A (zh) * 2018-04-23 2019-10-29 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090043360A (ko) * 2007-10-29 2009-05-06 주식회사 티지솔라 태양전지 제조방법
CN108987248A (zh) * 2017-06-01 2018-12-11 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
CN110391285A (zh) * 2018-04-23 2019-10-29 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109166787A (zh) * 2018-08-26 2019-01-08 合肥安德科铭半导体科技有限公司 一种氧化硅薄膜的可流动化学气相沉积方法

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