CN110892505B - 用于硅间隙填充的循环保形沉积/退火/蚀刻 - Google Patents

用于硅间隙填充的循环保形沉积/退火/蚀刻 Download PDF

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CN110892505B
CN110892505B CN201880046268.5A CN201880046268A CN110892505B CN 110892505 B CN110892505 B CN 110892505B CN 201880046268 A CN201880046268 A CN 201880046268A CN 110892505 B CN110892505 B CN 110892505B
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amorphous silicon
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程睿
杨奕
A·B·玛里克
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Applied Materials Inc
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Abstract

提供了用于无接缝和空隙的间隙填充方法，诸如用非晶硅对高纵横比的沟槽进行间隙填充。一种方法通常包括：在其上具有一个或多个特征的半导体器件上沉积非晶硅；将所述沉积的非晶硅退火以使所述一个或多个特征之间的所述沉积的非晶硅中的一个或多个接缝修复；以及蚀刻所述经退火的非晶硅以去除所述一个或多个特征之间的所述经退火的非晶硅中的一个或多个空隙。通常，将沉积、退火和蚀刻工艺重复任何合适的次数以实现非晶硅间隙填充，而在一个或多个特征之间没有任何接缝或空隙。

Description

用于硅间隙填充的循环保形沉积/退火/蚀刻
背景技术
技术领域
本公开内容的实施方式总的来说涉及半导体制造工艺，并且更具体地涉及用于用非晶硅膜对半导体器件的高纵横比沟槽进行间隙填充并且以形成无接缝或空隙的半导体器件的方法。
相关技术的描述
对于许多半导体器件制造工艺，需要填充具有大于例如10:1的高纵横比的窄沟槽。此类工艺的一个示例是浅沟槽隔离(STI)，其中膜需要具有高品质并在整个沟槽中具有非常低的泄漏。随着半导体器件结构尺寸的不断减小和纵横比的增大，后固化工艺变得越来越困难，并且导致在整个经填充的沟槽中膜具有变化的成分。
常规上，已将非晶硅(a-Si)用于半导体制造工艺中，因为a-Si通常相对于诸如氧化硅(SiO)和非晶碳(aC)等的其他膜提供良好的蚀刻选择性。然而，诸如等离子体增强化学气相沉积(PECVD)和保形沉积等的常规a-Si沉积方法不能用于对高纵横比沟槽进行间隙填充，常规a-Si沉积方法的沉积速率通常朝向沟槽顶部较高并且朝向沟槽底部较低，并且由于沉积速率不均匀，在高纵横比沟槽之间形成接缝。接缝在后固化工艺中进一步打开，并最终导致降低的产量，或者甚至半导体器件故障。接缝常规地通过热退火来修复。然而，热退火通常导致沟槽内部沉积的ids的收缩。
因此，需要用于对半导体器件的高纵横比沟槽进行间隙填充的方法，所述方法可提供无接缝和空隙的膜生长。
发明内容
提供了用于无接缝和空隙的间隙填充的方法，诸如用非晶硅对高纵横比的沟槽进行间隙填充。一种方法通常包括：在其上具有一个或多个特征的半导体器件上沉积非晶硅；将所述沉积的非晶硅退火以使所述一个或多个特征之间的所述沉积的非晶硅中的一个或多个接缝修复；以及蚀刻所述经退火的非晶硅以去除所述一个或多个特征之间的所述经退火的非晶硅中的一个或多个空隙。通常，将沉积、退火和蚀刻工艺重复任何合适的次数以实现非晶硅间隙填充，而在一个或多个特征之间没有任何接缝或空隙。
在一个实施方式中，公开了一种用于制造半导体器件的方法。所述方法包括：将基板定位在工艺腔室中，所述基板具有形成在所述基板的表面中的一个或多个特征，所述一个或多个特征中的每一个具有侧壁和底表面；在具有一个或多个特征的所述基板上沉积非晶硅膜；对所述非晶硅膜进行退火；以及蚀刻所述非晶硅膜的一部分。
在另一个实施方式中，公开了一种用于制造半导体器件的方法。所述方法包括：将基板定位在高压腔室中，所述基板具有形成在所述基板的表面中的一个或多个高纵横比沟槽，所述一个或多个高纵横比沟槽中的每一个具有侧壁和底表面；在所述一个或多个高纵横比沟槽中沉积非晶硅膜；对所述非晶硅膜进行退火以使形成在所述一个或多个高纵横比沟槽中的一个或多个接缝修复；以及蚀刻所述非晶硅膜到低于所述基板的顶表面的距离，所述距离等于所述基板的所述顶表面与所述一个或多个特征中的一个或多个空隙的最低处的底部之间的距离。
在又一实施方式中，公开了一种用于制造半导体器件的方法。所述方法包括将基板定位在第一腔室中，所述基板具有形成在所述基板的表面中的一个或多个特征，所述一个或多个特征中的每一个具有侧壁和底表面；在所述第一腔室中在具有一个或多个特征的所述基板上沉积材料；在所述第一腔室中对所述材料进行退火以使所述材料中的一个或多个接缝修复；将具有一个或多个特征的所述基板转移到第二腔室中；以及蚀刻所述经退火的材料的一部分以去除所述经退火的材料中的一个或多个空隙。
附图说明
为了能够详细地理解本公开内容的上述特征，可以参考实施方式来对以上简要概述的公开内容进行更具体的描述，所述实施方式中的一些在附图中示出。然而，应当注意，附图仅示出了示例性实施方式，并因此不应被认为是对公开内容的范围的限制，并且可允许其他等效的实施方式。
图1是概述根据本公开内容的实施方式的方法的流程图。
图2A至图2E描绘了根据本公开内容的实施方式的半导体器件的制造的阶段。
图3是根据本公开内容的实施方式的用于执行方法的设备的示意图。
为了便于理解，已经尽可能使用相同的附图标记来表示附图共有的相同元件。预期到的是，一个实施方式的元件和特征可以有益地并入其他的实施方式中，而无需进一步叙述。
具体实施方式
提供了用于无接缝和空隙的间隙填充的方法，诸如用非晶硅对高纵横比沟槽进行间隙填充。一种方法通常包括：在其上具有一个或多个特征的半导体器件上沉积非晶硅；将所述沉积的非晶硅退火以使所述一个或多个特征之间的所述沉积的非晶硅中的一个或多个接缝修复；以及蚀刻所述经退火的非晶硅以去除所述一个或多个特征之间的所述经退火的非晶硅中的一个或多个空隙。通常，将沉积、退火和蚀刻工艺重复任何合适的次数以实现非晶硅间隙填充，而在一个或多个特征之间没有任何接缝或空隙。
下面的描述将以用非晶硅对在基板上形成的高纵横比沟槽进行间隙填充作为示例。然而，本文描述的方法通常可用于用任何材料来对任何器件特征进行间隙填充或从沉积的材料去除接缝和/或空隙。通常，“特征”是指任何故意的表面不规则。特征通常具有任何合适的形状，包括但不限于过孔、沟槽、线、接触孔、通孔，或半导体、太阳能或其他电子器件中使用的其他特征定义，诸如高比率接触插塞。
在本文中用作示例的沟槽通常具有顶部和两个侧壁，并且形成在峰之间，所述峰通常具有顶部和两个侧壁。特征可具有任何合适的纵横比，所述纵横比为特征的深度与特征的宽度的比率。在一些示例中，高纵横比沟槽是具有的纵横比大于或等于约5:1、10:1、15:1、25:1、30:1、35:1或40:1的沟槽。
图1是流程图，其概述了根据本公开内容的实施方式的用非晶硅膜对器件特征进行间隙填充的方法100。图2A至图2E描绘了例如根据方法100的根据本公开内容的实施方式的半导体器件200的制造的阶段。因此，作为示例，下面根据图2A至图2E所示的用非晶硅膜对半导体器件200的高纵横比沟槽进行间隙填充的阶段来描述方法100。
方法100在操作110处通过以下步骤开始：将基板202定位到一位置或环境(诸如工艺腔室)中以供进一步处理，所述基板202具有形成在层206(诸如含硅层或含碳层)中的一个或多个特征204(示出为两个高纵横比沟槽)，如图2A所示。基板202通常是用于处理的任何合适的基板，包括但不限于硅(Si)和/或锗(Ge)基板，并且可以包括其他元素，诸如氧(O)、氮(N)和碳(C)。
如图2A所示，一个或多个特征204通常包括第一侧壁210、第二侧壁212和底部214。第一侧壁210和第二侧壁212限定一个或多个特征204的宽度(W)。一个或多个特征的高度(H)通常是从层206的顶表面208到层206的底表面216。虽然图2A示出了两个特征，但是本公开内容进一步预期到基板202可具有一个或多于一个特征204。
在操作120处，将材料218沉积在基板202的一个或多个特征204上以填充一个或多个特征204，如图2B所示。通常通过任何合适的沉积工艺来沉积材料218。合适的沉积工艺的示例包括但不限于化学气相沉积(CVD)、等离子体增强CVD(PECVD)，原子层沉积(ALD)和等离子体增强的ALD(PEALD)。在一个示例中，通过热CVD来沉积材料218。
在一个实施方式中，材料218是非晶硅膜，并且沉积材料218包括将基板202的一个或多个特征204暴露于硅前驱物。合适的硅的示例包括但不限于以下中的一种或多种：硅烷(SiH4)、乙硅烷(H6Si2)、二氯硅烷(DCS)、丙硅烷(H8Si3)和丁硅烷(Si4H10)。硅前驱物可任选地在热罐中被加热以增大蒸汽压力，然后被输送到工艺腔室以使用超高纯(UHP)氩(Ar)载气来进行沉积。通常与硅前驱物共同引入的其他合适的载气包括但不限于氦(He)和氢气(H2)。
在另一实施方式中，材料218是通过以下步骤而沉积的经掺杂的非晶硅膜：将基板202的一个或多个特征204暴露于掺杂前驱物以及硅前驱物。通过掺杂非晶硅，通常降低了用于后续处理操作(诸如蚀刻经掺杂的a-Si层)的温度。掺杂剂的示例包括但不限于硼(B)、磷(P)、镓(Ga)、锡(Tin)、砷(As)、锗(Ge)、碳(C)、氮(N)和锑(Sb)。合适的掺杂前驱物的示例包括但不限于二甲胺硼烷[NH(CH3)2BH3](DMAS)、乙硼烷(B2H6)、锗烷(GeH4)和膦(PH3)
在基板202的一个或多个特征204上沉积材料218通常发生在介于约150摄氏度(℃)与约500℃之间的温度下。可在有或没有电容耦合等离子体(CCP)或电感耦合远程等离子体(ICP)的情况下执行沉积。在沉积工艺期间，工艺腔室中的压力通常介于约100毫托(mTorr)与约350托(Torr)之间。
如上所讨论的，在材料218的沉积期间，通常在一个或多个特征204中形成一个或多个接缝220。如果保持未被处理，则一个或多个接缝220通常在半导体器件200的进一步处理期间打开，这导致有缺陷的器件性能。
在操作130处，对沉积的材料218进行退火以使一个或多个接缝220修复。在一个实施方式中，通过原位热退火工艺对材料218进行退火。退火期间的温度通常介于约400℃与约1100℃之间。所述退火工艺可以在任何适当时间量内执行，执行达例如介于约0.1秒与约5小时之间。用于退火工艺的气体环境通常包括H2、Ar、He和氮气(N2)中的一种或多种。在退火期间，工艺腔室压力通常在约100毫托与约1个大气压(atm)之间。
在另一实施方式中，一个或多个接缝220使用等离子体处理而被修复。在又一实施方式中，一个或多个接缝220用电子束处理而被修复。在进一步实施方式中，一个或多个接缝220使用使非晶硅的硅(Si)原子回流的任何合适工艺而被修复。
通常，如图2C所示，在退火过程期间在材料218中形成一个或多个空隙222(作为示例示出了三个)。例如，基板202或层206的任何表面张力通常导致在材料218中形成一个或多个空隙222。像一个或多个接缝220一样，如果一个或多个空隙222没有被部分地或完全地去除，则半导体器件200的性能通常受到负面影响。
在操作140处，蚀刻经退火的材料218的至少一部分以去除一个或多个空隙222，如图2D所示。在一个实施方式中，蚀刻经退火的材料218的一部分包括将基板202的一个或多个特征204上的材料218暴露于蚀刻剂。将材料218向下蚀刻到一个或多个特征204中低于基板202的层206的顶表面208的一定距离处，所述距离等于顶表面208与一个或多个特征204中的一个或多个空隙222的最低处的底部之间的距离。通过将材料218的一部分蚀刻至等于或低于一个或多个空隙222的最低处的底部的距离，将一个或多个空隙222在随后沉积附加材料218或另一材料之前去除。
蚀刻工艺通常是任何合适的蚀刻工艺，包括但不限于：热蚀刻、或用电容耦合等离子体(CCP)或电感耦合等离子体(ICP)进行的等离子蚀刻。合适的蚀刻剂的示例包括但不限于三氟化氮(NF3)、氯气(Cl2)、盐酸(HCl)、溴化氢(HBr)、六氟-2-丁炔(C4F6)，四氟乙烯(C2F4)、H2、Ar、He和N2中的一个或多个。
通常将操作120、操作130和操作140重复任何合适的次数，以用材料218来填充一个或多个特征204，而没有任何接缝或空隙或具有减少的接缝或空隙，如图2E所示。
图3是用于执行根据本文所述实施方式的方法的设备300的示意图。更具体地，设备300是用于根据上述方法制造半导体器件的群集工具。在设备300的中心处是转移腔室310。在转移腔室310中是基板转移机构312。基板转移机构312将基板分别从第一工艺腔室330、第二工艺腔室340或第三工艺腔室350中的一个转移至负载锁定腔室320，并且将基板分别从负载锁定腔室320转移至第一工艺腔室330、第二工艺腔室340或第三工艺腔室350中的一个。第一工艺腔室330、第二工艺腔室340和第三工艺腔室350连接到转移腔室310。负载锁定腔室320通过基板对准腔室322连接到转移腔室310。如图3所示，设备300包括三个工艺腔室。然而，设备300通常包括任何合适数量的腔室。
在一个实施方式中，第一工艺腔室330是沉积腔室，第二工艺腔室340是适用于执行退火工艺的腔室，并且第三工艺腔室350是蚀刻腔室。合适的腔室包括可从加利福尼亚州圣克拉拉市的应用材料公司(Applied Materials,inc.of Santa Clara,California)获得的腔室，诸如
Figure BDA0002362408330000051
腔室以及
Figure BDA0002362408330000052
腔室。操作120通常在第一工艺腔室330中发生。在一个实施方式中，在操作130处将基板202保留在第一工艺腔室330中进行退火工艺。在另一实施方式中，在操作130处将基板202转移到第二工艺腔室340进行退火工艺。然后，通常在操作140处将基板202转移到第三工艺腔室350以进行蚀刻工艺。
用于执行本文公开的操作的工艺腔室可从加利福尼亚州圣克拉拉市的应用材料公司获得。然而，预期的是也可以使用其他的工艺腔室，包括来自其他制造商的工艺腔室，并且可以从本公开内容的各方面受益。
本公开内容的实施方式提供了用于半导体器件特征的无接缝和空隙的间隙填充，诸如用于高纵横比沟槽的非晶硅间隙填充。由于间隙填充是无接缝和空隙的，或者包括减少的数量的接缝和空隙，所以改进了半导体器件的整体性能。
虽然前述内容是针对本公开内容的实施方式，但是可以在不脱离本公开内容的基本范围的情况下设计出本公开内容的其他和进一步的实施方式，并且本公开内容的所述范围由所附的权利要求来确定。

Claims (20)

1.一种用于制造半导体器件的方法，所述方法包括：
将基板定位在工艺腔室中，所述基板具有形成在所述基板的表面中的一个或多个特征，所述一个或多个特征中的每一个具有侧壁和底表面；
在具有一个或多个特征的所述基板上沉积非晶硅膜；
对沉积的非晶硅膜进行退火以使形成在所述一个或多个特征中的一个或多个接缝修复；以及
蚀刻经退火的非晶硅膜的一部分以去除所述一个或多个特征中的所述经退火的非晶硅膜中形成的一个或多个空隙。
2.根据权利要求1所述的方法，其中所述一个或多个特征为具有大于或等于5:1的纵横比的沟槽。
3.根据权利要求1所述的方法，其中所述沉积非晶硅膜包括：将所述基板暴露于硅前驱物。
4.根据权利要求3所述的方法，所述方法还包括：
将所述基板暴露于硼、磷、镓、锡、砷、锗、碳、氮、锑或铟前驱物。
5.根据权利要求3所述的方法，其中所述硅前驱物选自由以下项组成的群组：硅烷、乙硅烷、二氯硅烷、丙硅烷和丁硅烷。
6.根据权利要求1所述的方法，其中所述沉积非晶硅膜发生在介于150摄氏度与500摄氏度之间的温度和介于100毫托与350托之间的压力下。
7.根据权利要求1所述的方法，其中所述对所述沉积的非晶硅膜进行退火发生在介于400摄氏度与1100度之间的温度和介于100毫托与1atm之间的压力下。
8.根据权利要求1所述的方法，其中所述蚀刻所述经退火的非晶硅膜的一部分包括：使所述非晶硅膜暴露于蚀刻剂，所述蚀刻剂包括NF3、Cl2、HCl、HBr、C4F6、C2F4、H2、Ar、He和N2中的一种或多种。
9.根据权利要求1所述的方法，其中所述蚀刻所述经退火的非晶硅膜的所述一部分还包括：使所述经退火的非晶硅膜凹陷低于所述基板的顶表面的距离，所述距离等于所述基板的所述顶表面与所述一个或多个特征中的所述一个或多个空隙的最低处的底部之间的距离。
10.一种用于制造半导体器件的方法，所述方法包括：
将基板定位在工艺腔室中，所述基板具有形成在所述基板的表面中的一个或多个高纵横比沟槽，所述一个或多个高纵横比沟槽中的每一个具有侧壁和底表面；
在所述一个或多个高纵横比沟槽中沉积非晶硅膜；
对沉积的非晶硅膜进行退火以使形成在所述高纵横比沟槽中的一个或多个接缝修复；以及
将经退火的非晶硅膜蚀刻至低于所述基板的顶表面的距离，所述距离等于所述基板的所述顶表面与所述一个或多个高纵横比沟槽中的一个或多个空隙的最低处的底部之间的距离。
11.根据权利要求10所述的方法，其中所述非晶硅膜被掺杂。
12.根据权利要求11所述的方法，其中所述沉积非晶硅膜包括：
使所述基板暴露于硅前驱物；以及
使所述基板暴露于硼、磷、镓、锡、砷、锗、碳、氮、锑或铟前驱物。
13.根据权利要求12所述的方法，其中所述沉积非晶硅膜发生在介于150摄氏度与500摄氏度之间的温度和介于100毫托与350托之间的压力下。
14.根据权利要求13所述的方法，其中所述对非晶硅膜进行退火发生在介于400摄氏度与1100度之间的温度和介于100毫托与1atm之间的压力下。
15.根据权利要求14所述的方法，其中所述蚀刻所述经退火的非晶硅膜的一部分包括：使所述非晶硅膜暴露于蚀刻剂，所述蚀刻剂包括NF3、Cl2、HCl、HBr、C4F6、C2F4、H2、Ar、He和N2中的一种或多种。
16.一种用于制造半导体器件的方法，所述方法包括：
将基板定位在第一腔室中，所述基板具有形成在所述基板的表面中的一个或多个特征，所述一个或多个特征中的每一个具有侧壁和底表面；
在所述第一腔室中在具有一个或多个特征的所述基板上沉积材料；
在所述第一腔室中对所述材料进行退火以使所述材料中的一个或多个接缝修复；
将具有一个或多个特征的所述基板转移到第二腔室；以及
蚀刻所述经退火的材料的一部分以去除所述经退火的材料中的一个或多个空隙。
17.根据权利要求16所述的方法，其中所述材料是非晶硅。
18.根据权利要求16所述的方法，其中所述沉积材料发生在介于150摄氏度与500摄氏度之间的温度和介于100毫托与350托之间的压力下。
19.根据权利要求18所述的方法，其中所述对所述材料进行退火发生在介于400摄氏度与1100摄氏度之间的温度和介于100毫托与1atm之间的压力下。
20.根据权利要求19所述的方法，其中所述蚀刻所述经退火的材料的一部分包括：使所述经退火的材料凹陷低于所述基板的顶表面的距离，所述距离等于所述基板的所述顶表面与所述一个或多个特征中的一个或多个空隙的最低处的底部之间的距离。
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