CN110718593A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN110718593A
CN110718593A CN201910567643.7A CN201910567643A CN110718593A CN 110718593 A CN110718593 A CN 110718593A CN 201910567643 A CN201910567643 A CN 201910567643A CN 110718593 A CN110718593 A CN 110718593A
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integrated circuit
circuit die
semiconductor
photonic integrated
recess
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CN110718593B (zh
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余振华
夏兴国
黄松辉
黄冠育
丁国强
侯上勇
吴集锡
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了一种半导体结构，包括光子集成电路管芯、电子集成电路管芯、半导体坝和绝缘密封剂。光子集成电路管芯包括光学输入/输出部分和位于光学输入/输出部分附近的凹部，其中凹部适于横向插入至少一个光纤。电子集成电路管芯设置在光子集成电路管芯上方并且电连接至光子集成电路管芯。半导体坝设置在光子集成电路管芯上方。绝缘密封剂设置在光子集成电路管芯上方并且横向封装电子集成电路管芯和半导体坝。本发明的实施例还提供了其他的半导体结构以及形成方法。

Description

半导体结构及其形成方法
技术领域
本发明的实施例涉及半导体领域，并且更具体地，涉及半导体结构及其形成方法。
背景技术
光学收发器模块用在高速光学通信系统中，其需要高性能、紧密封装以及低能量功耗。光学传输/接收功能运用在可插拔光学收发器模块中。在达到大于100Gbps的通信速度，光学收发器模块具有多种国际标准规范。当前，紧凑型的光学收发器模块的制造工艺是非常复杂的并且需要其产率的增长。
发明内容
根据本发明的实施例，提供了一种半导体结构，包括：光子集成电路管芯，包括光学输入/输出部分和位于所述光学输入/输出部分附近的凹部；电子集成电路管芯，设置在所述光子集成电路管芯上方并且电连接至所述光子集成电路管芯；半导体坝，设置在所述光子集成电路管芯上方；以及绝缘密封剂，设置在所述光子集成电路管芯上方、横向封装所述电子集成电路管芯并且与所述半导体坝物理接触。
根据本发明的实施例，提供了一种半导体结构，包括：光子集成电路管芯，包括光学输入/输出部分和位于所述光学输入/输出部分附近的光纤凹部；电子集成电路管芯和半导体坝，以并排方式设置在所述光子集成电路管芯上方，所述电子集成电路管芯电连接至所述光子集成电路管芯；绝缘密封剂，设置在所述光子集成电路管芯上方、横向封装所述电子集成电路管芯并且与所述半导体坝的多侧物理接触，其中，所述半导体坝的侧表面由所述绝缘密封剂可接近地暴露，并且所述半导体坝将所述光纤凹部与所述绝缘密封剂隔开；以及至少一个光纤，位于所述光纤凹部中。
根据本发明的实施例，提供了一种形成半导体结构的方法，包括：提供包括至少一个光学输入/输出部分和至少一个凹部的光子集成电路管芯；将电子集成电路管芯和伪管芯接合在所述光子集成电路管芯上；以及移除所述伪管芯的一部分以形成具有凹口的半导体坝，从而使得所述至少一个凹部由所述半导体坝的凹口暴露。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1A至图1C示意性地示出了根据本发明的一些实施例的用于制造伪管芯的工艺流程。
图2示意性地示出了根据本发明的一些实施例的单个伪管芯的立体图。
图3A至图3K示意性地示出了根据本发明的一些实施例的用于制造衬底上晶圆上芯片(CoWoS)封装件的工艺流程。
图4示意性地示出了根据本发明的一些实施例的图3A中所示的中介层和图2中所示的单个伪管芯的立体图。
图5示意性地示出了根据本发明的一些实施例的图3K中所示的CoWoS封装件的俯视图。
图6示意性地示出了根据本发明的一些实施例的沿着图5中示出的线II-II’的截面图。
图7和图8示意性地示出了根据本发明的各个实施例的CoWoS封装件的截面图。
图9至图11示意性地示出了根据本发明的各个实施例的CoWoS封装件的俯视图。
具体实施方式
为了实施本发明的不同部件，以下描述提供了许多不同的实施例或实例。以下描述的元件和布置的特定实例以简化本发明。当然，这些仅是实例并不打算限定。例如，以下描述中第一部件形成在第二部件上可包括其中第一部件和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成在第一部件和第二部件之间的实施例，使得第一部件和第二部件不直接接触。另外，本发明可能在各个实施例中重复参考数字和/或字母。这种重复只是为了简明的目的且其本身并不指定各个实施例和/或所讨论的结构之间的关系。
为了便于描述，诸如“在…下面”、“在…下方”、“下”、“在…上方”、“上”等空间相对位置术语在本文中可以用于描述如附图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。应该理解，除了图中描述的方位外，这些空间相对位置术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，并因此对本文中使用的空间相对位置描述符进行同样的解释。
图1A至图1C示意性地示出了根据本发明的一些实施例的用于制造伪管芯的工艺流程。图2示意性地示出了根据本发明的一些实施例的单个伪管芯的立体图。图3A至图3K示意性地示出了根据本发明的一些实施例的用于制造CoWoS封装件的工艺流程。图4示意性地示出了根据本发明的一些实施例的图3A中所示的中介层和图2中所示的单个伪管芯的立体图。
参照图1A，提供了包括多个伪管芯100的伪半导体晶圆W1。伪半导体晶圆W1中的伪管芯100成阵列布置并且彼此物理连接。伪半导体晶圆W1可以是硅伪晶圆。在一些实施例中，伪半导体晶圆W1可以包括形成在其中的多个沟槽TR(例如，环形沟槽)，沟槽TR成阵列布置，并且每个伪管芯100可以分别包括至少一个沟槽TR。沟槽TR从伪半导体晶圆W1的顶面向下延伸至伪半导体晶圆W1的内部。在一些可选的实施例中，伪半导体晶圆W1可以包括形成在其中的多个沟槽TR(例如，环形沟槽)以及多个对准凹槽AR(例如，L形对准凹槽或者十字形对准凹槽)，其中沟槽TR成阵列布置，对准凹槽AR对应于沟槽TR布置，并且每个伪管芯100可以分别包括至少一个沟槽TR和至少一个对准凹槽AR。沟槽TR和对准凹槽AR从伪半导体晶圆W1的顶面向下延伸至伪半导体晶圆W1的内部。例如，每个对准凹槽AR分别位于一个沟槽TR的角部周围。
如图1A所示，在一些实施例中，沟槽TR的深度大于对准凹槽AR。例如，沟槽TR的深度可以在从约50微米至约600微米的范围内，其可以是伪半导体晶圆W1的厚度的约7％至约80％，并且对准凹槽AR的深度可以在从约30微米至约300微米的范围内，其可以是伪半导体晶圆W1的厚度的约4％至约40％。沟槽TR和对准凹槽AR可以通过蚀刻或其他适当的工艺形成。
参照图1B，在提供伪半导体晶圆W1之后，在伪半导体晶圆W1上执行印刷工艺以在沟槽TR中形成多个壁结构WS，在对准凹槽AR中形成多个对准标记AM并且形成多个保护涂层PC，其部分地覆盖伪半导体晶圆W1的顶面。壁结构WS和对准标记AM嵌入到伪半导体晶圆W1中，并且壁结构WS和对准标记AM未被保护涂层PC所覆盖。在一些实施例中，壁结构WS可以是环形壁结构，并且对准标记AM可以是L形对准标记或者十字形对准标记。例如，壁结构WS、对准标记AM和保护涂层PC通过三维(3D)印刷工艺形成，以使得壁结构WS、对准标记AM和保护涂层PC的厚度和体积可以不同。壁结构WS、对准标记AM和保护涂层PC的材料可以包括聚合物(例如聚酰亚胺等)。壁结构WS可以部分地填充沟槽TR，以允许至少部分地在沟槽TR中放置突起P(未在图1B中示出，但是在以下参照图3A示出和描述)，对准标记AM可以完全填充对准凹槽AR，并且保护涂层PC可以覆盖伪半导体晶圆W1的顶面的部分，该部分被环形壁结构WS围绕。由于壁结构WS部分地填充沟槽TR并且没有从伪半导体晶圆W1的顶面突出，所以壁结构WS没有与保护涂层PC直接接触。例如，壁结构WS的高度可以在从约50微米至约600微米的范围内，其为伪半导体晶圆W1的厚度的约7％至约80％。在一些实施例中，壁结构WS的顶面低于单个伪管芯100a的顶面，并且壁结构WS的表面和单个伪管芯100a的顶面之间的水平高度差在从约3微米至约50微米的范围内。
在图1C中示出的单个伪管芯100a的截面图为沿着图2中所示的截面线L-L’截取。参照图1C，伪半导体晶圆W1附接在锯切胶带T上，其由框架F承载。然后执行分离工艺(例如，晶圆锯切工艺)以分离伪半导体晶圆W1，从而获得多个单个伪管芯100a。
如图1C和图2所示，单个伪管芯100a包括沟槽TR、部分地填充在沟槽TR中的壁结构WS、对准标记AM、以及保护涂层PC。沟槽TR和壁结构WS限定单个伪管芯100a的中心区域和周边区域，其中由壁结构WS围绕的区域可以称为中心区域，并且壁结构WS外侧的区域可以称为周边区域。壁结构WS和对准标记AM嵌入到单个伪管芯100a中。壁结构WS和对准标记AM均从单个伪管芯100a的顶面向下延伸至单个伪管芯100a的内部。保护涂层PC部分地覆盖单个伪管芯100a的中心区域的顶面。壁结构WS和对准标记AM未被保护涂层PC所覆盖。保护涂层PC可以覆盖单个伪管芯100a的顶面的一部分，该部分被环形的壁结构WS围绕。由于壁结构WS部分地填充沟槽TR并且没有从单个伪管芯100a的顶面突出，所以嵌入到单个伪管芯100a中的壁结构WS没有与保护涂层PC直接接触。例如，壁结构WS的高度可以在从约50微米至约600微米的范围内，其为单个伪管芯100a的厚度的约7％至约80％。在一些可选的实施例中，单个伪管芯100a可以不包括对准标记AM。
参照图3A，提供了包括多个光子集成电路管芯200的中介层晶圆INT。中介层晶圆INT中的光子集成电路管芯200成阵列布置并且彼此物理连接。每个光子集成电路管芯200可以分别包括电接合部分200a、配置成传输和接收光学信号的至少一个光学输入/输出部分200b、以及位于至少一个光学输入/输出部分200b的附近的至少一个凹部200c。例如，如上所述的光学信号是脉冲光、光与连续波(CW)的结合等。在一些实施例中，光子集成电路管芯200的电接合部分200a可以包括结构以形成半导体通孔(TSV，以下将参照图3G描述)、半导体结构(例如，晶体管、电容器等)、布线或用于电连接的其他导体，光子集成电路管芯200的光学输入/输出部分200b可以包括半导体器件和光学器件用于处理光学信号。例如，形成在光学输入/输出部分200b中的半导体器件可以包括晶体管、电容器、光电二极管或它们的组合，形成在光学输入/输出部分200b中的光学器件可以包括边缘耦合器、调制器、波导、滤波器或它们的组合。如图3A所示，中介层晶圆INT可以包括第一有源表面AS1以及与第一有源表面AS1相对的第一后表面RS1，其中光子集成电路管芯200的电接合部分200a、光学输入/输出部分200b以及凹部200c形成在中介层晶圆INT的第一有源表面AS1上。在一些实施例中，形成在中介层晶圆INT的第一有源表面AS1上的凹部200c可以是V形凹部(如图4所示)，其通过蚀刻(例如，在晶圆INT上方堆叠介电层和钝化层、形成开口、以诸如氮化硅的电介质内衬开口、开口内衬以及在移除层之前通过内衬湿蚀刻晶圆INT)或其他合适的工艺形成。在每个光子集成电路管芯200上形成的凹部200c的数量在本发明中不作限制。
如图3A所示，中介层晶圆INT可以进一步包括多个导电凸块B1，其形成在第一有源表面AS1上。在一些实施例中，导电凸块B1可以是微凸块(例如，焊料凸块、铜凸块或其他金属凸块)，其形成在中介层晶圆INT的第一有源表面AS1上。例如，导电凸块B1的多个组可以形成在中介层晶圆INT上，并且导电凸块B1的每个组可以分别形成在一个光子集成电路管芯200上。此外，中介层晶圆INT可以进一步包括多个突起P，其形成在第一有源表面AS1上。在一些实施例中，突起P由相同材料形成并且用作导电凸块，而它们也可以是不同的。突起P可以是环形突起，其围绕凹部200c。突起P的尺寸(例如，厚度和宽度)、位置以及形状可以被设计成与图2所示的单个伪管芯100a的沟槽TR对应。例如，突起P的高度可以在从约5微米至约50微米的范围内。
参照图3B、图3C和图4，多个胶层G形成在中介层晶圆INT的第一有源表面AS1上。然后，单个伪管芯100a被拾取并放置在中介层晶圆INT的第一有源表面AS1上。单个伪管芯100a通过胶层G附接在中介层晶圆INT的第一有源表面AS1上。胶层G可以是热固化聚合物，其通过滴涂工艺等形成在中介层晶圆INT的第一有源表面AS1上。胶层G可以用作粘合剂，用于将单个伪管芯100a与中介层晶圆INT的第一有源表面AS1粘合在一起。胶层G可以与突起P保持横向距离。在一些可选的实施例中，胶层G可以与突起P粘接在一起。胶层G的厚度可以小于突起P的高度，如图3B所示。此外，胶层G的分布可以对应于单个伪管芯100a的周边区域，以使得形成在中介层晶圆INT的第一有源表面AS1上的凹部200c未被胶层G覆盖。
在将单个伪管芯100a附接在中介层晶圆INT上之后，单个伪管芯100a的周边区域通过胶层G与中介层晶圆INT粘接，并且单个伪管芯100a的中间区域覆盖凹部200c。突起P可以朝向壁结构WS延伸并且突出至单个伪管芯100a的沟槽TR中。在一些实施例中，突起P与单个伪管芯100a的壁结构WS直接接触，并且单个伪管芯100a的沟槽TR完全或部分地被突起P和壁结构WS填充。在一些可选的实施例中，突起P不与单个伪管芯100a的壁结构WS接触。突起P和沟槽TR可以有助于单个伪管芯100a与中介层晶圆INT的对准。
在将单个伪管芯100a附接在中介层晶圆INT上之后，单个伪管芯100a的保护涂层PC可以覆盖并保护中介层晶圆INT的凹部200c被破坏。如图3C所示，在一些实施例中，保护涂层PC可以与突起P保持横向距离，以帮助防止保护涂层PC干涉突起P。例如，保护涂层PC与突起P之间的横向距离可以在从约10微米至约100微米的范围内。在一些可选的实施例中，保护涂层PC可以与突起P接触。保护涂层PC的厚度可以基本上等于胶层G的厚度。例如，保护涂层PC和胶层G的厚度可以在从约100微米至约2000微米的范围内。另外，保护涂层PC可以与中介层晶圆INT的第一有源表面AS1接触，但并非与中介层晶圆INT的第一有源表面AS1永久地粘接。
参照图3C，提供包括形成在其上的导电凸块B2的多个电子集成电路管芯300并将其安装在中介层晶圆INT上。在一些实施例中，电子集成电路管芯300可以被拾取并放置在中介层晶圆INT的第一有源表面AS1上，以使得电子集成电路管芯300可以覆盖光子集成电路管芯200的电接合部分200a。每个电子集成电路管芯300可以分别包括第二有源表面AS2以及与第二有源表面AS2相对的第二后表面RS2。在将电子集成电路管芯300拾取并放置在中介层晶圆INT上之后，电子集成电路管芯300的第二有源表面AS2可以面向中介层晶圆INT并且电子集成电路管芯300可以通过导电凸块B1、导电凸块B2以及导电凸块B1和B2之间的焊料材料与中介层晶圆INT接合。例如，可以执行导电凸块B1的回流工艺，从而有助于电子集成电路管芯300和中介层晶圆INT之间的接合。在一些实施例中，电子集成电路管芯300的数量可以等于包括在中介层晶圆INT中的光子集成电路管芯200的数量。在一些可选的实施例中，电子集成电路管芯300的数量可以大于包括在中介层晶圆INT中的光子集成电路管芯200的数量。电子集成电路管芯300的数量在本发明中不构成限定。
在一些实施例中，在电子集成电路管芯300的接合之前，执行单个伪管芯100a的附接。在一些可选的实施例中，在单个伪管芯100a的附接之前，执行电子集成电路管芯300的接合。
参照图3D，在执行如上所述的导电凸块B1和B2的回流工艺之后，可以在电子集成电路管芯300和中介层晶圆INT之间形成底部填充物UF1，从而横向封装导电凸块B1和B2。底部填充物UF1不仅保护导电凸块B1和B2防止疲劳，而且还改善了电子集成电路管芯300和中介层晶圆INT之间的接合可靠性。在一些实施例中，胶层G和底部填充物UF1的材料可以是热固化聚合物，并且可以通过热固化工艺同时固化。
在一些其他的实施例中，底部填充物UF1的形成可以省略。
虽然电子集成电路管芯300和中介层晶圆INT之间的接合和电连接(如图3C所示)可以通过由底部填充物UF1封装的导电凸块B1和B2实现，但是本发明并不对电子集成电路管芯300和中介层晶圆INT之间的接合和电连接进行限制。也可以使用其他适当的芯片与晶圆接合工艺(例如，芯片与晶圆混合接合工艺)。
参照图3E和图3F，绝缘密封剂400形成在中介层晶圆INT上以封装单个伪管芯100a、电子集成电路管芯300、底部填充物UF1和胶层G。在一些实施例中，绝缘密封剂400可以通过包覆成型工艺然后第一研磨工艺形成。在包覆成型工艺期间，绝缘成型材料形成在中介层晶圆INT上以封装电子集成电路管芯300、底部填充物UF1和胶层G，从而使得电子集成电路管芯300、底部填充物UF1和胶层G未被暴露。然后，如图3F所示，绝缘成型材料被研磨或抛光直至电子集成电路管芯300的第二后表面RS2和伪管芯100a的后表面被暴露。在执行第一研磨工艺之后，横向封装伪管芯100a和电子集成电路管芯300的被抛光的绝缘密封剂400a形成在中介层晶圆INT上方。如上所述的绝缘成型材料的第一研磨工艺可以是化学机械抛光(CMP)工艺、机械研磨工艺、它们的组合或者其他合适的工艺。
参照图3G，执行减薄工艺以降低中介层晶圆INT从第一后表面RS1的厚度。在一些实施例中，研磨或抛光工艺可以在中介层晶圆INT的第一后表面RS1上执行，直至光子集成电路管芯200的电接合部分200a从中介层晶圆INT的第一后表面RS1暴露，即，完成形成TSV。如上所述的中介层晶圆INT的减薄工艺可以是化学机械抛光(CMP)工艺、机械研磨工艺、它们的组合或者其他合适的工艺。
在执行中介层晶圆INT的减薄工艺之后，再分布布线RDL和导电凸块B3可以形成在中介层晶圆INT的第一后表面RS1上。在一些实施例中，形成在中介层晶圆INT的第一后表面RS1上的导电凸块B3可以是可控塌陷芯片连接凸块(C4凸块)。例如，导电凸块B3的多个组可以形成在中介层晶圆INT的第一后表面RS1上，并且每组导电凸块B3可以分别形成在一个光子集成电路管芯200上。
在执行中介层晶圆INT的减薄工艺之后，通过第二研磨工艺对绝缘成型材料进行进一步研磨或抛光。在绝缘密封剂400a的第二研磨工艺期间，不仅绝缘成型材料被部分地移除，而且电子集成电路管芯300和单个伪管芯100a的部分也被移除。在执行第二研磨工艺之后，具有减小厚度的伪管芯100b、具有减小厚度的电子集成电路管芯300a、以及经抛光的绝缘密封剂400b形成在中介层晶圆INT上方。如图3G所示，在执行第二研磨工艺之后，壁结构WS从伪管芯100b的后表面暴露。如上所述的绝缘成型材料的第二研磨工艺可以是化学机械抛光(CMP)工艺、机械研磨工艺、它们的组合或者其他合适的工艺。
参照图3H，执行分离工艺以将图3G中所示的晶圆级结构分离成多个单个的光学收发器OTC。绝缘密封剂400b的部分、伪管芯100b的部分以及胶层G的部分可以通过分离工艺移除。如图3H所示，对准标记AM、壁结构WS的部分、伪管芯100b的中间区域的部分、以及伪管芯100b的周边区域的部分可以通过分离工艺移除。在执行分离工艺之后，凹部200c的端部从单个光学收发器OTC的侧壁可接近地暴露。
参照图3I，在执行分离工艺之后，一个单个的光学收发器OTC被拾取并放置在电路衬底SUB上。单个光学收发器OTC的导电凸块B3电连接至电路衬底SUB的布线。在一些实施例中，电路衬底SUB是印刷电路板，其包括形成在底面上的多个导电球(例如，焊料球等)。换句话说，电路衬底SUB是球珊阵列(BGA)电路衬底。
参照图3J，在将单个光学收发器OTC与电路衬底SUB接合之后，执行烧蚀工艺以移除嵌入在伪管芯100b中的壁结构WS，从而使得伪管芯100b的中间区域CR和保护涂层PC从伪管芯100b的周边区域D和光子集成电路管芯200剥离。在一些实施例中，烧蚀工艺为激光烧蚀工艺，用于部分地或完全地移除壁结构WS。在移除伪管芯100b的周边区域D和中间区域CR之间的壁结构WS之后，伪管芯100b的中间区域和保护涂层PC可以被拾取并移除，从而暴露光子集成电路管芯200上的突起P和凹部200c。周边区域D可以作为半导体坝(dam)(例如，硅坝)，用于限制绝缘密封剂400b的分布。例如，半导体坝D是电浮置的。在移除伪管芯100b的中间区域CR之后，形成了具有小形状因子的衬底上晶圆上芯片(CoWoS)封装件。在一些实施例中，具有小形状因子的CoWoS封装件的宽度或者长度可以在从约1厘米至约5厘米的范围内，而具有小形状因子的CoWoS封装件的厚度可以在从约1毫米至约3毫米的范围内。
还可以包括其他的部件和工艺。例如，可以包括测试结构以在3D封装或3D-IC器件的验证测试中进行辅助。例如，测试结构可以包括形成在允许3D封装或3D-IC的测试的再分布层中或衬底上的测试焊盘、探针和/或探针板的使用等。验证测试可以在中间结构上执行，也可以在最终结构上执行。此外，本文公开的结构和方法可以结合测试方法学使用，其结合已知良好管芯的中间验证从而增加产量并降低成本。
在一些实施例中，底部填充物UF2可以形成在单个光学收发器OTC和电路衬底SUB之间，以横向封装光子集成电路管芯200和导电凸块B3。在一些可选的实施例中，可以省略底部填充物UF2的形成。
参照图3K，在移除伪管芯100b的中间区域CR之后，提供光纤FB并将其组装至凹部200c中。在一些实施例中，提供光纤FB并将其横向插入至凹部中。光纤FB沿着凹部200c横向延伸，并且光学耦合至光子集成电路管芯200的光学输入/输出部分200b。由于组装至凹部200c的光纤FB横向延伸，因此包括光学收发器OTC和光纤FB的组件是紧凑的。
如图3K所示，周边区域D(例如，半导体坝)与电子集成电路管芯300a隔开距离D1。换句话说，距离D1表示绝缘密封剂400b的在电子集成电路管芯300a和周边区域D(例如，半导体坝)之间的部分的宽度。例如，距离D1在从约30微米至约200微米之间的范围内。
图4示意性地示出了图3A中所示的中介层和图2中所示的单个伪管芯的立体图。在实施例中，单个伪管芯100a被拾取并放置在中介层晶圆INT的第一有源表面AS1上。单个伪管芯100a通过胶层G附接在中介层晶圆INT的第一有源表面AS1上。图5示意性地示出了根据本发明的一些实施例的CoWoS封装件的俯视图。图3K示意性地示出了根据本发明的一些实施例的沿着图5中所示线I-I’的截面图。图6示意性地示出了根据本发明的一些实施例的沿着图5中所示线II-II’的截面图。
如图3K、图5和图6所示，在移除伪管芯100b的中间区域CR(如图3J所示)之后，凹口N形成在光子集成电路管芯200上方以暴露凹部200c，从而使得能够更容易地将光纤FB组装至凹部200c中。因此，可以提高光纤FB组装的产率。
图7和图8示意性地示出了根据本发明的各个实施例的CoWoS封装件的截面图。
参照图3K和图7，在图3K和图7中示出的CoWoS封装件是类似的，但是图7中示出的绝缘密封剂400b未填充在电子集成电路管芯300a和周边区域D(例如，半导体坝)之间。底部填充物UF1分配为整体填充电子集成电路管芯300a和周边区域D之间的空间，诸如通过将底部填充物UF1分配在周边区域D和电子集成电路管芯300a之间。如图7所示，周边区域D(例如，半导体坝)与电子集成电路管芯300a隔开距离D2。换句话说，距离D2表示底部填充物UF1的在电子集成电路管芯300a和周边区域D(例如，半导体坝)之间的部分的宽度。例如，距离D2在从约30微米至约200微米之间的范围内。
参照图7和图8，在图7和图8中示出的CoWoS封装件是类似的，但是图8中示出的周边区域D(例如，半导体坝)与电子集成电路管芯300a通过底部填充物UF1的部分和绝缘密封剂400b的部分隔开。例如，底部填充物UF1被分配为填充电子集成电路管芯300a和周边区域D之间的空间的部分，允许绝缘密封剂400b填充电子集成电路管芯300a和周边区域D之间的空间的剩余部分。例如，距离D2在从约30微米至约200微米之间的范围内。
图9至图11示意性地示出了根据本发明的各个实施例的CoWoS封装件的俯视图。
参照图5和图9，在图5和图9中示出的CoWoS封装件的俯视图是类似的，但是图9中示出的CoWoS封装件不包括突起P。
参照图9和图10，在图9和图10中示出的CoWoS封装件的俯视图是类似的，但是图10中示出的CoWoS封装件的半导体坝D是梳状半导体坝。如图10所示，梳状半导体坝D包括多个平行的凹口N。在一些实施例中，凹口N暴露凹部200c，并且平行的凹口N的延伸方向可以基本上平行于凹部200c。
参照图10和图11，在图10和图11中示出的CoWoS封装件的俯视图是类似的，但是图11中示出的CoWoS封装件进一步包括多个突起P，其中每个突起P分别分布为对应于半导体坝D的一个凹口N。
通过采用本文描述的实施例，光子光纤可以结合在诸如硅中介层的中介层中。此外，通过在集成芯片上系统(SOIC)中实施这些实施例，可以使得电损耗最小化，获得更高效的最终器件。
根据本发明的一些实施例，提供了光子集成电路管芯、电子集成电路管芯、半导体坝和绝缘密封剂。光子集成电路管芯包括光学输入/输出部分和位于光学输入/输出部分附近的凹部，其中凹部适于横向插入至少一个光纤。电子集成电路管芯设置在光子集成电路管芯上方并且电连接至光子集成电路管芯。半导体坝设置在光子集成电路管芯上方。绝缘密封剂设置在光子集成电路管芯上方并且横向封装电子集成电路管芯和半导体坝。
根据本发明的一些其他实施例，提供了一种结构，包括光子集成电路管芯、电子集成电路管芯、半导体坝和绝缘密封剂。光子集成电路管芯包括光学输入/输出部分和位于光学输入/输出部分附近的光纤插入凹部。电子集成电路管芯和半导体坝以并排方式设置在光子集成电路管芯上方，其中，电子集成电路管芯电连接至光子集成电路管芯。绝缘密封剂设置在光子集成电路管芯上方并且横向封装电子集成电路管芯和半导体坝，其中，半导体坝的侧表面由绝缘密封剂可接近地暴露，并且半导体坝将光纤插入凹部与绝缘密封剂隔开。
根据本发明的一些可选实施例，提供了包括以下步骤的方法。提供包括至少一个光学输入/输出部分和位于光学输入/输出部分附近的至少一个凹部的光子集成电路管芯。将电子集成电路管芯和伪管芯接合在光子集成电路管芯上。移除伪管芯的一部分以形成具有凹口的半导体坝，从而使得至少一个凹部由半导体坝的凹口暴露。
根据本发明的实施例，提供了一种半导体结构，包括：光子集成电路管芯，包括光学输入/输出部分和位于所述光学输入/输出部分附近的凹部；电子集成电路管芯，设置在所述光子集成电路管芯上方并且电连接至所述光子集成电路管芯；半导体坝，设置在所述光子集成电路管芯上方；以及绝缘密封剂，设置在所述光子集成电路管芯上方、横向封装所述电子集成电路管芯并且与所述半导体坝物理接触。
根据本发明的实施例，所述电子集成电路管芯通过多个微凸块电连接至所述光子集成电路管芯。
根据本发明的实施例，所述半导体坝包括凹口，并且所述凹部由所述半导体坝的凹口可接近地暴露。
根据本发明的实施例，还包括：设置在所述光子集成电路管芯上方的突起，其中，所述突起由所述半导体坝的凹口可接近地暴露。
根据本发明的实施例，还包括：胶层，位于所述半导体坝和所述光子集成电路管芯之间。
根据本发明的实施例，还包括位于所述凹部中的至少一个光纤。
根据本发明的实施例，还包括：电路衬底，其中，所述光子集成电路管芯设置在所述电路衬底上方并且电连接至所述电路衬底。
根据本发明的实施例，还包括：多个导电凸块；以及设置在所述电路衬底和所述光子集成电路管芯之间的底部填充物，其中，所述光子集成电路管芯通过所述导电凸块电连接至所述电路衬底，并且所述导电凸块被所述底部填充物封装。
根据本发明的实施例，提供了一种半导体结构，包括：光子集成电路管芯，包括光学输入/输出部分和位于所述光学输入/输出部分附近的光纤凹部；电子集成电路管芯和半导体坝，以并排方式设置在所述光子集成电路管芯上方，所述电子集成电路管芯电连接至所述光子集成电路管芯；绝缘密封剂，设置在所述光子集成电路管芯上方、横向封装所述电子集成电路管芯并且与所述半导体坝的多侧物理接触，其中，所述半导体坝的侧表面由所述绝缘密封剂可接近地暴露，并且所述半导体坝将所述光纤凹部与所述绝缘密封剂隔开；以及至少一个光纤，位于所述光纤凹部中。
根据本发明的实施例，所述半导体坝包括凹口，所述光纤凹部由所述半导体坝的凹口可接近地暴露，并且所述绝缘密封剂未位于所述半导体坝的凹口中。
根据本发明的实施例，还包括：设置在所述光子集成电路管芯上方的突起，其中，所述突起由所述半导体坝的凹口可接近地暴露。
根据本发明的实施例，所述电子集成电路管芯的顶面与所述半导体坝的顶面齐平。
根据本发明的实施例，还包括：电路衬底，其中，所述光子集成电路管芯设置在所述电路衬底上方并且电连接至所述电路衬底。
根据本发明的实施例，还包括：多个导电凸块；以及设置在所述电路衬底和所述光子集成电路管芯之间的底部填充物，其中，所述光子集成电路管芯通过所述导电凸块电连接至所述电路衬底，所述导电凸块被所述底部填充物封装，并且所述底部填充物的至少一部分被所述绝缘密封剂覆盖。
根据本发明的实施例，所述底部填充物完全填充所述电子集成电路管芯和所述半导体坝之间的空间。
根据本发明的实施例，所述底部填充物和所述绝缘密封剂完全填充所述电子集成电路管芯和所述半导体坝之间的空间。
根据本发明的实施例，提供了一种形成半导体结构的方法，包括：提供包括至少一个光学输入/输出部分和至少一个凹部的光子集成电路管芯；将电子集成电路管芯和伪管芯接合在所述光子集成电路管芯上；以及移除所述伪管芯的一部分以形成具有凹口的半导体坝，从而使得所述至少一个凹部由所述半导体坝的凹口暴露。
根据本发明的实施例，还包括：将至少一个光纤组装至所述至少一个凹部中。
根据本发明的实施例，还包括：在移除所述伪管芯的一部分之前，将上面接合有所述电子集成电路管芯和所述伪管芯的所述光子集成电路管芯安装在电路衬底上方。
根据本发明的实施例，还包括：在移除所述伪管芯的一部分之前，横向封装接合在所述光子集成电路管芯上的所述电子集成电路管芯和所述伪管芯。
上面论述了多个实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或修改其他用于执行与本文所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员还应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
光子集成电路管芯，包括光学输入/输出部分和位于所述光学输入/输出部分附近的凹部；
电子集成电路管芯，设置在所述光子集成电路管芯上方并且电连接至所述光子集成电路管芯；
半导体坝，设置在所述光子集成电路管芯上方；以及
绝缘密封剂，设置在所述光子集成电路管芯上方、横向封装所述电子集成电路管芯并且与所述半导体坝物理接触。
2.根据权利要求1所述的半导体结构，其中，所述电子集成电路管芯通过多个微凸块电连接至所述光子集成电路管芯。
3.根据权利要求1所述的半导体结构，其中，所述半导体坝包括凹口，并且所述凹部由所述半导体坝的凹口可接近地暴露。
4.根据权利要求3所述的半导体结构，还包括：
设置在所述光子集成电路管芯上方的突起，其中，所述突起由所述半导体坝的凹口可接近地暴露。
5.根据权利要求3所述的半导体结构，还包括：
胶层，位于所述半导体坝和所述光子集成电路管芯之间。
6.根据权利要求1所述的半导体结构，还包括位于所述凹部中的至少一个光纤。
7.根据权利要求1所述的半导体结构，还包括：
电路衬底，其中，所述光子集成电路管芯设置在所述电路衬底上方并且电连接至所述电路衬底。
8.根据权利要求7所述的半导体结构，还包括：
多个导电凸块；以及
设置在所述电路衬底和所述光子集成电路管芯之间的底部填充物，其中，所述光子集成电路管芯通过所述导电凸块电连接至所述电路衬底，并且所述导电凸块被所述底部填充物封装。
9.一种半导体结构，包括：
光子集成电路管芯，包括光学输入/输出部分和位于所述光学输入/输出部分附近的光纤凹部；
电子集成电路管芯和半导体坝，以并排方式设置在所述光子集成电路管芯上方，所述电子集成电路管芯电连接至所述光子集成电路管芯；
绝缘密封剂，设置在所述光子集成电路管芯上方、横向封装所述电子集成电路管芯并且与所述半导体坝的多侧物理接触，其中，所述半导体坝的侧表面由所述绝缘密封剂可接近地暴露，并且所述半导体坝将所述光纤凹部与所述绝缘密封剂隔开；以及
至少一个光纤，位于所述光纤凹部中。
10.一种形成半导体结构的方法，包括：
提供包括至少一个光学输入/输出部分和至少一个凹部的光子集成电路管芯；
将电子集成电路管芯和伪管芯接合在所述光子集成电路管芯上；以及
移除所述伪管芯的一部分以形成具有凹口的半导体坝，从而使得所述至少一个凹部由所述半导体坝的凹口暴露。
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