TW202018896A - 光收發器及其製造方法 - Google Patents

光收發器及其製造方法 Download PDF

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TW202018896A
TW202018896A TW108122325A TW108122325A TW202018896A TW 202018896 A TW202018896 A TW 202018896A TW 108122325 A TW108122325 A TW 108122325A TW 108122325 A TW108122325 A TW 108122325A TW 202018896 A TW202018896 A TW 202018896A
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Taiwan
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integrated circuit
die
circuit die
photonic integrated
item
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TW108122325A
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TWI719514B (zh
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余振華
吳集錫
丁國強
黃松輝
侯上勇
夏興國
黃冠育
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台灣積體電路製造股份有限公司
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    • G—PHYSICS
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    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
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Abstract

一種結構，包含光子積體電路晶粒、電積體電路晶粒、半導體障壁以及絕緣包封體。光子積體電路晶粒包含光輸入/輸出部分及鄰近於光輸入/輸出部分定位的凹槽，其中凹槽適用於側向插入至少一個光纖。電積體電路晶粒安置於光子積體電路晶粒上方且電性連接至光子積體電路晶粒。半導體障壁安置於光子積體電路晶粒上方。絕緣包封體安置於光子積體電路晶粒上方且側向地包封電積體電路晶粒及半導體障壁。

Description

光收發器及其製造方法
光收發器模組用於需要高效能、緊湊封裝以及低功耗的高速光通信系統。光傳輸/接收功能在可插拔光收發器模組中實施。光收發器模組在高達100 Gbps以上的範圍的通信速度下遵守各種國際標準規格。當前，緊湊光收發器模組的製造製程非常複雜，且需要其良品率增加。
以下揭露內容提供用於實施所提供的標的的不同特徵的許多不同實施例或實例。以下描述組件及配置的特定實例以簡化本揭露內容。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單性及清晰的目的，且本身不指示所論述的各種實施例及/或配置之間的關係。
另外，為易於描述，可在本文中使用諸如「在...之下（beneath）」、「在...下方（below）」、「下部（lower）」、「在..上方（above）」、「上部（upper）」以及類似者的空間相對術語來描述如在圖式中所示出的一個元件或特徵與另一元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
圖1A至圖1C示意性地示出根據本揭露的一些實施例用於製造虛擬晶粒的製程流程。圖2示意性地示出根據本揭露的一些實施例的單體化虛擬晶粒的透視圖。圖3A至圖3K示意性地示出根據本揭露的一些實施例用於製造CoWoS封裝的製程流程。圖4示意性地示出根據本揭露的一些實施例的圖3A中所示出的插入件及圖2中所示出的單體化虛擬晶粒的透視圖。
參看圖1A，提供包含多個虛擬晶粒100的虛擬半導體晶圓W1。虛擬半導體晶圓W1中的虛擬晶粒100排成陣列且彼此物理接觸。虛擬半導體晶圓W1可為矽虛擬晶圓。在一些實施例中，虛擬半導體晶圓W1可包含形成於其中的多個溝槽TR（例如環形溝槽），溝槽TR排成陣列，且虛擬晶粒100中的每一者可分別包含至少一個溝槽TR。溝槽TR自虛擬半導體晶圓W1的頂部表面朝下延伸至虛擬半導體晶圓W1的內部中。在一些替代實施例中，虛擬半導體晶圓W1可包含形成於其中的多個溝槽TR（例如環形溝槽）及多個對準凹部AR（例如L形對準凹部或十字形對準凹部），其中溝槽TR排成陣列，對準凹部AR對應於溝槽TR配置，且虛擬晶粒100中的每一者可分別包含至少一個溝槽TR及至少一個對準凹部AR。溝槽TR及對準凹部AR自虛擬半導體晶圓W1的頂部表面朝下延伸至虛擬半導體晶圓W1的內部中。舉例而言，每個對準凹部AR分別定位於一個溝槽TR的拐角周圍。
如圖1A中所繪示，在一些實施例中，溝槽TR具有比對準凹部AR更大的深度。舉例而言，溝槽TR的深度可介於約50微米至約600微米範圍內，所述深度為虛擬半導體晶圓W1的厚度的約7%至約80%，且對準凹部AR的深度可介於約30微米至約300微米範圍內，所述深度為虛擬半導體晶圓W1的厚度的約4%至約40%。溝槽TR及對準凹部AR可藉由蝕刻或其他適合的製程形成。
參看圖1B，在提供虛擬半導體晶圓W1之後，對虛擬半導體晶圓W1執行印刷製程以形成溝槽TR中的多個壁結構WS、對準凹部AR中的多個對準標記AM以及部分覆蓋虛擬半導體晶圓W1的頂部表面的多個保護塗層PC。壁結構WS及對準標記AM嵌入於虛擬半導體晶圓W1中，同時壁結構WS及對準標記AM未經保護塗層PC覆蓋。在一些實施例中，壁結構WS可為環形壁結構，且對準標記AM可為L形對準標記或十字形對準標記。舉例而言，壁結構WS、對準標記AM以及保護塗層PC由三維（three-dimensional；3D）印刷製程形成，以使得壁結構WS、對準標記AM以及保護塗層PC的厚度及體積可不同。壁結構WS、對準標記AM以及保護塗層PC的材料可包含聚合物（例如聚醯亞胺或其類似者）。壁結構WS可部分填充溝槽TR以允許突部P（圖1B中未示出但下文關於圖3A示出且描述）至少部分地置放至溝槽TR中，對準標記AM可完全填充對準凹部AR，且保護塗層PC可覆蓋虛擬半導體晶圓W1的頂部表面的部分，所述部分被環形壁結構WS圍封。因為壁結構WS部分填充溝槽TR且不自虛擬半導體晶圓W1的頂部表面突出，所以壁結構WS不直接地與保護塗層PC接觸。舉例而言，壁結構WS的高度可介於約50微米至約600微米範圍內，所述高度為虛擬半導體晶圓W1的厚度的約7%至約80%。在一些實施例中，壁結構WS的頂部表面低於單體化虛擬晶粒100a的頂部表面，且壁結構WS的表面之間的水平高度差介於約3微米至約50微米範圍內，所述表面低於單體化虛擬晶粒100a的頂部表面。
圖1C中所示出的單體化虛擬晶粒100a的截面視圖沿圖2中所繪示的橫截面線L-L'切割。參看圖1C，虛擬半導體晶圓W1附接至由框架F承載的鋸帶T上。隨後執行單體化製程（例如晶圓鋸割製程）以使虛擬半導體晶圓W1單體化以獲得多個單體化虛擬晶粒100a。
如圖1C及圖2中所繪示，單體化虛擬晶粒100a包含溝槽TR、部分填充於溝槽TR中的壁結構WS、對準標記AM以及保護塗層PC。溝槽TR及壁結構WS定義單體化虛擬晶粒100a的中心區域及周邊區域，其中由壁結構WS包圍的區域可稱作中心區域，且壁結構WS外部的區域可稱作周邊區域。壁結構WS及對準標記AM嵌入於單體化虛擬晶粒100a中。壁結構WS及對準標記AM皆自單體化虛擬晶粒100a的頂部表面朝下延伸至單體化虛擬晶粒100a的內部中。保護塗層PC部分覆蓋單體化虛擬晶粒100a的中心區域的頂部表面。壁結構WS及對準標記AM未被保護塗層PC覆蓋。保護塗層PC可覆蓋單體化虛擬晶粒100a的頂部表面的一部分，所述部分藉由環形壁結構WS圍封。因為壁結構WS部分填充溝槽TR且不自單體化虛擬晶粒100a的頂部表面突出，所以嵌入於單體化虛擬晶粒100a中的壁結構WS不直接地與保護塗層PC接觸。舉例而言，壁結構WS的高度可介於約50微米至約600微米範圍內，所述高度為單體化虛擬晶粒100a的厚度的約7%至約80%。在一些替代實施例中，單體化虛擬晶粒100a可不包含對準標記AM。
參看圖3A，提供包含多個光子積體電路晶粒200的插入件晶圓INT。插入件晶圓INT中的光子積體電路晶粒200排成陣列且彼此物理連接。光子積體電路晶粒200中的每一者可分別包含電接合部分200a、經配置以傳輸及接受光信號的至少一個光輸入/輸出部分200b以及位置鄰近至少一個光輸入/輸出部分200b的至少一個凹槽200c。上文所提及的光信號為例如脈衝光、具有連續波（continuous wave；CW）的光、前述光的組合或其類似者。在一些實施例中，光子積體電路晶粒200的電接合部分200a可包含用以形成半導體穿通孔（through semiconductor via；TSV－下文關於圖3G進一步描述）的結構、半導體裝置（例如電晶體、電容器等）、配線或用於電連接的其他導體，而光子積體電路晶粒200的光輸入/輸出部分200b可包含用於處理光信號的半導體裝置及光裝置。舉例而言，形成於光輸入/輸出部分200b中的半導體裝置可包含電晶體、電容器、光電二極體或其組合，且形成於光輸入/輸出部分200b中的光裝置可包含邊緣耦合器、調變器、波導管、濾光器或其組合。如圖3A中所繪示，插入件晶圓INT可包含第一主動表面AS1及與第一主動表面AS1相對的第一背面RS1，其中光子積體電路晶粒200的電接合部分200a、光輸入/輸出部分200b以及凹槽200c形成於插入件晶圓INT的第一主動表面AS1處。在一些實施例中，形成於插入件晶圓INT的第一主動表面AS1上的凹槽200c可為藉由蝕刻（例如將介電層及鈍化層堆疊在晶圓INT上方，形成開口，用諸如氮化矽的介電質給開口加襯套，使襯套開口，以及在移除所述層之前經由襯套對晶圓INT進行濕式蝕刻）或其他適合的製程形成的V形凹槽（圖4中所繪示）。形成於每一光子積體電路晶粒200上的凹槽200c的數目在本揭露中不受限制。
如圖3A中所繪示，插入件晶圓INT可更包含形成於其第一主動表面AS1上的多個導電凸塊B1。在一些實施例中，導電凸塊B1可為形成於插入件晶圓INT的第一主動表面AS1上的微型凸塊（例如焊料凸塊、銅凸塊或其他金屬凸塊）。舉例而言，多個導電凸塊B1組可形成於插入件晶圓INT上，且每一導電凸塊B1組可分別形成於一個光子積體電路晶粒200上。此外，插入件晶圓INT可更包含形成於其第一主動表面AS1上的多個突部P。在一些實施例中，突部P由與導電凸塊相同的材料及製程形成，但所述材料及製程亦可不同。突部P可為包圍凹槽200c的環形突部。突部P的尺寸（亦即，厚度及寬度）、位置以及形狀可經設計以對應於如圖2中所示出的單體化虛擬晶粒100a的溝槽TR。舉例而言，突部P的高度介於約5微米至約50微米範圍內。
參看圖3B、圖3C以及圖4，多個膠層G形成於插入件晶圓INT的第一主動表面AS1上。隨後，單體化虛擬晶粒100a經拾取並置放於插入件晶圓INT的第一主動表面AS1上。單體化虛擬晶粒100a經由膠層G附接至插入件晶圓INT的第一主動表面AS1上。膠層G可為經由點膠製程或其類似者形成於插入件晶圓INT的第一主動表面AS1上的可熱固化的聚合物。膠層G可充當使單體化虛擬晶粒100a與插入件晶圓INT的第一主動表面AS1黏著的黏著劑。膠層G可與突部P保持一側向距離。在一些替代實施例中，膠層G可黏著於突部P。膠層G的厚度可小於突部P的高度，如圖3B中所示出。此外，膠層G的分佈可對應於單體化虛擬晶粒100a的周邊區域，以使得形成於插入件晶圓INT的第一主動表面AS1上的凹槽200c未被膠層G覆蓋。
在將單體化虛擬晶粒100a附接至插入件晶圓INT上之後，單體化虛擬晶粒100a的周邊區域與插入件晶圓INT經由膠層G黏著，且單體化虛擬晶粒100a的中心區域覆蓋凹槽200c。突部P可朝向壁結構WS延伸且可突出至單體化虛擬晶粒100a的溝槽TR中。在一些實施例中，突部P與單體化虛擬晶粒100a的壁結構WS直接接觸，且單體化虛擬晶粒100a的溝槽TR由突部P及壁結構WS完全或部分填充。在一些替代實施例中，突部P不與單體化虛擬晶粒100a的壁結構WS接觸。突部P及溝槽TR可促進單體化虛擬晶粒100a及插入件晶圓INT的對準。
在將單體化虛擬晶粒100a附接至插入件晶圓INT上之後，單體化虛擬晶粒100a的保護塗層PC可覆蓋插入件晶圓INT的凹槽200c並保護其不受損壞。如圖3C中所示出，在一些實施例中，保護塗層PC可與突部P保持一側向距離，以幫助使保護塗層PC免於干擾突部P。舉例而言，保護塗層PC與突部P的側向距離介於約10微米至約100微米範圍內。在一些替代實施例中，保護塗層PC可與突部P接觸。保護塗層PC的厚度可與膠層G的厚度實質上一致。舉例而言，保護塗層PC及膠層G的厚度介於約100微米至約2000微米範圍內。此外，保護塗層PC可與插入件晶圓INT的第一主動表面AS1接觸且可不與插入件晶圓INT的第一主動表面AS1永久地黏著。
參看圖3C，包含形成於其上的導電凸塊B2的多個電積體電路晶粒300經提供且安裝至插入件晶圓INT上。在一些實施例中，電積體電路晶粒300可經拾取並置放於插入件晶圓INT的第一主動表面AS1上，以使得電積體電路晶粒300可覆蓋光子積體電路晶粒200的電接合部分200a。電積體電路晶粒300中的每一者可分別包含第二主動表面AS2及與第二主動表面AS2相對的第二背面RS2。在電積體電路晶粒300經拾取並置放於插入件晶圓INT上之後，電積體電路晶粒300的第二主動表面AS2可面向插入件晶圓INT，且電積體電路晶粒300可與插入件晶圓INT經由導電凸塊B1、導電凸塊B2以及導電凸塊B1與導電凸塊B2之間的焊料材料接合。舉例而言，可執行導電凸塊B1的回焊製程以促進電積體電路晶粒300與插入件晶圓INT之間的接合。在一些實施例中，電積體電路晶粒300的數目可等於包含於插入件晶圓INT中的光子積體電路晶粒200的數目。在一些替代實施例中，電積體電路晶粒300的數目可大於包含於插入件晶圓INT中的光子積體電路晶粒200的數目。電積體電路晶粒300的數目在本揭露中不受限制。
在一些實施例中，在電積體電路晶粒300的接合之前執行單體化虛擬晶粒100a的附接。在一些替代實施例中，在單體化虛擬晶粒100a的附接之前執行電積體電路晶粒300的接合。
參看圖3D，在執行導電凸塊B1及導電凸塊B2的上文所提及的回焊製程之後，底膠（underfill）UF1可形成於電積體電路晶粒300與插入件晶圓INT之間以便側向地包封導電凸塊B1及導電凸塊B2。底膠UF1不僅保護導電凸塊B1及導電凸塊B2免於疲勞且亦增強電積體電路晶粒300與插入件晶圓INT之間的接合可靠性。在一些實施例中，膠層G及底膠UF1的材料可為可熱固化的聚合物且可藉由熱固化製程同時固化。
在一些其他實施例中，可省略底膠UF1的形成。
儘管電積體電路晶粒300與插入件晶圓INT之間的接合及電連接（圖3C中所繪示）藉由被底膠UF1包封的導電凸塊B1及導電凸塊B2來達成，但本揭露的電積體電路晶粒300與插入件晶圓INT之間的接合及電連接不限於此。可利用其他適合的晶片與晶圓接合製程（例如晶片與晶圓混合接合製程）。
參看圖3E及圖3F，絕緣包封體400形成於插入件晶圓INT上以包封單體化虛擬晶粒100a、電積體電路晶粒300、底膠UF1以及膠層G。在一些實施例中，絕緣包封體400可藉由包覆模製製程形成，隨後為第一研磨製程。在包覆模製製程期間，絕緣模製材料形成於插入件晶圓INT上以包封電積體電路晶粒300、底膠UF1以及膠層G，以使得未顯露電積體電路晶粒300、底膠UF1以及膠層G。隨後，如圖3F中所示出，絕緣模製材料經研磨或拋光直至電積體電路晶粒300的第二背面RS2及虛擬晶粒100a的背面暴露為止。在執行第一研磨製程之後，經拋光的絕緣包封體400a側向地包封虛擬晶粒100a，且電積體電路晶粒300形成於插入件晶圓INT上方。上文所提及的絕緣模製材料的第一研磨製程可為化學機械研磨（chemical mechanical polishing；CMP）製程、機械研磨製程、其組合或其他適合的製程。
參看圖3G，執行薄化製程以自第一背面RS1減小插入件晶圓INT的厚度。在一些實施例中，可對插入件晶圓INT的第一背面RS1執行研磨或拋光製程，直至光子積體電路晶粒200的電接合部分200a自插入件晶圓INT的第一背面RS1顯露為止，亦即完全形成TSV。插入件晶圓INT的上文所提及的薄化製程可為化學機械研磨（CMP）製程、機械研磨製程、其組合或其他適合的製程。
在執行插入件晶圓INT的薄化製程之後，重佈線RDL及導電凸塊B3可形成於插入件晶圓INT的第一背面RS1上。在一些實施例中，形成於插入件晶圓INT的第一背面RS1上的導電凸塊B3可為可控塌陷晶片連接凸塊（controlled collapse chip connection bump；C4凸塊）。舉例而言，多個導電凸塊B3組可形成於插入件晶圓INT的第一背面RS1上，且每一導電凸塊B3組可分別形成於光子積體電路晶粒200中的一者上。
在執行插入件晶圓INT的薄化製程之後，絕緣模製材料藉由第二研磨製程進一步研磨或拋光。在絕緣包封體400a的第二研磨製程期間，不僅部分移除絕緣模製材料且亦移除電積體電路晶粒300及單體化虛擬晶粒100a的部分。在執行第二研磨製程之後，具有減小厚度的虛擬晶粒100b、具有減小厚度的電積體電路晶粒300a以及經研磨的絕緣包封體400b形成於插入件晶圓INT上方。如圖3G中所繪示，在執行第二研磨製程之後，壁結構WS自虛擬晶粒100b的背面顯露。絕緣模製材料的上文所提及的第二研磨製程可為化學機械研磨（CMP）製程、機械研磨製程、其組合或其他適合的製程。
參看圖3H，執行單體化製程以使圖3G中所示出的晶圓級結構單體化成多個單體化光收發器OTC。絕緣包封體400b的部分、虛擬晶粒100b的部分以及膠層G的部分可藉由單體化製程移除。如圖3H中所示出，對準標記AM、壁結構WS的部分、虛擬晶粒100b的中心區域的部分以及虛擬晶粒100b的周邊區域的部分可藉由單體化製程移除。在執行單體化製程之後，凹槽200c的一端自單體化光收發器OTC的側壁暴露。
參看圖3I，在執行單體化製程之後，單體化光收發器OTC中的一者經拾取並置放於電路基底SUB上。單體化光收發器OTC的導電凸塊B3電性連接至電路基底SUB的配線。在一些實施例中，電路基底SUB為印刷電路板，所述印刷電路板包含形成於其底部表面上的多個導電球（例如焊料球或其類似者）。換言之，電路基底SUB為球柵陣列（ball grid array；BGA）電路基底。
參看圖3J，在將單體化光收發器OTC與電路基底SUB接合之後，執行剝離製程以移除嵌入於虛擬晶粒100b中的壁結構WS，以使得虛擬晶粒100b的中心區域CR及保護塗層PC自虛擬晶粒100b的周邊區域D及光子積體電路晶粒200剝離。在一些實施例中，剝離製程為用於部分或完全移除壁結構WS的雷射剝離製程。在移除虛擬晶粒100b的周邊區域D與中心區域CR之間的壁結構WS之後，可拾取並移除虛擬晶粒100b的中心區域及保護塗層PC，以使得突部P及光子積體電路晶粒200上的凹槽200c顯露。周邊區域D可充當用於限制絕緣包封體400b的分佈的半導體障壁（例如矽障壁）。半導體障壁D例如電性浮置。在移除虛擬晶粒100b的中心區域CR之後，完成具有較小形狀因素的基底上晶圓上晶片（CoWoS）封裝。在一些實施例中，具有較小形狀因素的CoWoS封裝的寬度或長度可介於約1公分至約5公分範圍內，而具有較小外觀尺寸的CoWoS封裝的厚度可介於約1毫米至約3毫米範圍內。
亦可包含其他特徵及製程。舉例而言，可包含測試結構以幫助對3D封裝或3D-IC裝置的驗證測試。測試結構可包含例如形成於重佈層中或基底上的測試墊，從而允許測試3D封裝或3D-IC、使用探針及/或探針卡以及其類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併有對良好晶粒的中間驗證的測試方法使用，以提高良率且降低成本。
在一些實施例中，底膠UF2可形成於單體化光收發器OTC與電路基底SUB之間以側向地包封光子積體電路晶粒200及導電凸塊B3。在一些替代實施例中，可省略底膠UF2的形成。
參看圖3K，在移除虛擬晶粒100b的中心區域CR之後，光纖FB經提供並組裝於凹槽200c中。在一些實施例中，光纖FB經提供且側向地插入凹槽中。光纖FB沿凹槽200c側向地延伸且光學耦接至光子積體電路晶粒200的光輸入/輸出部分200b。因為組裝於凹槽200c中的光纖FB側向地延伸，所以包含光收發器OTC及光纖FB的組件為緊湊的。
如圖3K中所繪示，周邊區域D（例如半導體障壁）與電積體電路晶粒300a藉由距離D1間隔開。換言之，距離D1表示電積體電路晶粒300a與周邊區域D（例如半導體障壁）之間的絕緣包封體400b的一部分的寬度。舉例而言，距離D1介於約30微米至約200微米範圍內。
圖4示出示意性地示出圖3A中所示出的插入件及圖2中所示出的單體化虛擬晶粒的透視圖。在實施例中，單體化虛擬晶粒100a經拾取並置放於插入件晶圓INT的第一主動表面AS1上。單體化虛擬晶粒100a經由膠層G附接至插入件晶圓INT的第一主動表面AS1上。圖5示意性地示出根據本揭露的一些實施例的CoWoS封裝的俯視圖。圖3K示意性地示出根據本揭露的一些實施例的沿圖5中所繪示的線I-I'的截面視圖。圖6示意性地示出根據本揭露的一些實施例的沿圖5中所繪示的線II-II'的截面視圖。
如圖3K、圖5以及圖6中所繪示，在移除虛擬晶粒100b的中心區域CR（圖3J中所繪示）之後，凹口N形成於光子積體電路晶粒200上方以暴露凹槽200c，以使得更易於將光纖FB組裝至凹槽200c中。因此，可增加光纖FB的組裝的良品率。
圖7及圖8示意性地示出根據本揭露的各種實施例的CoWoS封裝的截面視圖。
參看圖3K及圖7，除了圖7中所示出的絕緣包封體400b未填充於電積體電路晶粒300a與周邊區域D（例如半導體障壁）之間外，圖3K及圖7中所示出的CoWoS封裝類似。相反，諸如藉由將底膠UF1分配於周邊區域D與電積體電路晶粒300a之間，分配底膠UF1以完全填充電積體電路晶粒300a與周邊區域D之間的空間。如圖7中所繪示，周邊區域D（例如半導體障壁）與電積體電路晶粒300a藉由距離D2間隔開。換言之，距離D2表示電積體電路晶粒300a與周邊區域D（例如半導體障壁）之間的部分底膠UF1的寬度。舉例而言，距離D2介於約30微米至約200微米範圍內。
參看圖7及圖8，除了圖8中所示出的周邊區域D（亦即，半導體障壁）與電積體電路晶粒300a藉由底膠UF1的一部分及絕緣包封體400b的一部分間隔開外，圖7及圖8中所示出的CoWoS封裝類似。舉例而言，分配底膠UF1以填充電積體電路晶粒300a與周邊區域D之間的空間的一部分，從而允許絕緣包封體400b填充電積體電路晶粒300a與周邊區域D之間的空間的剩餘部分。舉例而言，距離D2介於約30微米至約200微米範圍內。
圖9至圖11示意性地示出根據本揭露的各種實施例的CoWoS封裝的俯視圖。
參看圖5及圖9，除了圖9中所示出的CoWoS封裝不包含突部P外，圖5及圖9中所示出的CoWoS封裝的俯視圖類似。
參看圖9及圖10，除了圖10中所示出的CoWoS封裝的半導體障壁D為梳形半導體障壁外，圖9及圖10中所示出的CoWoS封裝的俯視圖類似。如圖10中所繪示，梳形半導體障壁D包含多個平行的凹口N。在一些實施例中，凹口N暴露凹槽200c，且平行的凹口N的延伸方向可與凹槽200c的延伸方向實質上平行。
參看圖10及圖11，除了圖11中所示出的CoWoS封裝更包含多個突部P外，圖10及圖11中所示出的CoWoS封裝的俯視圖類似，其中每一突部P分別對應於半導體障壁D的凹口N中的一者分佈。
藉由利用本文中所描述的實施例，光子纖維可整合於諸如矽插入件的插入件內。另外，藉由將實施例實施於系統整合晶片（system on integrated chip；SOIC），可使電損失最小化，從而產生更高效的最終裝置。
根據本發明的一些實施例，提供光子積體電路晶粒、電積體電路晶粒、半導體障壁以及絕緣包封體。光子積體電路晶粒包含光輸入/輸出部分及位置鄰近於光輸入/輸出部分的凹槽，其中凹槽適用於側向插入至少一個光纖。電積體電路晶粒安置於光子積體電路晶粒上方且電性連接至所述光子積體電路晶粒。半導體障壁安置於光子積體電路晶粒上方。絕緣包封體安置於光子積體電路晶粒上方且側向地包封電積體電路晶粒及半導體障壁。
根據本發明的一些其他實施例，提供一種包含光子積體電路晶粒、電積體電路晶粒、半導體障壁以及絕緣包封體的結構。光子積體電路晶粒包含光輸入/輸出部分及位置鄰近光輸入/輸出部分的光纖插入凹槽。電積體電路晶粒及半導體障壁以並列方式安置於光子積體電路晶粒上方，其中電積體電路晶粒電性連接至光子積體電路晶粒。絕緣包封體安置於光子積體電路晶粒上方且側向地包封電積體電路晶粒及半導體障壁，其中半導體障壁的側表面自絕緣包封體暴露，且半導體障壁使光纖插入凹槽與絕緣包封體分離。
根據本發明的一些替代實施例，提供一種包含以下步驟的方法。提供光子積體電路晶粒，所述光子積體電路晶粒包含至少一個光輸入/輸出部分及位置鄰近光輸入/輸出部分的至少一個凹槽。將電積體電路晶粒及虛擬晶粒接合於光子積體電路晶粒上。移除虛擬晶粒的一部分以形成具有凹口的半導體障壁，以使得至少一個凹槽藉由半導體障壁的凹口暴露。
前文概述若干實施例的特徵，以使得所屬領域中具通常知識者可較好地理解本揭露的態樣。所屬領域中具通常知識者應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的且/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出改變、替代以及更改。
100、100b:虛擬晶粒 100a:單體化虛擬晶粒 200:光子積體電路晶粒 200a:電氣接合部分 200b:光輸入/輸出部分 200c:凹槽 300、300a:電積體電路晶粒 400:絕緣包封體 400a、400b:經研磨絕緣包封體 AM:對準標記 AR:對準凹部 AS1:第一主動表面 AS2:第二主動表面 B1、B2、B3:導電凸塊 CR:中心區域 D:周邊區域/半導體障壁 D1、D2:距離 F:框架 FB:光纖 G:膠層 INT:插入件晶圓 L-L':橫截面線 N:凹口 OTC:單體化光收發器 P:突部 PC:保護塗層 RDL:重佈線 RS1:第一背面 RS2:第二背面 SUB:電路基底 T:鋸帶 TR:溝槽 UF1、UF2:底膠 W1:虛擬半導體晶圓 WS:壁結構 I-I'、II-II':線
根據結合附圖閱讀的以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特性未按比例繪製。事實上，可出於論述清楚起見而任意地增大或減小各種特徵的尺寸。 圖1A至圖1C示意性地示出根據本揭露的一些實施例用於製造虛擬晶粒的製程流程。 圖2示意性地示出根據本揭露的一些實施例的單體化虛擬晶粒的透視圖。 圖3A至圖3K示意性地示出根據本揭露的一些實施例用於製造基底上晶圓上晶片（Chip-on-Wafer-on-Substrate；CoWoS）封裝的製程流程。 圖4示意性地示出根據本揭露的一些實施例的圖3A中所示出的插入件及圖2中所示出的單體化虛擬晶粒的透視圖。 圖5示意性地示出根據本揭露的一些實施例的圖3K中所示出的CoWoS封裝的俯視圖。 圖6示意性地示出根據本揭露的一些實施例的沿圖5中所繪示的線II-II'的截面視圖。 圖7及圖8示意性地示出根據本揭露的各種實施例的CoWoS封裝的截面視圖。 圖9至圖11示意性地示出根據本揭露的各種實施例的CoWoS封裝的俯視圖。
200:光子積體電路晶粒
200a:電氣接合部分
200b:光輸入/輸出部分
200c:凹槽
300a:電積體電路晶粒
400b:經研磨絕緣包封體
D:周邊區域/半導體障壁
D1:距離
UF1、UF2:底膠
G:膠層
P:突部
N:凹口
FB:光纖
RDL:重佈線
B3:導電凸塊
SUB:電路基底

Claims (20)

  1. 一種結構，包括： 光子積體電路晶粒，包括光輸入/輸出部分及位置鄰近於所述光輸入/輸出部分的凹槽； 電積體電路晶粒，安置於所述光子積體電路晶粒上方且電性連接至所述光子積體電路晶粒； 半導體障壁，安置於所述光子積體電路晶粒上方；以及 絕緣包封體，安置於所述光子積體電路晶粒上方，側向地包封所述電積體電路晶粒，且與所述半導體障壁物理接觸。
  2. 如申請專利範圍第1項所述的結構，其中所述電積體電路晶粒經由多個微型凸塊電性連接至所述光子積體電路晶粒。
  3. 如申請專利範圍第1項所述的結構，其中所述半導體障壁包括凹口，且所述凹槽藉由所述半導體障壁的所述凹口暴露。
  4. 如申請專利範圍第3項所述的結構，更包括： 突部，安置於所述光子積體電路晶粒上方，其中所述突部藉由所述半導體障壁的所述凹口暴露。
  5. 如申請專利範圍第3項所述的結構，更包括： 膠層，在所述半導體障壁與所述光子積體電路晶粒之間。
  6. 如申請專利範圍第1項所述的結構，更包括位於所述凹槽內的至少一個光纖。
  7. 如申請專利範圍第1項所述的結構，更包括： 電路基底，其中所述光子積體電路晶粒安置於所述電路基底上方且電性連接至所述電路基底。
  8. 如申請專利範圍第7項所述的結構，更包括： 多個導電凸塊；以及 底膠，安置於所述電路基底與所述光子積體電路晶粒之間，其中所述光子積體電路晶粒經由所述導電凸塊電性連接至所述電路基底，且所述導電凸塊藉由所述底膠包封。
  9. 一種結構，包括： 光子積體電路晶粒，包括光輸入/輸出部分及與所述光輸入/輸出部分相鄰的光纖凹槽； 電積體電路晶粒及半導體障壁，以並列方式安置於所述光子積體電路晶粒上方，所述電積體電路晶粒電性連接至所述光子積體電路晶粒； 絕緣包封體，安置於所述光子積體電路晶粒上方，側向地包封所述電積體電路晶粒，且與所述半導體障壁的多個側面物理接觸，其中所述半導體障壁的側表面自絕緣包封體暴露，且所述半導體障壁使所述光纖凹槽與所述絕緣包封體分離；以及 至少一個光纖，位於所述光纖凹槽內。
  10. 如申請專利範圍第9項所述的結構，其中所述半導體障壁包括凹口，所述光纖凹槽藉由所述半導體障壁的所述凹口暴露，且所述絕緣包封體不位於所述半導體障壁的所述凹口中。
  11. 如申請專利範圍第10項所述的結構，更包括： 突部，安置於所述光子積體電路晶粒上方，其中所述突部藉由所述半導體障壁的所述凹口暴露。
  12. 如申請專利範圍第10項所述的結構，其中所述電積體電路晶粒的頂部表面與所述半導體障壁的頂部表面齊平。
  13. 如申請專利範圍第9項所述的結構，更包括： 電路基底，其中所述光子積體電路晶粒安置於所述電路基底上方且電性連接至所述電路基底。
  14. 如申請專利範圍第13項所述的結構，更包括： 多個導電凸塊；以及 底膠，安置於所述電路基底與所述光子積體電路晶粒之間，其中所述光子積體電路晶粒經由所述導電凸塊電性連接至所述電路基底，所述導電凸塊藉由所述底膠包封，且所述底膠的至少一部分由所述絕緣包封體覆蓋。
  15. 如申請專利範圍第13項所述的結構，其中所述底膠完全填充所述電積體電路晶粒與所述半導體障壁之間的空間。
  16. 如申請專利範圍第13項所述的結構，其中所述底膠及所述絕緣包封體完全填充所述電積體電路晶粒與所述半導體障壁之間的空間。
  17. 一種方法，包括： 提供光子積體電路晶粒，所述光子積體電路晶粒包括至少一個光輸入/輸出部分及至少一個凹槽； 將電積體電路晶粒及虛擬晶粒接合於所述光子積體電路晶粒上；以及 移除所述虛擬晶粒的一部分以形成具有凹口的半導體障壁，以使得所述至少一個凹槽藉由所述半導體障壁的所述凹口暴露。
  18. 如申請專利範圍第17項所述的方法，更包括： 將至少一個光纖組裝於所述至少一個凹槽中。
  19. 如申請專利範圍第17項所述的方法，更包括： 在移除所述虛擬晶粒的所述部分之前，將具有接合於其上的所述電積體電路晶粒及所述虛擬晶粒的所述光子積體電路晶粒安裝於電路基底上方。
  20. 如申請專利範圍第17項所述的方法，更包括： 在移除所述虛擬晶粒的所述部分之前，側向地包封接合於所述光子積體電路晶粒上的所述電積體電路晶粒及所述虛擬晶粒。
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