CN110660684A - 用于封装件集成的缓冲设计 - Google Patents

用于封装件集成的缓冲设计 Download PDF

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Publication number
CN110660684A
CN110660684A CN201910089333.9A CN201910089333A CN110660684A CN 110660684 A CN110660684 A CN 110660684A CN 201910089333 A CN201910089333 A CN 201910089333A CN 110660684 A CN110660684 A CN 110660684A
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device die
die
forming
dielectric
layer
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CN110660684B (zh
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陈洁
陈宪伟
陈明发
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种形成封装件的方法包括将器件管芯接合到中介层晶圆，其中，中介层晶圆包括金属线和通孔；形成介电区以包围器件管芯；以及形成贯通孔以穿透介电区。贯通孔通过中介层晶圆中的金属线和通孔电连接到器件管芯；在介电区上形成聚合物层；以及形成电连接件。电连接件通过聚合物层中的导电部件电连接到贯通孔；以及锯切中介层晶圆以将封装件与其他封装件分离。本发明的实施例还涉及用于封装件集成的缓冲设计。

Description

用于封装件集成的缓冲设计
技术领域
本发明的实施例涉及用于封装件集成的缓冲设计。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，需要将更多功能集成到半导体管芯中。因此，半导体管芯需要具有越来越多的封装到更小区域中的I/O焊盘，并且I/O焊盘的密度随时间上升。结果，半导体管芯的封装变得更加困难，这不利地影响了封装的产量。
传统的封装技术可以分为两类。在第一类中，晶圆上的管芯在锯切之前被封装。这种封装技术具有一些有利的特征，例如更高的产量和更低的成本。此外，需要较少的底部填充物或模塑料。然而，这种封装技术也存在缺点。由于管芯的尺寸变得越来越小，并且相应的封装件只能是扇入型封装件，其中每个管芯的I/O焊盘限于直接位于相应管芯的表面上方的区域。由于管芯的有限区域，由于I/O焊盘的间距的限制，I/O焊盘的数量受到限制。如果要减小焊盘的间距，则可能发生焊料桥接。另外，在固定的球尺寸要求下，焊球必须具有一定的尺寸，这又限制了可以封装在管芯的表面上的焊球的数量。
在另一类封装中，在封装之前从晶圆锯切管芯。这种封装技术的一个有利特征是可以形成扇出封装件，这意味着管芯上的I/O焊盘可以重新分布到比管芯更大的区域，因此封装在管芯的表面上的I/O焊盘的数量可以增加。该封装技术的另一个有利特征是封装了“已知良好管芯”，并且丢弃了有缺陷的管芯，因此不会在有缺陷的管芯上浪费成本和精力。
发明内容
本发明的实施例提供了一种形成半导体器件的方法，包括：形成第一封装件，包括：将第一器件管芯接合到中介层晶圆，其中，所述中介层晶圆包括金属线和通孔；形成介电区以包围所述第一器件管芯；形成贯通孔以穿透所述介电区，其中，所述贯通孔通过所述中介层晶圆中的所述金属线和通孔电连接到所述第一器件管芯；在所述介电区上形成聚合物层；形成电连接件，其中，所述电连接件通过所述聚合物层中的导电部件电连接到所述贯通孔；以及锯切所述中介层晶圆以将所述第一封装件与其他封装件分离。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：形成第一封装件，包括：将第一器件管芯和第二器件管芯接合到中介层管芯；将所述第一器件管芯和所述第二器件管芯包封在无机间隙填充材料中；在所述中介层管芯的金属焊盘上形成通孔，其中，所述通孔穿透所述无机间隙填充材料，并且通过所述中介层管芯电连接到所述第一器件管芯和所述第二器件管芯；在所述第一器件管芯、所述第二器件管芯和所述通孔上形成介电层；在所述介电层中形成金属部件，其中，使用镶嵌工艺形成所述金属部件；在所述金属部件上形成聚合物层，其中，所述聚合物层下面的所有介电材料都是无机材料；在所述聚合物层上形成电连接件；以及将所述第一封装件接合到第二封装件，其中，所述电连接件接合到所述第二封装件。
本发明的又一实施例提供了一种半导体器件，包括：第一封装件，包括：中介层管芯，在所述中介层管芯中没有有源器件；第一器件管芯和第二器件管芯，接合到所述中介层管芯；无机介电区，将所述第一器件管芯和所述第二器件管芯包封在其中；第一通孔，穿透所述无机介电区，其中，所述第一通孔通过所述中介层管芯电连接到所述第一器件管芯和所述第二器件管芯；介电层，位于所述第一器件管芯、所述第二器件管芯和所述第一通孔上；聚合物层，位于所述介电层上，其中，所述聚合物层下面的所有介电材料都是无机材料；以及电连接件，位于所述聚合物层上。
附图说明
当接合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图12是根据一些实施例的形成集成芯片上系统(SoIC)封装件的中间阶段的截面图。
图13至图18是根据一些实施例的形成集成扇出(InFO)封装件的中间阶段的截面图。
图19示出了根据一些实施例的包括接合到InFO封装件的SoIC封装件的封装件的截面图。
图20和图21示出了根据一些实施例的包括与InFO封装件接合的SoIC封装件的封装件的截面图。
图22示出了根据一些实施例的用于形成集成封装件的工艺流程，该集成封装件包括接合到InFO封装件的SoIC封装件。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，各个部件可以以不同的比例任意地绘制。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各种实施例提供了一种集成封装件及其形成方法，集成封装件包括接合到集成扇出(InFO)封装件的集成芯片上系统(SoIC)封装件。根据一些实施例示出了形成封装件的中间阶段。讨论了一些实施例的一些变型。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。
图1至图12示出了根据本发明的一些实施例的SoIC封装件的形成中的中间阶段的截面图。图1至12中所示的步骤也在图17中所示的工艺流程200中示意性地反映。
图1示出了晶圆2的形成中的截面图。根据本发明的一些实施例，晶圆2是中介层晶圆，其中没有任何有源器件，例如晶体管和/或二极管。根据本发明的一些实施例，中介层晶圆2也没有诸如电容器、电感器、电阻器等的无源器件。中介层晶圆2可以在其中包括多个金属线和通孔，其中示意性地示出一个中介层管芯4的一些细节。在下文中，中介层管芯4可选地称为中介层或芯片。中介层管芯4用于布线，如后续段落中所讨论的。
晶圆2可以包括衬底20和位于衬底20的顶面上的部件。根据本发明的一些实施例，衬底20是半导体衬底。衬底20可以由晶体硅、晶体锗、晶体硅锗和/或III-V族化合物半导体(例如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等)形成。半导体衬底20也可以是体硅衬底或绝缘体上硅(SOI)衬底。根据衬底20是半导体衬底的一些实施例，可以在衬底20中形成浅沟槽隔离(STI)区(未示出)以隔离衬底20中的区域。根据可选实施例，因为晶圆2不具有有源器件，所以在晶圆2中未形成STI区，因此不需要STI区来将有源区彼此隔离。衬底20也可以是介电衬底，例如，其可以由氧化硅形成。根据一些实施例，形成通孔(未示出)以延伸到半导体衬底20中，其中通孔用于电互连衬底20的相对侧上的部件。根据可选实施例，没有形成延伸到半导体衬底20中的通孔。
可以在衬底20上形成介电层24。根据本发明的一些实施例，介电层24是层间电介质(ILD)，其可以由氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等形成。可以使用热氧化、旋涂、可流动化学气相沉积(FCVD)、原子层沉积(ALD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)等来形成介电层24。
在介电层24上方存在互连结构26。互连结构26包括形成在介电层32中的金属线28和通孔30。在下文中，介电层32可选地称为金属间介电(IMD)层。根据本发明的一些实施例，介电层32由具有低于3.8的介电常数(k值)的低k介电材料形成。例如，介电层32的k值可以低于约3.0或低于约2.5。介电层32可以由Black Diamond(应用材料公司的注册商标)，含碳的低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。根据本发明的可选实施例，介电层32中的一些或全部由非低k介电材料形成，例如氧化硅、碳化硅(SiC)、碳氮化硅(SiCN)、碳氧氮硅(SiOCN)等。根据本发明的一些实施例，介电层32的形成包括沉积含致孔剂的介电材料，然后实施固化工艺以驱除致孔剂，因此剩余的介电层32是多孔的。可以由碳化硅、氮化硅等形成的蚀刻停止层(未示出)形成在IMD层32之间，并且为了简单起见未示出。
金属线28和通孔30形成在介电层32中。以下将相同层级处的金属线28统称为金属层。根据本发明的一些实施例，互连结构26包括通过通孔30互连的多个金属层。金属线28和通孔30可以由铜或铜合金形成，并且它们也可以由其他金属形成。形成工艺可以包括单镶嵌和双镶嵌工艺。在单镶嵌工艺中，首先在介电层32之一中形成沟槽，然后用导电材料填充沟槽。然后实施诸如CMP工艺的平坦化工艺以去除高于IMD层的顶面的导电材料的多余部分，在沟槽中留下金属线。在双镶嵌工艺中，沟槽和通孔开口都形成在IMD层中，其中通孔开口位于沟槽下方并且与沟槽空间连通。然后将导电材料填充到沟槽和通孔开口中以分别形成金属线和通孔。导电材料可以包括衬在沟槽和通孔上的扩散阻挡层以及位于扩散阻挡层上的含铜金属材料。扩散阻挡层可以包括钛、氮化钛、钽、氮化钽等。
图1示出了根据本发明的一些实施例的表面介电层34。表面介电层34由诸如氧化硅的非低k介电材料形成。表面介电层34可选地称为钝化层，因为它具有将下面的低k介电层(如果有的话)与有害化学品和湿气的不利影响隔离的功能。表面介电层34还可以具有包括多于一层的复合结构，其可以由氧化硅、氮化硅、未掺杂的硅酸盐玻璃(USG)等形成。中介层管芯4还可以包括位于表面介电层34下面的金属焊盘，并且金属焊盘可以包括铝或铝铜焊盘，为简单起见未示出钝化后互连件(PPI)等。
在表面介电层34中形成接合焊盘36A和36B，其也共同且单独地称为接合焊盘36。根据本发明的一些实施例，接合焊盘36A和36B通过单镶嵌工艺形成，并且还可以包括阻挡层和形成在阻挡层上的含铜材料。根据本发明的可选实施例，通过双镶嵌工艺形成接合焊盘36A和36B。一些接合焊盘36A可以通过金属线28和通孔30电耦合到其他接合焊盘36A和36B。根据本发明的一些实施例，接合焊盘36A和接合焊盘36B中的每一个通过金属线28和通孔30电连接到至少一个(或者更多)其他接合焊盘36A和36B，并且接合焊盘36A和36B都不与所有其他接合焊盘36A和36B电断开。
根据本发明的一些实施例，在晶圆2中不存在诸如聚合物、树脂和模塑料的有机介电材料。有机介电层通常具有高的热膨胀系数(CTE)，例如10ppm/C°或更高。这显著大于硅衬底(例如衬底20)的CTE，硅衬底的CTE为约3ppm/℃。因此，有机介电层倾向于引起晶圆2的翘曲。晶圆2中不包括有机材料有利地减少了晶圆2中的层之间的CTE失配，并且导致所得到的SoIC封装件86(图12)的翘曲减小。而且，晶圆2中不包括有机材料使得可以形成细间距金属线(例如图12中的66)和高密度接合焊盘，并且导致路由能力的提高。平坦化顶面介电层34和接合焊盘36，使得它们的顶面是共面的，这可能是由于接合焊盘36的形成中的CMP而产生的。
接下来，器件管芯42A和42B接合到晶圆2，如图2所示。相应的工艺示出为图22中所示的工艺流程中的工艺202。根据本发明的一些实施例，器件管芯42A和42B是存储器管芯，例如动态随机存取存储器(DRAM)管芯或静态随机存取存储器(SRAM)管芯。器件管芯42A和42B中的每一个还可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。器件管芯42A和42B可以是从上面列出的类型中选择的相同类型或不同类型的管芯。此外，器件管芯42A和42B可以使用不同的技术形成，例如45nm技术、28nm技术、20nm技术等。管芯4、器件管芯42A和器件管芯42B组合起来作为封装件，其可以是存储器封装件或逻辑封装件。
器件管芯42A和42B分别包括衬底44A和44B，衬底44A和44B可以是诸如硅衬底的半导体衬底。根据一些实施例，衬底44A和44B也称为半导体衬底44A和44B。根据本发明的一些实施例，器件管芯42A和42B中没有硅通孔(TSV)。而且，器件管芯42A和42B分别包括互连结构48A和48B，用于连接到器件管芯42A和42B中的有源器件和无源器件。互连结构48A和48B包括示意性地示出的金属线和通孔。衬底44A和44B中没有通孔。因此，器件管芯42A和42B的所有外部电连接件都是通过接合焊盘50A和50B制成的。
器件管芯42A包括在所示底面处的接合焊盘50A和介电层52A。接合焊盘50A的底面与介电层52A的底面共面。器件管芯42B包括在所示底面处的接合焊盘50B和介电层52B。接合焊盘50B的底面与介电层52B的底面共面。根据本发明的一些实施例，器件管芯42A和42B不含有机介电材料，例如聚合物、树脂、模塑料等。
可以通过混合接合来实现器件管芯42A和42B与晶圆2的接合。例如，接合焊盘50A和50B通过金属-金属直接接合接合到接合焊盘36A。根据本发明的一些实施例，金属-金属直接接合是铜-铜直接接合。此外，介电层52A和52B接合到表面介电层34，例如，产生熔合接合(可以包括Si-O-Si键)。
为了实现混合接合，首先通过将器件管芯42A和42B轻轻压在中介层管芯4上，将器件管芯42A和42B预接合到表面介电层34和接合焊盘36A。尽管示出了两个器件管芯42A和42B，但是可以在晶圆级实施混合接合，并且预接合与包括器件管芯42A和42B的所示管芯组相同的多个器件管芯组，并且布置为行和列。
在预接合所有器件管芯42A和42B之后，实施退火以引起接合焊盘36A和相应的上面的接合焊盘50A和50B中的金属的相互扩散。根据一些实施例，退火温度可以在约200°和约400℃之间的范围内，并且可以在约300°和约400℃之间的范围内。根据一些实施例，退火时间在约1.5小时和约3.0小时之间的范围内，并且可以在约1.5小时和约2.5小时之间的范围内。通过混合接合，接合焊盘50A和50B通过由金属相互扩散引起的直接金属接合而接合到相应的接合焊盘36A。
表面介电层34也接合到介电层52A和52B，在表面介电层34与介电层52A和52B之间形成接合。例如，表面介电层34和介电层52A/52B之一中的原子(例如氧原子)与表面介电层34和介电层52A/52B中的另一个中的原子(例如硅原子)形成化学键或共价键。表面介电层34和介电层52A/52B之间产生的接合是电介质-电介质接合。接合焊盘50A和50B的尺寸可以大于、等于或小于相应接合焊盘36A的尺寸。间隙46留在相邻的器件管芯42A和42B之间。
进一步参考图2，可以对薄器件管芯42A和42B实施背面研磨至例如厚度在约15μm和约30μm之间。图2示意性地示出了虚线44A-BS1和44B-BS1，它们分别是在背面研磨之前的器件管芯42A和42B的背面。44A-BS2和44B-BS2分别是在背面研磨之后的器件管芯42A和42B的背面。通过减薄器件管芯42A和42B，减小了相邻器件管芯42A和42B之间的间隙46的高宽比。否则，由于间隙46的高高宽比，间隙填充可能是困难的。根据其他实施例，其中间隙46的高宽比对于间隙填充而言不太高，跳过背面研磨。
图3示出了间隙填充层/区域54和56的形成。相应的工艺示出为图22中所示的工艺流程中的工艺204。根据本发明的一些实施例，间隙填充层包括介电层54以及位于蚀刻停止层54上并且与蚀刻停止层54接触的介电层56。可以使用诸如原子层沉积(ALD)或化学气相沉积(CVD)的共形沉积方法来沉积介电层54。根据一些实施例，介电层54也称为蚀刻停止层或介电衬垫。可以使用共形沉积方法或非共形沉积方法(诸如高密度等离子体化学气相沉积(HDPCVD)、可流动化学气相沉积(CVD)、旋涂等)来形成介电层56。根据本发明的一些实施例，间隙填充层不含有机材料，例如聚合物、树脂、模塑料等。
蚀刻停止层54由介电材料形成，该介电材料对器件管芯42A和42B的顶面和侧壁以及表面介电层34和接合焊盘36B的顶面具有良好的粘附性。蚀刻停止层54也在器件管芯42A和42B的顶面上延伸。根据本发明的一些实施例，蚀刻停止层54由诸如氮化硅的含氮化物材料形成。蚀刻停止层54的厚度T1(包括T1A和T1B)可以在约
Figure BDA0001962785710000091
和约之间的范围内。应理解，整个说明书中引用的值是示例，并且可以使用不同的值。蚀刻停止层54可以是共形层，例如，水平部分的厚度T1A和垂直部分的厚度T1B基本上彼此相等，例如，差值(T1A-T1B)的绝对值小于厚度T1A和T1B的约20％或小于约10％。
介电层56由与蚀刻停止层54的材料不同的材料形成。介电层56可以由无机介电材料形成。根据本发明的一些实施例，介电层56包括诸如氧化硅的氧化物，氧化硅可以由TEOS形成，但是当介电层56和蚀刻停止层54之间存在足够的蚀刻选择性(例如，高于约50)时，也可以使用其他介电材料，例如碳化硅、氮氧化硅、碳氧氮化硅等。蚀刻选择性是在后续工艺中蚀刻介电层56时介电层56的蚀刻速率与蚀刻停止层54的蚀刻速率的比率。介电层56完全填充间隙46(图2)，并且还包括与器件管芯42A和42B重叠的一些部分。介电层56可以由非共形形成方法或共形形成方法形成。
实施诸如CMP工艺或机械研磨工艺的平坦化工艺以去除介电层56的多余部分。根据本发明的一些实施例，当存在介电层56的与器件管芯42A和42B重叠的层时停止平坦化。因此，不抛光蚀刻停止层54。根据本发明的可选实施例，使用蚀刻停止层54作为CMP停止层来实施平坦化。结果，当停止平坦化时，蚀刻停止层54的顶面54A暴露，并且存在与器件管芯42A和42B重叠的蚀刻停止层54的剩余水平部分。根据本发明的其他实施例，在器件管芯42A的衬底44A和器件管芯42B的衬底44B暴露之后停止平坦化。蚀刻停止层54和介电层56的剩余部分统称为(间隙填充)隔离区58。隔离区58也称为无机间隙填充(或间隙填充)区。
图4示出了介电层56的蚀刻以形成开口59。相应的工艺示出为图22中所示的工艺流程中的工艺206。根据本发明的一些实施例，形成并且图案化光刻胶(未示出)，并且使用图案化的光刻胶作为蚀刻掩模蚀刻介电层56。因此形成开口59，并且向下延伸到蚀刻停止层54。根据本发明的一些实施例，介电层56包括氧化物，并且蚀刻可以通过干蚀刻来实施。蚀刻气体可以包括NF3和NH3的混合物，或HF和NH3的混合物。使用蚀刻顶层54来停止用于形成开口59的蚀刻允许同一晶圆2上的多个开口59的向下行进在相同的中间层级处同步，使得较快蚀刻的开口59将在它们再次向下延伸之前等待较慢蚀刻的开口59。
接下来，蚀刻蚀刻停止层54，使得开口59向下延伸到接合焊盘36B。根据本发明的一些实施例，蚀刻停止层54包括氮化硅，并且使用干蚀刻实施蚀刻。蚀刻气体可以包括CF4、O2和N2的混合物，NF3和O2的混合物，SF6，或SF6和O2的混合物。
图5示出了通孔60的形成，通孔60填充开口59(图4)，并且连接到接合焊盘36B。相应的工艺示出为图22中所示的工艺流程中的工艺208。根据本发明的一些实施例，通孔60的形成包括实施诸如电化学镀工艺或化学镀工艺的镀工艺。通孔60可以包括金属材料，例如钨、铝、铜等。还可以在金属材料下面形成导电阻挡层(例如钛、氮化钛、钽、氮化钽等)。实施诸如CMP工艺的平坦化工艺以去除镀的金属材料的多余部分，并且金属材料的剩余部分形成通孔60。通孔60可以具有基本笔直和垂直的侧壁。而且，通孔60可以具有锥形轮廓，顶部宽度WT略大于相应的底部宽度WB。根据一些实施例，如图5所示，形成单个通孔60以接触每个接合焊盘36B。根据可选实施例，多个通孔60(例如两个或三个)形成在相同的接合焊盘36B上并且与相同的接合焊盘36B接触。
参考图6，形成可以是无机层的介电层62。相应的工艺示出为图22中所示的工艺流程中的工艺210。根据本发明的一些实施例，介电层62由k值低于3.8的低k介电材料形成，并且k值例如可以低于约3.0，低于约2.5。根据可选实施例，介电层62由诸如氧化硅的氧化物、诸如氮化硅的氮化物等形成。然后在光刻工艺中图案化介电层62以形成开口64，并且暴露通孔60。
然后形成金属部件66，如图7所示。相应的工艺也示出为图22所示的工艺流程中的工艺210。金属部件66可以包括金属线和金属焊盘，并且可以使用镶嵌工艺形成。镶嵌工艺包括将共形导电阻挡层沉积到开口64(图6)中，镀诸如铜或铜合金的金属材料，以及实施平坦化以去除金属部件66的多余部分。金属部件66可以具有如图7所示的单镶嵌结构。根据本发明的其他实施例，金属部件66具有双镶嵌结构。
根据本发明的一些实施例，包括介电层62和所有下面的结构的组合结构不含有机材料(例如聚合物层、模塑料、树脂等)，因此用于形成金属部件66的工艺可以采用用于形成器件管芯的工艺，并且可以实现具有小间距和线宽的细间距金属线66。
图8示出了金属焊盘68的形成。相应的工艺示于图22所示的工艺流程中的工艺212。根据一些实施例，金属焊盘68由铝铜形成。形成可以包括沉积金属层，以及图案化金属层。蚀刻的金属层的剩余部分是金属焊盘68。
图9示出了钝化层70和聚合物层72的形成。根据一些实施例，钝化层70形成在介电层62上并与介电层62接触。钝化层70可以是单层或复合层，并且可以由非多孔材料形成。根据本发明的一些实施例，钝化层70是复合层，其包括氧化硅层(未单独示出)以及位于氧化硅层上的氮化硅层(未单独示出)。钝化层70还可以由其他非多孔介电材料形成，例如未掺杂的硅酸盐玻璃(USG)、氮氧化硅等。
接下来，图案化钝化层70，使得金属焊盘68的一些部分通过钝化层70中的开口暴露。然后形成聚合物层72。相应的工艺示出为图22所示的工艺流程中的工艺214。聚合物层72可以由聚酰亚胺、聚苯并恶唑(PBO)等形成。也图案化聚合物层72以形成开口，金属焊盘68通过该开口暴露。根据一些实施例，聚合物层72具有大的厚度，其可以在约3μm和约6μm之间的范围内。
参考图10，形成再分布线(RDL)74，并且RDL 74的通孔部分延伸到聚合物层72(图9)中的开口中以电连接到金属焊盘68。相应的工艺示出为图22所示的工艺流程中的工艺216。可以理解，RDL 74可以包括金属焊盘和金属线，并且可以用于布线，使得RDL 74中的金属焊盘可以重新路由到与器件管芯42A和42B重叠的区域中。
图11示出了聚合物层76的形成，其可以由聚酰亚胺、PBO等形成。相应的工艺示出为图22所示的工艺流程中的工艺218。在聚合物层76中形成开口78以露出RDL 74。根据一些实施例，聚合物层76具有很大的厚度，其可以在约5μm和约10μm之间的范围内。由于聚合物层72和76具有低杨氏模量，其远低于由无机材料形成的下面的层中的杨氏模量，因此聚合物层72和76可以吸收所得封装件中的应力。由于聚合物层72和76具有大的厚度，它们吸收应力的能力得到改善。例如，聚合物层72和76下面的结构(下面的结构)包括晶圆2、器件管芯42A和42B以及介电层56，可以包括或不包括聚合物。当下面的层不包括聚合物时，由于它们吸收应力的能力，封装件可受益于聚合物层72和76。
参考图12，形成凸块下金属(UBM)80，并且UBM 80延伸到聚合物层76中以连接到RDL 74。根据本发明的一些实施例，每个UBM 80包括阻挡层(未示出)和位于阻挡层上的晶种层(未示出)。阻挡层可以是钛层、氮化钛层、钽层、氮化钽层或由钛合金或钽合金形成的层。晶种层的材料可以包括铜或铜合金。在UBM 80中也可以包括其他金属，如银、金、铝、钯、镍、镍合金、钨合金、铬、铬合金及其组合。根据一些实施例，UBM 80的形成包括沉积毯状阻挡层和毯状晶种层，在晶种层上形成图案化的蚀刻掩模(例如图案化的光刻胶)，然后蚀刻毯状晶种层和毯状阻挡层。根据其他实施例，UBM 80的形成包括沉积毯状阻挡层和毯状晶种层，在毯状晶种层上形成图案化的镀掩模(例如图案化的光刻胶)，在图案化的镀掩模中的开口中镀金属柱，去除图案化的镀掩模，然后蚀刻先前由图案化的镀掩模覆盖的毯状晶种层和毯状阻挡层的部分。
还如图12所示，电连接件82形成在UBM 80上并且与UBM 80接触。相应的工艺在图22所示的工艺流程中示为工艺220。电连接件82可以包括金属柱、焊料区等。在整个说明书中，图12中所示的结构称为复合晶圆84。对复合晶圆84实施管芯锯切(分割)步骤，以将复合晶圆84分离成多个SoIC封装件86。相应的工艺示出为图22所示的工艺流程中的工艺222。
图13至图18示出了根据一些实施例的集成扇出(InFO)封装件的形成中的中间阶段的截面图。参照图13，提供载体120，并且在载体120上形成释放膜122。载体120由透明材料形成，并且可以是玻璃载体、陶瓷载体、有机载体等。释放膜122可以由光-热转换(LTHC)涂层材料形成，其通过涂层布施加到载体120上。根据一些实施例，释放膜122也称为LTHC涂层材料。根据本发明的一些实施例，LTHC涂层材料能够在光/辐射(例如激光)的热量下分解，因此可以从形成在其上的结构释放载体120。
根据一些实施例，也如图1所示，聚合物缓冲层124形成在LTHC涂层材料122上。根据一些实施例，聚合物缓冲层124由PBO、聚酰亚胺、苯并环丁烯(BCB)或其他适用的聚合物形成。
例如，通过物理气相沉积(PVD)形成金属晶种层126。相应的工艺示出为图22中所示的工艺流程中的工艺230。金属晶种层126可以与聚合物缓冲层124物理接触。根据本发明的一些实施例，金属晶种层126包括钛层和位于钛层上的铜层。根据本发明的可选实施例，金属晶种层126包括与LTHC涂层材料122接触的铜层。
在金属晶种层126上形成光刻胶128。相应的工艺也示出为图22所示的工艺流程中的工艺230。然后使用光刻掩模(未示出)对光刻胶128实施曝光。在随后的显影之后，在光刻胶128中形成开口130。金属晶种层126的一些部分通过开口130暴露。接下来，通过在开口130中镀金属材料来形成金属柱132。镀的金属材料可以是铜或铜合金。相应的工艺示出为图22中所示的工艺流程中的工艺232。
在随后的步骤中，去除光刻胶128，因此暴露下面的金属晶种层126的部分。然后在蚀刻步骤中去除金属晶种层126的暴露部分，例如，在各向异性或各向同性蚀刻步骤中。因此，剩余金属晶种层126的边缘与相应上面的金属柱132的部分共末端。所得到的金属柱132在图14中示出。在整个说明书中，金属晶种层126的剩余部分被认为是金属柱132的一部分，并且可以不单独示出。金属柱132的顶视图形状包括但不限于圆形、矩形、六边形、八边形等。
图15示出了器件管芯136的放置/附接。相应的工艺示出为图22中所示的工艺流程中的工艺234。器件管芯136通过管芯连接膜(DAF)138连接到聚合物缓冲层124。DAF 138是在器件管芯136放置在聚合物缓冲层124上之前预先附接在器件管芯136上的粘合膜。因此，DAF 138和器件管芯136在附接到聚合物缓冲层124之前组合成集成件。器件管芯136可以包括具有与DAF 138物理接触的背面(面向下的表面)的半导体衬底。器件管芯136可以包括位于半导体衬底的正面(面向上的表面)的集成电路器件(例如有源器件，包括例如未示出的晶体管)。根据本发明的一些实施例，器件管芯136是逻辑管芯，其可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯、应用处理器(AP)管芯等。由于载体120处于晶圆级，尽管示出了一个器件管芯136，但是多个器件管芯136放置在聚合物缓冲层124上，并且可以分布为包括多个行和多个列的阵列。
根据一些示例性实施例，金属柱142(诸如铜柱)预形成为器件管芯136的一部分，并且金属柱142电耦合到器件管芯136中的集成电路器件(例如晶体管(未示出))。根据本发明的一些实施例，诸如聚合物的介电材料填充相邻金属柱142之间的间隙以形成顶部介电层144。顶部介电层144还可以包括覆盖和保护金属柱142的部分。根据本发明的一些实施例，顶部介电层144可以是聚合物层，其可以由PBO或聚酰亚胺形成。
接下来，将器件管芯136和金属柱132包封在包封材料148中，如图16所示。相应的工艺示于图22所示的工艺流程中的工艺236。包封材料148可以包括模塑料、模塑底部填充物、环氧树脂和/或树脂。当由模塑料形成时，包封材料148可以包括基底材料以及位于基底材料中的填料颗粒(未示出)，基底材料可以是聚合物、树脂、环氧树脂等。填料颗粒可以是SiO2、Al2O3、硅石等的介电颗粒，并且可以具有球形形状。而且，球形填料颗粒可以具有多种不同的直径。模塑料中的填料颗粒和基底材料均可与聚合物缓冲层124物理接触。
如所设置的，包封材料148的顶面高于金属柱142和金属柱132的顶端。在随后的步骤中，如图16所示，实施平坦化工艺，例如CMP工艺或机械研磨工艺，以减薄包封材料148和顶部介电层144，直到暴露金属柱132和金属柱142。金属柱132可选地称为通孔132，因为它们穿透包封材料148。由于平坦化工艺，通孔132的顶端与金属柱142的顶面基本齐平(共面)，并且基本上与包封材料148的顶面共面。
图17示出了正面再分布结构150的形成，其包括介电层152和位于介电层152中的RDL 154。相应的工艺示出为图22所示的工艺流程中的工艺238。在本发明的一些实施例中，介电层152由诸如PBO、聚酰亚胺等的聚合物形成。根据本发明的可选实施例，介电层152由诸如氮化硅、氧化硅等的无机介电材料形成。
根据本发明的一些实施例，介电层152和相应的RDL 154的形成可以包括沉积介电层152，在相应的介电层152中形成通孔开口以暴露下面的导电部件，沉积金属晶种层(未示出)，在相应的金属晶种层上形成和图案化光刻胶(未示出)，以及在金属晶种层上镀诸如铜和/或铝的金属材料。然后去除图案化的光刻胶，接着蚀刻先前被图案化的光刻胶覆盖的金属晶种层的部分。
图18示出了UBM 156的形成。图案化顶部介电层152以形成开口，并且UBM 156形成为延伸到顶部介电层152中的开口中以接触RDL 154中的金属焊盘。UBM 156可以由镍、铜、钛或其多层形成。根据一些示例性实施例，UBM 156包括钛层和位于钛层上的铜层。
然后形成电连接件158。相应的工艺示出为图22所示的工艺流程中的工艺240。电连接件158的形成可以包括将焊球放置在UBM 156的暴露部分上，然后将焊球回流成焊料区。在整个说明书中，包括聚合物缓冲层124的结构和上面的结构组合称为封装件160，封装件160是包括多个器件管芯136的复合晶圆(下文中也称为复合晶圆160)。接下来，例如，通过将激光束投射到LTHC涂层材料122上，从而分解LTHC涂层材料122，将复合晶圆160从载体120释放，从载体120卸下复合晶圆160。复合晶圆160中包括多个InFO封装件162。
图19示出了封装88的形成，其包括将SoIC封装件86接合到InFO封装件162。相应的工艺示出为图22中所示的工艺流程中的工艺242。根据本发明的一些实施例，多个SoIC封装件86接合到复合晶圆160，SoIC封装件86的电连接件82穿透InFO封装件162的聚合物缓冲层124以接合到通孔132。底部填充区90分配到SoIC封装件86和InFO封装件162之间的间隙中。然后，将得到的复合晶圆160分割，得到多个封装件88。相应的工艺示出为图22所示的工艺流程中的工艺244。
图20和图21示出了根据本发明的一些实施例的封装件88。除了省略图19中的一些部件之外，根据这些实施例的封装件88类似于图19所示的封装件88。根据本发明的一些实施例，可以省略如图19中所示的金属焊盘68和钝化层70。得到的图在图20中示出。根据本发明的一些其他实施例，省略了如图19中所示的金属焊盘68、钝化层70、RDL 74和聚合物层72。得到的图在图21中示出。根据本发明的一些实施例，当省略聚合物层72时，聚合物层76的厚度可以(或可以不)增加至例如约8μm和约16μm，这样可以保持聚合物吸收应力的能力。
在以上示出的实施例中，根据本发明的一些实施例讨论了一些工艺和部件。还可以包括其他部件和工艺。例如，可以包括测试结构以帮助3D封装或3DIC器件的验证测试。例如，测试结构可以包括形成在再分布层中或衬底上的允许使用探针和/或探针卡等来测试3D封装或3DIC的测试焊盘。可以对中间结构以及最终结构实施验证测试。另外，本文所公开的结构和方法可以与测试方法结合使用，测试方法结合已知良好管芯的中间验证以增加产量并且降低成本。
本发明的实施例具有一些有利特征。由于SoIC封装件的部分(如图8所示)不含聚合物、树脂和模塑料，因此SoIC封装件的这部分中的CTE失配减小，SoIC封装件的这部分内部的应力减小。因此，由于翘曲的减少，可以形成细间距RDL。一些无机材料很硬并且具有高杨氏模量。如果不含聚合物，SoIC封装件将具有高硬度值。例如，在SoIC封装件中使用的氮化硅具有大于100的杨氏模量。另一方面，诸如聚酰亚胺和PBO的聚合物具有等于约3.5或更低的杨氏模量。因此，添加的聚合物层可以吸收不能由SoIC封装件中的硬质无机材料吸收的应力。实验结果表明，如果SoIC封装件不含聚合物，则在将SoIC封装件接合到包括未锯切的InFO封装件的复合晶圆之后，接合可能会断裂，并且SoIC封装件将从复合晶圆上脱落。通过形成聚合物层以吸收应力，SoIC封装件和复合晶圆之间的接合不会受到应力的损害。
根据本发明的一些实施例，一种方法包括形成第一封装件，包括：将第一器件管芯接合到中介层晶圆，其中，中介层晶圆包括金属线和通孔；形成间隙填充区以包围第一器件管芯；形成贯通孔以穿透间隙填充区，其中贯通孔通过中介层晶圆中的金属线和通孔电连接到第一器件管芯；在间隙填充区上形成聚合物层；形成电连接件，其中电连接件通过聚合物层中的导电部件电连接到贯通孔；以及锯切中介层晶圆以将第一封装件与其他封装件分离。在一个实施例中，形成间隙填充区包括在中介层晶圆和第一器件管芯的表面上形成介电衬垫；在介电衬垫上填充介电材料；以及平坦化介电材料。在一个实施例中，在平坦化之后，介电衬垫包括与第一器件管芯重叠的部分。在一个实施例中，中介层晶圆中没有有源器件。在一个实施例中，聚合物层下面的所有介电材料都是无机材料。在一个实施例中，该方法还包括形成第二封装件，包括：形成金属柱；将金属柱和第二器件管芯包封在包封材料中；以及将第二封装件接合到第一封装件。在一个实施例中，该方法还包括将第二器件管芯接合到中介层晶圆，其中金属线和通孔将第一器件管芯电连接到第二器件管芯，并且间隙填充区包括分隔第一器件管芯与第二个器件管芯的部分。在一个实施例中，间隙填充区由无机介电材料形成
根据本发明的一些实施例，一种方法包括形成第一封装件，包括将第一器件管芯和第二器件管芯接合到中介层管芯；将第一器件管芯和第二器件管芯包封在无机间隙填充材料中；在中介层管芯的金属焊盘上形成通孔，其中通孔穿透无机间隙填充材料，并且通过中介层管芯电连接到第一器件管芯和第二器件管芯；在第一器件管芯、第二器件管芯和通孔上形成介电层；在介电层中形成金属部件，其中使用镶嵌工艺形成金属部件；在金属部件上形成聚合物层，其中聚合物层下面的所有介电材料都是无机材料；在聚合物层上形成电连接件；以及将第一封装件接合到第二封装件，其中电连接件接合到第二封装件。在一个实施例中，包封第一器件管芯和第二器件管芯包括沉积与第一器件管芯、第二器件管芯和中介层管芯接触的蚀刻停止层；在蚀刻停止层上形成介电材料；以及平坦化介电材料。在一个实施例中，中介层管芯没有有源器件和无源器件，并且从第一器件管芯和第二器件管芯到第二封装件的所有电连接都通过中介层管芯。在一个实施例中，形成介电层包括形成第一低k介电层。在一个实施例中，聚合物层与第一低k介电层物理接触。在一个实施例中，中介层管芯包括第二低k介电层，并且第一低k介电层和第二低k介电层位于无机间隙填充材料的相对侧上。
根据本发明的一些实施例，一种器件包括第一封装件，第一封装件包括其中没有有源器件的中介层管芯；第一器件管芯和第二器件管芯，接合到中介层管芯；无机间隙填充区，将第一器件管芯和第二器件管芯包封在其中；第一通孔，穿透无机间隙填充区，其中第一通孔通过中介层管芯电连接到第一器件管芯和第二器件管芯；介电层，位于第一器件管芯、第二器件管芯和第一通孔上；聚合物层，位于介电层上，其中聚合物层下面的所有介电材料都是无机材料；以及电连接件，位于聚合物层上。在一个实施例中，器件还包括位于第一封装件上并且与所述第一封装件接合的第二封装件，其中第二封装件包括：第三器件管芯；模塑料，将第三器件管芯包封在其中；以及第二通孔，穿过模塑料，其中第二通孔中的一个接合到电连接件。在一个实施例中，该器件还包括位于介电层中的金属部件，其中金属部件具有镶嵌结构。在一个实施例中，介电层是低k介电层。在一个实施例中，无机间隙填充区包括衬于中介层管芯、第一器件管芯和第二器件管芯的表面的氮化硅层；以及氧化物层，位于氮化硅层上，其中氮化硅层和氧化物层都包括与第一器件管芯重叠的部分。在一个实施例中，第一器件管芯和第二器件管芯通过中介层管芯中的导线电互连。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
形成第一封装件，包括：
将第一器件管芯接合到中介层晶圆，其中，所述中介层晶圆包括金属线和通孔；
形成介电区以包围所述第一器件管芯；
形成贯通孔以穿透所述介电区，其中，所述贯通孔通过所述中介层晶圆中的所述金属线和通孔电连接到所述第一器件管芯；
在所述介电区上形成聚合物层；
形成电连接件，其中，所述电连接件通过所述聚合物层中的导电部件电连接到所述贯通孔；以及
锯切所述中介层晶圆以将所述第一封装件与其他封装件分离。
2.根据权利要求1所述的方法，其中，形成所述介电区包括：
在所述中介层晶圆和所述第一器件管芯的表面上形成介电衬垫；
在所述介电衬垫上填充介电材料；以及
平坦化所述介电材料。
3.根据权利要求2所述的方法，在所述平坦化之后，所述介电衬垫包括与所述第一器件管芯重叠的部分。
4.根据权利要求1所述的方法，其中，所述中介层晶圆中没有有源器件。
5.根据权利要求1所述的方法，其中，所述聚合物层下面的所有介电材料都是无机材料。
6.根据权利要求1所述的方法，还包括：
形成第二封装件，包括：
形成金属柱；
将所述金属柱和第二器件管芯包封在包封材料中；以及
将所述第二封装件接合到所述第一封装件。
7.根据权利要求1所述的方法，还包括将第二器件管芯接合到所述中介层晶圆，其中，所述金属线和通孔将所述第一器件管芯电连接到所述第二器件管芯，并且所述介电区包括分隔所述第一器件管芯与所述第二个器件管芯的部分。
8.根据权利要求1所述的方法，其中，通过混合接合将所述第一器件管芯接合至所述中介层晶圆。
9.一种形成半导体器件的方法，包括：
形成第一封装件，包括：
将第一器件管芯和第二器件管芯接合到中介层管芯；
将所述第一器件管芯和所述第二器件管芯包封在无机间隙填充材料中；
在所述中介层管芯的金属焊盘上形成通孔，其中，所述通孔穿透所述无机间隙填充材料，并且通过所述中介层管芯电连接到所述第一器件管芯和所述第二器件管芯；
在所述第一器件管芯、所述第二器件管芯和所述通孔上形成介电层；
在所述介电层中形成金属部件，其中，使用镶嵌工艺形成所述金属部件；
在所述金属部件上形成聚合物层，其中，所述聚合物层下面的所有介电材料都是无机材料；
在所述聚合物层上形成电连接件；以及
将所述第一封装件接合到第二封装件，其中，所述电连接件接合到所述第二封装件。
10.一种半导体器件，包括：
第一封装件，包括：
中介层管芯，在所述中介层管芯中没有有源器件；
第一器件管芯和第二器件管芯，接合到所述中介层管芯；
无机介电区，将所述第一器件管芯和所述第二器件管芯包封在其中；
第一通孔，穿透所述无机介电区，其中，所述第一通孔通过所述中介层管芯电连接到所述第一器件管芯和所述第二器件管芯；
介电层，位于所述第一器件管芯、所述第二器件管芯和所述第一通孔上；
聚合物层，位于所述介电层上，其中，所述聚合物层下面的所有介电材料都是无机材料；以及
电连接件，位于所述聚合物层上。
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