CN110612599B - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN110612599B
CN110612599B CN201780090559.XA CN201780090559A CN110612599B CN 110612599 B CN110612599 B CN 110612599B CN 201780090559 A CN201780090559 A CN 201780090559A CN 110612599 B CN110612599 B CN 110612599B
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insulating film
transistor
semiconductor device
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gate electrode
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小山英寿
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Mitsubishi Electric Corp
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Abstract

在GaN类半导体层(3、4)之上形成源极电极(5)、漏极电极(6)、T型栅极电极(9)而形成晶体管。形成覆盖T型栅极电极(9)的绝缘膜(10、11)。对晶体管的特性进行评价。通过与评价结果对应地对绝缘膜(10、11)的膜种类、膜厚度或介电常数进行调整，从而使晶体管的特性接近作为目标的特性。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体装置的制造方法。
背景技术
在GaN类半导体晶体管中形成剖面为T型的栅极电极(例如，参照专利文献1)。在GaN类半导体晶体管的栅极周边的通常的制造工艺中，首先在半导体层的表面形成绝缘膜。接着，通过抗蚀层进行图案化而通过干蚀刻加工将形成栅极的区域的绝缘膜去除。接着，进行用于形成栅极金属的转印工艺，以比绝缘膜的开口尺寸长的尺寸的栅极金属成为攀至绝缘膜的形状的方式形成T型栅极电极。在T型栅极电极的栅极头和半导体层之间形成场板。
但是，在对绝缘膜进行干蚀刻而形成开口时，会对半导体层造成损伤。GaN类半导体晶体管与GaAs类半导体晶体管相比，容易在半导体内形成陷阱。由于该陷阱，脉冲IV特性降低，晶体管的特性降低。为了改善该情况，通常在GaN类半导体晶体管中采用场板构造。
另外，与GaAs类半导体晶体管相比，GaN类半导体晶体管在高电压下进行动作。因此，通过场板使栅极周边的电场得到缓和而将耐压提高。因此，就高耐压化而言，场板也是重要的。
专利文献1：日本特开2012-094726号公报
发明内容
为了形成T型栅极电极而针对绝缘膜的开口区域进行转印。如果该转印的对准产生偏差，则不能够得到作为目标的场板的尺寸。并且，在绝缘膜的开口尺寸产生了波动的情况下，也不能够得到作为目标的场板的尺寸。其结果，不能够得到作为目标的晶体管的特性。
还想到了以下状况，即，除了工艺波动之外又加入了外延波动，因此相对于作为目标的晶体管的特性来说的偏离会进一步变大。这些状况互相叠加，因此存在晶体管的特性以每个晶片为单位产生波动，成品率降低这样的问题。
本发明就是为了解决上述那样的课题而提出的，其目的在于得到能够对各个晶片的特性波动进行抑制的半导体装置的制造方法。
本发明涉及的半导体装置的制造方法的特征在于具备：在GaN类半导体层之上形成源极电极、漏极电极、T型栅极电极而形成晶体管的工序；形成覆盖所述T型栅极电极的绝缘膜的工序；对所述晶体管的特性进行评价的工序；以及通过与评价结果对应地对所述绝缘膜的膜种类、膜厚度或介电常数进行调整而使所述晶体管的特性接近作为目标的特性的工序。
发明的效果
在本发明中，通过在工艺中途对晶体管的特性进行评价，与评价结果对应地对绝缘膜的膜种类、膜厚度或介电常数进行调整而使晶体管的特性接近作为目标的特性。由此，能够对各个晶片的特性波动进行抑制。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图2是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图3是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图4是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图5是表示本发明的实施方式1涉及的半导体装置的制造方法的变形例1的剖视图。
图6是表示本发明的实施方式1涉及的半导体装置的制造方法的变形例2的剖视图。
图7是表示本发明的实施方式1涉及的半导体装置的制造方法的变形例3的剖视图。
图8是表示本发明的实施方式2涉及的半导体装置的制造方法的剖视图。
图9是表示本发明的实施方式2涉及的半导体装置的制造方法的剖视图。
图10是表示本发明的实施方式5涉及的半导体装置的制造方法的剖视图。
图11是表示本发明的实施方式6涉及的半导体装置的制造方法的剖视图。
图12是表示本发明的实施方式7涉及的半导体装置的制造方法的剖视图。
图13是表示本发明的实施方式8涉及的半导体装置的制造方法的剖视图。
具体实施方式
参照附图，对本发明的实施方式涉及的半导体装置的制造方法进行说明。对相同或对应的结构要素标注相同标号，有时省略重复说明。
实施方式1.
图1～4是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。首先，如图1所示，在SiC衬底1之上依次生长AlN缓冲层2、GaN沟道层3及AlGaN阻挡层4。也可以替代SiC衬底1而使用由Si、蓝宝石、GaN或AlN构成的衬底。在AlGaN阻挡层4之上形成源极电极5及漏极电极6。
然后，如图2所示，通过转印工艺形成抗蚀层7、8，通过蒸镀、溅射、镀敷等在源极电极5和漏极电极6之间形成T型栅极电极9。由此，形成晶体管。之后，去除抗蚀层7、8。
接着，如图3所示，形成覆盖T型栅极电极9整体的绝缘膜10。此时，没有通过绝缘膜10完全填埋T型栅极电极9和AlGaN阻挡层4之间，在T型栅极电极9的栅极头的下表面的绝缘膜10和AlGaN阻挡层4的上表面的绝缘膜10之间存在间隙。在T型栅极电极9的栅极头和AlGaN阻挡层4之间夹着T型栅极电极9的根部分的侧面的绝缘膜10而形成场板。
接着，对晶体管的特性进行评价。由于外延波动或栅极长度Lg波动，有时评价结果相对于作为目标的特性产生偏差。在该情况下，如图4所示，通过膜厚度控制性良好的制造方法在绝缘膜10之上形成绝缘膜11。此外，如果评价结果为与目标相同的特性，则进入下一个工序而不追加地形成绝缘膜11。
通过与评价结果对应地对绝缘膜11的膜厚度进行调整，从而对T型栅极电极9的根部分的侧面的绝缘膜10、11的膜厚度进行调整。由此，对在T型栅极电极9的栅极头和AlGaN阻挡层4之间形成的场板的尺寸FP进行调整，使晶体管的特性接近作为目标的特性。
例如，在栅极长度Lg比目标小的情况下，即使栅极头的宽度w与目标相同，尺寸FP也变长。如果尺寸FP变长，则脉冲IV特性提高，但电容成分增加，晶体管的特性恶化。另一方面，在栅极长度Lg比目标大的情况下，即使栅极头的宽度w与目标相同，尺寸FP也变短。如果尺寸FP变短，则脉冲IV特性劣化，晶体管特性恶化。因此，通过追加地形成绝缘膜11而与栅极长度Lg对应地对尺寸FP进行调整，从而能够得到作为目标的晶体管特性。
如以上说明所述，在本实施方式中，通过在工艺中途对晶体管的特性进行评价，与评价结果对应地对绝缘膜10、11的膜厚度进行调整，从而使晶体管的特性接近作为目标的特性。特别地，关于工艺波动，与晶片面内的波动相比各个晶片间的波动更大。因此，针对各个晶片进行晶体管的特性评价，相对于与作为目标的特性之间的偏差针对各个晶片对追加的绝缘膜11的膜厚度进行调整。由此，能够对各个晶片的特性波动进行抑制。其结果，能够提高成品率。另外，虽然并未达到工艺波动这样的程度但各个晶片的外延特性也产生波动，晶体管的特性评价成为还加入了外延波动的影响后的结果，因此还能够同时对与外延波动对应的各个晶片的波动进行抑制。
另外，以往，在为了制造T型栅极电极对绝缘膜进行干蚀刻而形成开口时会对半导体层造成损伤。另一方面，在本实施方式中，由于在形成T型栅极电极9后形成绝缘膜10、11，因此不会造成损伤，能够避免晶体管的特性降低。
另外，通过T型栅极电极9的根部分的侧面的绝缘膜10、11的膜厚度对尺寸FP进行调整。因此，不会产生以往那样的由转印造成的场板的对准偏差，因此能够使尺寸FP与目标相同。特别在使用了ALD法的情况下，由于能够进行原子层级别的膜厚度控制，因此尺寸FP的控制性变高。
但是，还设想到相对于抗蚀层7，抗蚀层8的转印对准产生偏差。因此，T型栅极电极9的栅极头的宽度w是以比作为目标的尺寸FP长的尺寸形成的。由于尺寸FP由绝缘膜10、11的膜厚度决定，因此不会受到转印的对准偏差的影响而能够得到作为目标的尺寸FP。另外，T型栅极电极9的根部分的高度H比设想的尺寸FP的2倍大。由此，没有通过绝缘膜10、11将T型栅极电极9的栅极头之下填充，因此能够得到良好的特性而没有增加多余的寄生电容。
另外，作为晶体管的特性的评价，对夹断(pinch off)特性、栅极-源极间耐压、栅极-漏极间耐压或脉冲IV特性等DC特性进行评价。或者，也可以通过RF的小信号特性评价，对小信号增益MSG/MAG、fk、互导gm、栅极-源极间电容Cgs、栅极-漏极间电容Cgd、漏极-源极间电容Cds或源极电感Ls等进行评价。
场板具有缓和栅极周边的电场的效果。因此，例如，如果由DC特性的夹断特性评价得到的漏极泄漏电流比目标高，则通过延长尺寸FP而缓和电场，能够降低漏极泄漏电流。如果由栅极-源极间耐压或栅极-漏极间耐压评价得到的耐压比目标低，则同样地通过延长尺寸FP而缓和电场，能够使耐压提高。如果由脉冲IV特性评价得到的脉冲IV特性比目标低，则同样地通过延长尺寸FP而缓和电场，能够使脉冲IV特性提高。如果由RF的小信号特性评价得到的电容值比目标小，则能够延长尺寸FP而使电容增大。如果由小信号增益或fk评价得到的值比目标高，则通过延长尺寸FP能够使值降低。
绝缘膜10、11是AlO、TaO、ZnO、SiO、MgO、GaO、TiO、HfO、ZrO、SiN、AlN的任意一者的单层或多层的层叠构造。如果通过ALD(Atomic Layer Deposition)法、p-CVD(ChemicalVapor Deposition)法、热CVD法形成绝缘膜10、11，则绝缘膜10、11的覆盖性变得良好。由于ALD法能够进行原子层级别的膜厚度控制，因此能够以更好的控制性形成目标膜厚度。
图5是表示本发明的实施方式1涉及的半导体装置的制造方法的变形例1的剖视图。T型栅极电极9的栅极头的宽度在源极电极5侧和漏极电极6侧不对称。通过延长栅极头的宽度能够降低栅极电阻Rg。但是，如果通过绝缘膜10、11将栅极头与AlGaN阻挡层4之间完全填埋，则尺寸FP也以将栅极头的宽度延长的量变长，电容成分增加，晶体管特性的改善效果变小。另一方面，在栅极头的下表面的绝缘膜10、11和AlGaN阻挡层4之上的绝缘膜10、11之间存在间隙的情况下，即使延长栅极头的宽度，尺寸FP也不会变长，因此不会使电容成分增加，能够降低栅极电阻Rg。
图6是表示本发明的实施方式1涉及的半导体装置的制造方法的变形例2的剖视图。在AlGaN阻挡层4之上追加了GaN盖层12。也可以对GaN盖层12进行n型掺杂或p型掺杂。
图7是表示本发明的实施方式1涉及的半导体装置的制造方法的变形例3的剖视图。在AlGaN阻挡层4和GaN沟道层3之间追加了AlN间隔层13。
实施方式2.
图8、9是表示本发明的实施方式2涉及的半导体装置的制造方法的剖视图。如图8所示，在形成了绝缘膜10后对晶体管的特性进行评价。接着，在评价结果相对于作为目标的特性产生偏差的情况下，对绝缘膜10进行蚀刻。此时，通过与评价结果对应地对绝缘膜10的蚀刻量进行调整，从而对尺寸FP进行调整，使晶体管的特性接近作为目标的特性。由此，能够得到与实施方式1同样的效果。
优选将绝缘膜10设为AlO/SiO或AlO/SiN等彼此不同的多个层的层叠构造。由此，各个层的相对于干蚀刻的选择比高，因此能够通过特定的膜种类使蚀刻停止，能够进一步调整为与目标相同的膜厚度。另外，通过将各层设为几nm级别例如1～2nm的薄膜，从而能够对蚀刻膜厚度精细地进行调整，因此能够进一步使膜厚度的控制性提高。
实施方式3.
在本实施方式中，在形成绝缘膜10前对晶体管的特性进行评价。不仅对晶体管的特性，还对T型栅极电极9的栅极长度Lg进行测定。由此，还能够对栅极长度Lg比目标长还是短进行判断。在此，通过还加入晶体管的特性的评价结果，能够更准确地对晶体管的特性进行预测。通过与该结果对应地对绝缘膜10的膜种类、膜厚度或介电常数进行调整，从而使尺寸FP、脉冲IV特性、电容值等晶体管的特性接近作为目标的特性。由此，即使没有如实施方式1那样形成绝缘膜11，也能够对晶片间的特性波动进行抑制。
实施方式4.
在形成了绝缘膜10后对晶体管的特性进行了评价时，例如，在电容值比目标低但脉冲IV特性与目标相同的情况下，通过绝缘膜11的膜厚度的调整不能够得到作为目标的特性。例如，在将膜厚度设得厚的情况下，电容值变高，接近作为目标的值，但尺寸FP变得过长，脉冲IV特性大幅度偏离作为目标的值。因此，在本实施方式中，通过与评价结果对应地对绝缘膜11的介电常数进行调整，从而使晶体管的特性接近作为目标的特性。其它结构与实施方式1相同。
由此，能够不变更绝缘膜10、11的膜厚度而仅改变电容值。在上述例子的情况下，通过组成比调整而设为介电常数高的绝缘膜11，由此能够不使膜厚度大幅度增加而仅提高电容值，能够得到作为目标的晶体管特性。例如，在绝缘膜10、11为SiN的情况下，通过提高绝缘膜11的Si组成，从而介电常数变高，因此，即使薄也能够形成高介电常数的SiN膜。
实施方式5.
图10是表示本发明的实施方式5涉及的半导体装置的制造方法的剖视图。在AlGaN阻挡层4之上形成绝缘膜14，在其之上形成T型栅极电极9。其它结构与实施方式1相同。在这样形成MIS栅极构造的情况下，也能够得到与实施方式1同样的效果。
实施方式6.
图11是表示本发明的实施方式6涉及的半导体装置的制造方法的剖视图。在AlGaN阻挡层4形成凹槽15，在凹槽15形成T型栅极电极9。其它结构与实施方式1相同。在这样形成凹槽栅极构造的情况下，也能够得到与实施方式1同样的效果。
实施方式7.
图12是表示本发明的实施方式7涉及的半导体装置的制造方法的剖视图。在AlGaN阻挡层4形成凹槽15，并且形成绝缘膜14后，形成T型栅极电极9。其它结构与实施方式1相同。在这样形成凹槽MIS栅极构造的情况下，也能够得到与实施方式1同样的效果。
实施方式8.
图13是表示本发明的实施方式8涉及的半导体装置的制造方法的剖视图。T型栅极电极9的栅极头的下表面成为台阶状。即使相对于这样的将场板形成为多阶的栅极构造，也能够得到作为目标的晶体管特性。
此外，可以替代AlGaN阻挡层4而使用InAlN层、InGaN层或AlN层，也可以进行n型掺杂或p型掺杂。另外，可以替代GaN沟道层3而使用GaN/AlGaN层、GaN/InGaN层或与肖特基层相比Al组成低的AlGaN层，也可以对各个层进行Fe掺杂或C掺杂。另外，并不限于GaN类晶体管，即使将实施方式1～8的制造方法应用于尺寸FP的影响小且低电压动作的AlGaAs/GaAs构造等GaAs类晶体管，也能够得到同样的效果。
标号的说明
3GaN沟道层(GaN类半导体层)，4AlGaN阻挡层(GaN类半导体层)，5源极电极，6漏极电极，9T型栅极电极，10、11、14绝缘膜，15凹槽

Claims (14)

1.一种半导体装置的制造方法，其特征在于，具备：
在GaN类半导体层之上形成源极电极、漏极电极、T型栅极电极而形成晶体管的工序；
形成覆盖所述T型栅极电极的绝缘膜的工序；
对所述晶体管的特性进行评价的工序；以及
通过与评价结果对应地对所述绝缘膜的膜种类、膜厚度或介电常数进行调整而使所述晶体管的特性接近作为目标的特性的工序，
所述评价是DC特性的评价或者RF的小信号特性评价。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，
在所述T型栅极电极的栅极头的下表面的所述绝缘膜和所述GaN类半导体层的上表面的所述绝缘膜之间存在间隙，
通过与所述评价结果对应地对所述T型栅极电极的根部分的侧面的所述绝缘膜的膜厚度进行调整，从而对在所述T型栅极电极的所述栅极头和所述GaN类半导体层之间形成的场板的尺寸进行调整，使所述晶体管的特性接近所述作为目标的特性。
3.根据权利要求2所述的半导体装置的制造方法，其特征在于，
所述绝缘膜具有第1及第2绝缘膜，
在形成了所述第1绝缘膜后对所述晶体管的特性进行评价，
在所述评价结果相对于所述作为目标的特性产生了偏差的情况下，在所述第1绝缘膜之上形成所述第2绝缘膜，
通过与所述评价结果对应地对所述第2绝缘膜的膜厚度进行调整，从而使所述晶体管的特性接近所述作为目标的特性。
4.根据权利要求2所述的半导体装置的制造方法，其特征在于，
在形成了所述绝缘膜后对所述晶体管的特性进行评价，
在所述评价结果相对于所述作为目标的特性产生了偏差的情况下，对所述绝缘膜进行蚀刻，
通过与所述评价结果对应地对所述绝缘膜的蚀刻量进行调整，从而使所述晶体管的特性接近所述作为目标的特性。
5.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
在形成所述绝缘膜前对所述晶体管的特性进行评价。
6.根据权利要求1所述的半导体装置的制造方法，其特征在于，
所述绝缘膜具有第1及第2绝缘膜，
在形成了所述第1绝缘膜后对所述晶体管的特性进行评价，
在所述评价结果相对于所述作为目标的特性产生了偏差的情况下，在所述第1绝缘膜之上形成所述第2绝缘膜，
通过与所述评价结果对应地对所述第2绝缘膜的介电常数进行调整，从而使所述晶体管的特性接近所述作为目标的特性。
7.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
还具备在所述GaN类半导体层之上形成第3绝缘膜的工序，
在所述第3绝缘膜之上形成所述T型栅极电极。
8.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
还具备在所述GaN类半导体层形成凹槽的工序，
在所述凹槽形成所述T型栅极电极。
9.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
所述T型栅极电极的栅极头的下表面呈台阶状。
10.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
所述T型栅极电极的栅极头尺寸在所述源极电极侧和所述漏极电极侧不对称。
11.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
通过ALD法、p-CVD法、热CVD法形成所述绝缘膜。
12.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
所述绝缘膜是AlO、TaO、ZnO、SiO、MgO、GaO、TiO、HfO、ZrO、SiN、AlN的任意一者的单层或多层的层叠构造。
13.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
作为所述晶体管的特性的评价，对夹断特性、栅极-源极间耐压、栅极-漏极间耐压或脉冲IV特性进行评价。
14.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
作为所述晶体管的特性的评价，对小信号增益、互导、栅极-源极间电容、栅极-漏极间电容、漏极-源极间电容或源极电感进行评价。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040038525A1 (en) * 2002-08-26 2004-02-26 Shuang Meng Enhanced atomic layer deposition
US20130277680A1 (en) * 2012-04-23 2013-10-24 Bruce M. Green High Speed Gallium Nitride Transistor Devices
US20140284661A1 (en) * 2013-03-25 2014-09-25 Raytheon Company Monolithic integrated circuit (mmic) structure and method for forming such structure
CN106531791A (zh) * 2015-09-15 2017-03-22 三菱电机株式会社 半导体装置及其制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0815159B2 (ja) 1986-09-22 1996-02-14 株式会社日立製作所 半導体装置の製造方法
JPH04230041A (ja) 1990-12-27 1992-08-19 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH0883813A (ja) * 1994-09-09 1996-03-26 Mitsubishi Electric Corp 高周波半導体装置，及びその製造方法
JP3642146B2 (ja) 1997-03-24 2005-04-27 株式会社神戸製鋼所 半導体装置の評価方法
US6060402A (en) * 1998-07-23 2000-05-09 The Whitaker Corporation Process for selective recess etching of epitaxial field effect transistors with a novel etch-stop layer
JP4437611B2 (ja) * 2000-11-16 2010-03-24 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4620333B2 (ja) * 2003-05-09 2011-01-26 三菱電機株式会社 半導体装置の製造方法
WO2007040160A1 (ja) * 2005-09-30 2007-04-12 Nec Corporation 電界効果トランジスタ
US7795642B2 (en) * 2007-09-14 2010-09-14 Transphorm, Inc. III-nitride devices with recessed gates
JP2009081177A (ja) * 2007-09-25 2009-04-16 Nec Electronics Corp 電界効果トランジスタ、半導体チップ及び半導体装置
JP5186661B2 (ja) * 2007-09-28 2013-04-17 富士通株式会社 化合物半導体装置
JP5499441B2 (ja) 2008-04-01 2014-05-21 沖電気工業株式会社 半導体装置及びその製造方法
JP5660280B2 (ja) * 2010-03-27 2015-01-28 日本電気株式会社 電界効果トランジスタ、電界効果トランジスタの製造方法、および電子装置
JP2012094726A (ja) 2010-10-28 2012-05-17 Fujitsu Ltd 電界効果トランジスタ及びその製造方法
JP2013149914A (ja) * 2012-01-23 2013-08-01 Mitsubishi Electric Corp 光電気化学装置および半導体装置の製造方法
JP2014003222A (ja) * 2012-06-20 2014-01-09 Toshiba Corp 電界効果トランジスタ
US10825924B2 (en) * 2012-06-26 2020-11-03 Nxp Usa, Inc. Semiconductor device with selectively etched surface passivation
US9425267B2 (en) * 2013-03-14 2016-08-23 Freescale Semiconductor, Inc. Transistor with charge enhanced field plate structure and method
KR101736270B1 (ko) * 2014-02-14 2017-05-17 한국전자통신연구원 안정화된 게이트 구조를 갖는 반도체 소자 및 그의 제조 방법
US11038023B2 (en) * 2018-07-19 2021-06-15 Macom Technology Solutions Holdings, Inc. III-nitride material semiconductor structures on conductive silicon substrates

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040038525A1 (en) * 2002-08-26 2004-02-26 Shuang Meng Enhanced atomic layer deposition
US20130277680A1 (en) * 2012-04-23 2013-10-24 Bruce M. Green High Speed Gallium Nitride Transistor Devices
US20140284661A1 (en) * 2013-03-25 2014-09-25 Raytheon Company Monolithic integrated circuit (mmic) structure and method for forming such structure
CN106531791A (zh) * 2015-09-15 2017-03-22 三菱电机株式会社 半导体装置及其制造方法

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