CN110546743B - 蚀刻方法 - Google Patents
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- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 36
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- 239000007789 gas Substances 0.000 claims description 30
- AZSZCFSOHXEJQE-UHFFFAOYSA-N dibromodifluoromethane Chemical compound FC(F)(Br)Br AZSZCFSOHXEJQE-UHFFFAOYSA-N 0.000 claims description 8
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Abstract
提供一种能够将硅氮化物层的蚀刻速度和硅氧化物层的蚀刻速度控制为相同程度的蚀刻方法。将具备具有层叠了的硅氧化物层(2)和硅氮化物层(3)的层叠膜(5)的被处理体，通过含有由碳、溴和氟构成的卤化碳化合物的蚀刻气体进行处理。硅氧化物层(2)和硅氮化物层(3)以相同程度的蚀刻速度被蚀刻。
Description
技术领域
本发明涉及蚀刻方法。
背景技术
在半导体的制造工序中，包括将抗蚀剂、有机膜、碳膜作为掩模，利用蚀刻气体对具有层叠了的硅氧化物层和硅氮化物层的层叠膜进行蚀刻的工序。例如专利文献1公开了使用由1,3,3,3-四氟丙烯、添加气体和惰性气体构成的蚀刻气体蚀刻上述层叠膜的方法。但是Si-N键比Si-O键的键合能弱，所以硅氮化物层的蚀刻速度比硅氧化物层的蚀刻速度快1.2倍左右。
因此，在对上述层叠膜实施形成长宽比大于20这样的高长宽比的贯通孔的深挖蚀刻的情况下，与硅氧化物层在厚度方向上被蚀刻的速度相比，硅氮化物层在与厚度方向正交的面方向上被蚀刻的速度更快，所以硅氮化物层在面方向上被过度蚀刻，有可能产生蚀刻形状的异常。
在先技术文献
专利文献1：日本特许公开公报2012年第114402号
发明内容
本发明的课题是提供一种能够将硅氮化物层的蚀刻速度和硅氧化物层的蚀刻速度控制为相同程度的蚀刻方法。
为解决所述课题，本发明的一技术方案如以下的[1]～[4]所述。
[1]一种蚀刻方法，具备蚀刻工序，在所述蚀刻工序中，将具备具有层叠了的硅氧化物层和硅氮化物层的层叠膜的被处理体，通过含有由碳、溴和氟构成的卤化碳化合物的蚀刻气体进行处理，将所述硅氧化物层和所述硅氮化物层这两者蚀刻。
[2]根据[1]记载的蚀刻方法，所述卤化碳化合物是二溴二氟甲烷和溴五氟乙烷中的至少一者。
[3]根据[1]或[2]记载的蚀刻方法，所述蚀刻气体还含有惰性气体。
[4]根据[1]～[3]的任一项记载的蚀刻方法，在所述蚀刻工序中，使用将所述蚀刻气体等离子化而得到的等离子气体进行蚀刻。
根据本发明的蚀刻方法，将具备具有层叠了的硅氧化物层和硅氮化物层的层叠膜的被处理体进行蚀刻，能够将硅氮化物层的蚀刻速度和硅氧化物层的蚀刻速度控制为相同程度。
附图说明
图1是用于说明本发明的一实施方式涉及的蚀刻方法的被处理体的截面图。
图2是表示ICP电力与蚀刻速度之间的关系的图表。
具体实施方式
以下，对本发明的一实施方式进行说明。再者，本实施方式表示本发明的一例，本发明并不限定于本实施方式。另外，可以对本实施方式添加各种变更或改良，添加了变更和改良的实施方式也包含在本发明内。
本实施方式的蚀刻方法，具备蚀刻工序，在蚀刻工序中，将具备具有层叠了的硅氧化物层(SiOx层)和硅氮化物层的层叠膜的被处理体，通过含有由碳、溴和氟构成的卤化碳化合物的蚀刻气体进行处理，将硅氧化物层和硅氮化物层这两者蚀刻。
采用本实施方式的蚀刻方法，将具备具有层叠了的硅氧化物层和硅氮化物层的层叠膜的被处理体进行蚀刻，根据蚀刻条件等，能够将硅氮化物层的蚀刻速度相对于硅氧化物层的蚀刻速度之比([硅氮化物层的蚀刻速度]/[硅氧化物层的蚀刻速度])在0.8以上且小于1.5之间任意控制。由此，采用本实施方式的蚀刻方法，能够将硅氮化物层的蚀刻速度和硅氧化物层的蚀刻速度控制为相同程度，硅氮化物层的蚀刻速度相对于硅氧化物层的蚀刻速度之比优选为0.9以上且小于1.2。
对于由碳、溴和氟构成的卤化碳化合物的种类没有特别限定，可以使用二溴二氟甲烷(CBr2F2)和溴五氟乙烷(C2BrF5)中的至少一者。
蚀刻气体可以含有卤化碳化合物和惰性气体。通过在使惰性气体共存的状态下进行蚀刻，能够对于掩模具有选择性地并且以高的蚀刻速度蚀刻硅氧化物层和硅氮化物层。对于惰性气体的种类没有特别限定，可举出氦气(He)、氩气(Ar)、氖气(Ne)、氪气(Kr)、氙气(Xe)、氮气(N2)。这些惰性气体可以单独使用一种，也可以并用两种以上。
另外，对于在蚀刻工序中所采用的蚀刻方法没有特别限定，可以采用使用将蚀刻气体等离子化而得到的等离子气体进行蚀刻的等离子蚀刻法。
蚀刻所使用的等离子体有等离子容性耦合等离子体(CCP：Capacitively CoupledPlasma)、电子回旋共振等离子体(ECP：Electron Cyclotron resonance Plasma)、螺旋波激发等离子体(HWP：Helicon Wave Plasma)、电感耦合等离子体(ICP：InductivelyCoupled Plasma)、微波激发表面波等离子体(SWP：Surface Wave Plasma)等。
这样的本实施方式的蚀刻方法，例如能够在作为三维NAND型闪存的制造过程中的一工序的、对于硅氮化物层和硅氧化物层在基板上交替层叠多个而成的层叠膜形成沿厚度方向延伸的贯通孔的工序中使用。
参照图1，对采用本实施方式的蚀刻方法将具备具有层叠了的硅氧化物层和硅氮化物层的层叠膜的被处理体蚀刻、在层叠膜形成贯通孔的方法的一例进行说明。
图1是在层叠膜5形成有贯通孔9的被处理体的截面图，该被处理体是通过硅氮化物层3和硅氧化物层2交替层叠多个(图1的例子中各为3层)而成的层叠膜5设置在半导体基板1上而构成的。再者，在半导体基板1的紧上方层叠有层叠膜5的硅氧化物层2。
在层叠膜5的最上层的硅氮化物层3上，被覆有形成图案的掩模7，采用本实施方式的蚀刻方法进行蚀刻，从掩模7露出的层叠膜5被蚀刻而形成贯通孔9。
本实施方式的蚀刻方法，能够将硅氮化物层3的蚀刻速度和硅氧化物层2的蚀刻速度控制为相同程度，因此在层叠膜5形成贯通孔9时，能够抑制在贯通孔9的内表面露出的硅氮化物层3在面方向(与厚度方向正交的方向)上被过度蚀刻。由此，即使在对层叠膜5实施形成长宽比大于20的高长宽比的贯通孔9的深挖蚀刻的情况下，如图1所示，也能够形成贯通孔9并且不发生层叠膜5的层叠结构的崩坏、蚀刻形状异常。
以下示出各种试验例，对本发明进行更详细的说明。
〔试验例1〕
采用等离子化学气相沉积法在Si基板上形成硅氮化物层，得到试验片。硅氮化物层的膜厚为500nm。对该试验片实施电感耦合等离子蚀刻(ICP蚀刻)，将硅氮化物层蚀刻。蚀刻条件如下所述。
蚀刻装置：samco有限公司制作的ICP蚀刻装置RIE-200iP
蚀刻时间：120秒
ICP电力：200W、500W或800W
偏压电力：200W
压力：2Pa
蚀刻气体：1体积份二溴二氟甲烷和9体积份氩气的混合气体
蚀刻气体的流量：100SCCM
当蚀刻结束时，使用日本分光有限公司制作的椭圆偏振仪M-550测定硅氮化物层的膜厚。然后，通过蚀刻前后的膜厚之差除以蚀刻时间，算出硅氮化物层的蚀刻速度。
〔试验例2〕
除了代替硅氮化物层，在Si基板上形成膜厚2000nm的硅氧化物层而得到试验片这一点以外，与试验例1同样地算出硅氧化物层的蚀刻速度。
〔试验例3〕
除了将蚀刻气体中的卤化碳化合物的种类从二溴二氟甲烷替换为四氟化碳(CF4)这一点以外，与试验例1同样地算出硅氮化物层的蚀刻速度。
〔试验例4〕
除了将蚀刻气体中的卤化碳化合物的种类从二溴二氟甲烷替换为四氟化碳(CF4)以外，与试验例2同样地算出硅氧化物层的蚀刻速度。
〔试验例5〕
除了将蚀刻气体替换为1体积份四氟化碳、8体积份氩气和1体积份氧气的混合气体这一点以外，与试验例3同样地算出硅氮化物层的蚀刻速度。
〔试验例6〕
除了将蚀刻气体替换为1体积份四氟化碳、8体积份氩气和1体积份氧气的混合气体这一点以外，与试验例4同样地算出硅氧化物层的蚀刻速度。
表1
将各试验例的结果示于表1和图2的图表中。表1中的“比”是指硅氮化物层的蚀刻速度相对于硅氧化物层的蚀刻速度之比([硅氮化物层的蚀刻速度]/[硅氧化物层的蚀刻速度])。由表1和图2的图表可知，在蚀刻气体中的卤化碳化合物的种类为四氟化碳的情况下，硅氮化物层的蚀刻速度比硅氧化物层的蚀刻速度快。与此相对，在蚀刻气体中的卤化碳化合物的种类为二溴二氟甲烷的情况下，硅氧化物层的蚀刻速度和硅氮化物层的蚀刻速度大致相同(参照表1的“比”一栏)。
通过使用四氟化碳、氩气和氧气的混合气体作为蚀刻气体，能够使硅氮化物层的蚀刻速度降低。但是，存在具有层叠了的硅氧化物层和硅氮化物层的层叠膜整体的蚀刻速度大大降低这样的问题。另外，如果混合氧气，则在图案基板的蚀刻中，光刻胶等掩模容易被蚀刻。
如果使用二溴二氟甲烷，则能够不使层叠膜整体的蚀刻速度降低，并且能够将硅氧化物层的蚀刻速度和硅氮化物层的蚀刻速度控制为大致相同程度。
附图标记说明
1 半导体基板
2 硅氧化物层
3 硅氮化物层
5 层叠膜
7 掩模
9 贯通孔。
Claims (2)
1.一种蚀刻方法，具备蚀刻工序，
在所述蚀刻工序中，将具备具有层叠了的硅氧化物层和硅氮化物层的层叠膜的被处理体，通过含有由碳、溴和氟构成的卤化碳化合物的蚀刻气体进行处理，将所述硅氧化物层和所述硅氮化物层这两者蚀刻，
所述卤化碳化合物是二溴二氟甲烷，
在所述蚀刻工序中，使用将所述蚀刻气体等离子化而得到的等离子气体进行蚀刻，
将所述硅氮化物层的蚀刻速度相对于所述硅氧化物层的蚀刻速度之比设为0.8以上且小于1.5。
2.根据权利要求1所述的蚀刻方法，
所述蚀刻气体还含有惰性气体。
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4374698A (en) * | 1980-07-11 | 1983-02-22 | U.S. Philips Corporation | Method of manufacturing a semiconductor device |
| US5302236A (en) * | 1990-10-19 | 1994-04-12 | Tokyo Electron Limited | Method of etching object to be processed including oxide or nitride portion |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US114402A (en) | 1871-05-02 | Improvement in shaft-couplings | ||
| JPS55138834A (en) | 1979-04-16 | 1980-10-30 | Nippon Telegr & Teleph Corp <Ntt> | Dry etching method |
| NL8204437A (nl) | 1982-11-16 | 1984-06-18 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met behulp van plasma-etsen. |
| JPH03208367A (ja) | 1990-01-10 | 1991-09-11 | Fujitsu Ltd | 半導体装置の製造方法 |
| US5279705A (en) | 1990-11-28 | 1994-01-18 | Dainippon Screen Mfg. Co., Ltd. | Gaseous process for selectively removing silicon nitride film |
| JP3160961B2 (ja) * | 1991-10-02 | 2001-04-25 | ソニー株式会社 | ドライエッチング方法 |
| DE4232475C2 (de) | 1992-09-28 | 1998-07-02 | Siemens Ag | Verfahren zum plasmachemischen Trockenätzen von Si¶3¶N¶4¶-Schichten hochselektiv zu SiO¶2¶-Schichten |
| JPH06204192A (ja) * | 1992-12-28 | 1994-07-22 | Toshiba Corp | シリコン窒化膜のエッチング方法 |
| KR100243893B1 (ko) | 1993-09-30 | 2000-03-02 | 다나까 도미오 | 기어펌프 |
| JP2000208488A (ja) | 1999-01-12 | 2000-07-28 | Kawasaki Steel Corp | エッチング方法 |
| US6660643B1 (en) | 1999-03-03 | 2003-12-09 | Rwe Schott Solar, Inc. | Etching of semiconductor wafer edges |
| TW527763B (en) | 2000-05-01 | 2003-04-11 | Koninkl Philips Electronics Nv | Power adaptive frequency divider |
| JP4761502B2 (ja) | 2004-10-07 | 2011-08-31 | 株式会社アルバック | 層間絶縁膜のドライエッチング方法 |
| WO2007116515A1 (ja) | 2006-04-07 | 2007-10-18 | Philtech Inc. | 半導体装置及びその製造方法、ドライエッチング方法、並びに配線材料の作製方法 |
| US8125069B2 (en) | 2006-04-07 | 2012-02-28 | Philtech Inc. | Semiconductor device and etching apparatus |
| TW200842971A (en) | 2007-04-18 | 2008-11-01 | Philtech Inc | Semiconductor device, its manufacturing method, dry etching method, method for manufacturing wiring material and dry etching device |
| JP5434970B2 (ja) | 2010-07-12 | 2014-03-05 | セントラル硝子株式会社 | ドライエッチング剤 |
| KR102333443B1 (ko) * | 2014-10-24 | 2021-12-02 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| JP6327295B2 (ja) * | 2015-08-12 | 2018-05-23 | セントラル硝子株式会社 | ドライエッチング方法 |
| CN109564868B (zh) | 2016-08-25 | 2023-04-04 | 日本瑞翁株式会社 | 等离子体蚀刻方法 |
-
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4374698A (en) * | 1980-07-11 | 1983-02-22 | U.S. Philips Corporation | Method of manufacturing a semiconductor device |
| US5302236A (en) * | 1990-10-19 | 1994-04-12 | Tokyo Electron Limited | Method of etching object to be processed including oxide or nitride portion |
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