CN110010187B - 半导体存储器装置及其操作方法 - Google Patents

半导体存储器装置及其操作方法 Download PDF

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Publication number
CN110010187B
CN110010187B CN201811409219.1A CN201811409219A CN110010187B CN 110010187 B CN110010187 B CN 110010187B CN 201811409219 A CN201811409219 A CN 201811409219A CN 110010187 B CN110010187 B CN 110010187B
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normal
address
memory device
semiconductor memory
target
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CN110010187A (zh
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金经纶
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/76Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/806Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by reducing size of decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
CN201811409219.1A 2017-11-24 2018-11-23 半导体存储器装置及其操作方法 Active CN110010187B (zh)

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KR10-2017-0158829 2017-11-24
KR1020170158829A KR20190060527A (ko) 2017-11-24 2017-11-24 반도체 메모리 장치 및 그 동작 방법

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CN110010187B true CN110010187B (zh) 2024-09-17

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US (1) US10692582B2 (https=)
JP (1) JP7271139B2 (https=)
KR (1) KR20190060527A (https=)
CN (1) CN110010187B (https=)
DE (1) DE102018122491A1 (https=)

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US20190164621A1 (en) 2019-05-30
CN110010187A (zh) 2019-07-12
JP7271139B2 (ja) 2023-05-11
US10692582B2 (en) 2020-06-23
JP2019096376A (ja) 2019-06-20
DE102018122491A1 (de) 2019-05-29
KR20190060527A (ko) 2019-06-03

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