CN109983574B - 功率半导体模块的制造 - Google Patents
功率半导体模块的制造 Download PDFInfo
- Publication number
- CN109983574B CN109983574B CN201780072618.0A CN201780072618A CN109983574B CN 109983574 B CN109983574 B CN 109983574B CN 201780072618 A CN201780072618 A CN 201780072618A CN 109983574 B CN109983574 B CN 109983574B
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- Prior art keywords
- leadframe
- lead frame
- power semiconductor
- interlocking
- mold
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000000465 moulding Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 24
- 239000012778 molding material Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 230000000903 blocking effect Effects 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 6
- 238000007789 sealing Methods 0.000 description 17
- 239000010410 layer Substances 0.000 description 11
- 239000010949 copper Substances 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000013536 elastomeric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP16200329 | 2016-11-23 | ||
EP16200329.7 | 2016-11-23 | ||
PCT/EP2017/080248 WO2018096050A1 (en) | 2016-11-23 | 2017-11-23 | Manufacturing of a power semiconductor module |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109983574A CN109983574A (zh) | 2019-07-05 |
CN109983574B true CN109983574B (zh) | 2023-05-12 |
Family
ID=57394431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780072618.0A Active CN109983574B (zh) | 2016-11-23 | 2017-11-23 | 功率半导体模块的制造 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11189556B2 (zh) |
EP (1) | EP3545550B1 (zh) |
JP (1) | JP7162001B2 (zh) |
CN (1) | CN109983574B (zh) |
WO (1) | WO2018096050A1 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130175704A1 (en) * | 2012-01-05 | 2013-07-11 | Ixys Corporation | Discrete power transistor package having solderless dbc to leadframe attach |
JP2022529965A (ja) | 2019-04-18 | 2022-06-27 | ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト | レーザ溶接のリードフレームを備えた電力半導体モジュール |
KR102348395B1 (ko) * | 2020-06-27 | 2022-01-10 | 김기중 | 복수의 단자를 포함하는 케이블 커넥터 |
EP4040471A1 (en) * | 2021-02-08 | 2022-08-10 | Hitachi Energy Switzerland AG | Power semiconductor module, power semiconductor device and method for producing a power semiconductor device |
US11404392B1 (en) * | 2021-03-03 | 2022-08-02 | Infineon Technologies Ag | Molded semiconductor module for PCB embedding |
Citations (4)
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US5767573A (en) * | 1995-10-26 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US5792676A (en) * | 1995-10-03 | 1998-08-11 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating power semiconductor device and lead frame |
CN102074540A (zh) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | 矩阵式dip引线框架、该框架的ic封装件及其生产方法 |
CN103946976A (zh) * | 2011-11-18 | 2014-07-23 | 德州仪器公司 | 具有翻转式球接合表面的双层级引线框架及装置封装 |
Family Cites Families (27)
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JP3088193B2 (ja) * | 1992-06-05 | 2000-09-18 | 三菱電機株式会社 | Loc構造を有する半導体装置の製造方法並びにこれに使用するリードフレーム |
US5339518A (en) * | 1993-07-06 | 1994-08-23 | Motorola, Inc. | Method for making a quad leadframe for a semiconductor device |
US6072228A (en) * | 1996-10-25 | 2000-06-06 | Micron Technology, Inc. | Multi-part lead frame with dissimilar materials and method of manufacturing |
JP3833464B2 (ja) | 2000-11-01 | 2006-10-11 | 株式会社三井ハイテック | リードフレーム |
AU2003242873A1 (en) * | 2002-06-06 | 2003-12-22 | Koninklijke Philips Electronics N.V. | Quad flat non-leaded package comprising a semiconductor device |
US6713317B2 (en) * | 2002-08-12 | 2004-03-30 | Semiconductor Components Industries, L.L.C. | Semiconductor device and laminated leadframe package |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US8252615B2 (en) * | 2006-12-22 | 2012-08-28 | Stats Chippac Ltd. | Integrated circuit package system employing mold flash prevention technology |
US8354740B2 (en) * | 2008-12-01 | 2013-01-15 | Alpha & Omega Semiconductor, Inc. | Top-side cooled semiconductor package with stacked interconnection plates and method |
DE102010002945A1 (de) | 2010-03-17 | 2011-09-22 | Robert Bosch Gmbh | Schaltungsanordnung und zugehöriges steuergerät für ein kraftfahrzeug |
US8513784B2 (en) * | 2010-03-18 | 2013-08-20 | Alpha & Omega Semiconductor Incorporated | Multi-layer lead frame package and method of fabrication |
JP2012114238A (ja) * | 2010-11-25 | 2012-06-14 | Panasonic Corp | 電子部品用リードフレームとその製造方法 |
JP5649142B2 (ja) * | 2011-04-05 | 2015-01-07 | パナソニック株式会社 | 封止型半導体装置及びその製造方法 |
CN103339722B (zh) * | 2011-11-21 | 2016-04-06 | 松下知识产权经营株式会社 | 电气零件用树脂、半导体装置及配线基板 |
JP2013258387A (ja) * | 2012-05-15 | 2013-12-26 | Rohm Co Ltd | パワーモジュール半導体装置 |
JP5889753B2 (ja) | 2012-08-31 | 2016-03-22 | 新電元工業株式会社 | リードフレーム及び樹脂封止型半導体装置の製造方法 |
US8698288B1 (en) * | 2013-05-23 | 2014-04-15 | Freescale Semiconductor, Inc. | Flexible substrate with crimping interconnection |
US20150060123A1 (en) * | 2013-09-04 | 2015-03-05 | Texas Instruments Incorporated | Locking dual leadframe for flip chip on leadframe packages |
CN104838494B (zh) * | 2013-12-05 | 2017-06-23 | 新电元工业株式会社 | 引线框架、模具、附带贴装元件的引线框架的制造方法 |
WO2016080519A1 (ja) * | 2014-11-20 | 2016-05-26 | 日本精工株式会社 | 電子部品搭載用放熱基板 |
US20170103904A1 (en) * | 2015-10-12 | 2017-04-13 | Texas Instruments Incorporated | Integrated circuit package mold assembly |
US10312184B2 (en) * | 2015-11-04 | 2019-06-04 | Texas Instruments Incorporated | Semiconductor systems having premolded dual leadframes |
US9917039B2 (en) * | 2016-04-20 | 2018-03-13 | Amkor Technology, Inc. | Method of forming a semiconductor package with conductive interconnect frame and structure |
DE102016112289B4 (de) * | 2016-07-05 | 2020-07-30 | Danfoss Silicon Power Gmbh | Leiterrahmen und Verfahren zur Herstellung desselben |
DE102017207564A1 (de) * | 2017-05-05 | 2018-11-08 | Robert Bosch Gmbh | Halbleitermodul |
US20190181076A1 (en) * | 2017-12-07 | 2019-06-13 | Stmicroelectronics S.R.L. | Method of manufacturing leadframes of semiconductor devices,corresponding leadframe and semiconductor device |
US10546805B2 (en) * | 2017-12-29 | 2020-01-28 | Texas Instruments Incorporated | Integrated circuit package with conductive clips |
-
2017
- 2017-11-23 CN CN201780072618.0A patent/CN109983574B/zh active Active
- 2017-11-23 EP EP17801058.3A patent/EP3545550B1/en active Active
- 2017-11-23 JP JP2019547784A patent/JP7162001B2/ja active Active
- 2017-11-23 WO PCT/EP2017/080248 patent/WO2018096050A1/en unknown
-
2019
- 2019-05-22 US US16/419,668 patent/US11189556B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5792676A (en) * | 1995-10-03 | 1998-08-11 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating power semiconductor device and lead frame |
US5767573A (en) * | 1995-10-26 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
CN102074540A (zh) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | 矩阵式dip引线框架、该框架的ic封装件及其生产方法 |
CN103946976A (zh) * | 2011-11-18 | 2014-07-23 | 德州仪器公司 | 具有翻转式球接合表面的双层级引线框架及装置封装 |
Also Published As
Publication number | Publication date |
---|---|
JP7162001B2 (ja) | 2022-10-27 |
US20190273040A1 (en) | 2019-09-05 |
JP2020501380A (ja) | 2020-01-16 |
EP3545550A1 (en) | 2019-10-02 |
US11189556B2 (en) | 2021-11-30 |
CN109983574A (zh) | 2019-07-05 |
EP3545550B1 (en) | 2021-02-17 |
WO2018096050A1 (en) | 2018-05-31 |
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Effective date of registration: 20200921 Address after: Baden, Switzerland Applicant after: ABB grid Switzerland AG Applicant after: AUDI AG Address before: Baden, Switzerland Applicant before: ABB Switzerland Co.,Ltd. Applicant before: AUDI AG |
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