WO2005122250A2 - High power mcm package with improved planarity and heat dissipation - Google Patents

High power mcm package with improved planarity and heat dissipation Download PDF

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Publication number
WO2005122250A2
WO2005122250A2 PCT/US2005/019515 US2005019515W WO2005122250A2 WO 2005122250 A2 WO2005122250 A2 WO 2005122250A2 US 2005019515 W US2005019515 W US 2005019515W WO 2005122250 A2 WO2005122250 A2 WO 2005122250A2
Authority
WO
WIPO (PCT)
Prior art keywords
component
module
recess
circuit substrate
mcm
Prior art date
Application number
PCT/US2005/019515
Other languages
French (fr)
Other versions
WO2005122250A3 (en
WO2005122250B1 (en
Inventor
Christopher P. Schaffer
Original Assignee
International Rectifier Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/620,029 external-priority patent/US6946740B2/en
Application filed by International Rectifier Corporation filed Critical International Rectifier Corporation
Priority to JP2007515599A priority Critical patent/JP2008502158A/en
Publication of WO2005122250A2 publication Critical patent/WO2005122250A2/en
Publication of WO2005122250A3 publication Critical patent/WO2005122250A3/en
Publication of WO2005122250B1 publication Critical patent/WO2005122250B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and a manufacturing method providing improved coplanarity accommodation and heat dissipation in a multi-chip module. One of the components in a multi-chip module (MCM) is provided with a recess formed in its respective top surface; and a film is applied so as to cover the top surfaces of the components and so that any excess film can enter into the recess. The recess is preferably a peripheral groove. Then when molding material is injected, it may surround and seal the side surfaces of the components, while not substantially covering the top surfaces that are covered by the film. Since the recess receives any excess film material that may be present, it may prevent such excess film material from covering the respective side surfaces of the corresponding component and creating a void between the component and the molding material. This advantageous effect of the invention is particularly useful when the top component surface in which the recess is formed is higher above the circuit substrate than the respective top surface of another one of the components.

Description

HIGH POWER MCM PACKAGE WITH IMPROVED P ANARITY AND HEAT DISSIPATION
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation-in-part of U.S . Serial No. 10/620,029 filed July 14, 2003 (IR-2241). It is based upon and claims priority of U.S. Serial No. 60/576,766 filed June 3, 2004 (IR-2790 PROV) and Serial No. 60/583,104 filed June 25, 2004 (IR-2561 PROV). The disclosures of the foregoing applications are incorporated by reference.
BACKGROUND OF THE INVENTION
Field of the Invention
[0002] The present invention relates to multi-chip modules and more particularly to a structure providing improved coplanarity accommodation and heat dissipation in a multi-chip module.
Background Art
[0003] Serial No. 10/620,029 (IR-2241) and Serial No. 60/576,766 (IR-2790 PROV) disclose several embodiments of a multi-chip module (MCM), including a conductive element which serves as an electrical connector for electrically connecting respective electrical contacts on at least two power semiconductor devices. In addition to serving as an input or output connector, the conductive element improves heat transfer from the power semiconductor devices through the top of the module. This type of MCM is referred to commercially as a T-PAC™ module by its manufacturer, the International Rectifier Corporation. [0004] One of those embodiments is the T-PAC module 54 shown in Figure 1. A conductive element 56 bridges over and electrically connects respective contacts on a conventional MOSFET 30 and a flip-chip MOSFET 42 with its web portion 60. The conductive element 56 may be made of copper or another heat- conductive metal such as Au, Ag, Sn, Ti, brass, Ni or Al. A connector 64 connects the web portion 60 to a printed circuit board 40. The connector 64 may optionally be disposed between the two MOSFETS 30, 42 rather than in the position shown.
[0005] In more detail, a top surface of the web portion 60 of the conductive element 56 is exposed to the exterior of the T-PAC module 54, which improves heat dissipation from the MOSFETs 30, 42 through the top of the module. The above components are placed in a mold and resin is injected, forming a molded housing 58, disposed around and between the conductive element 56, its connector 64, the conventional MOSFET 30, and the flip-chip MOSFET 42. The resin is not, however, molded over the top of the conductive element 56. [0006] A typical layout of an MCM (multi-chip module) 55 is shown in plan view in Figure 2. In this example, the MCM 55 contains only the one T-PAC module 54. As shown, additional components CI, C2, C3 and C4 may be disposed on the circuit board along with the T-PAC module 54 and within the molding 58. Additional layouts are shown in Serial No. 60/576,766 (IR-2790 PROV).
[0007] A problem in this technology is that the components within an MCM module, which may include one or more T-PAC module(s), may differ in height. The presence of a tall T-PAC module in the mold may cause resin to flow in the mold over the top of a shorter T-PAC module, which is undesirable since the tops of the T-PAC modules should remain exposed.
[0008] Figure 3 is a schematic cross-sectional view of the MCM 55 in Fig. 2 as seen during an intermediate manufacturing step. A T-PAC module 54 containing components such as switching components, passive components or MOSFETs as seen for example in Figure 1 is disposed at the center of the printed circuit board 40, while other components CI and C4 are disposed on other portions of the printed circuit board 40.
[0009] A lead frame or another type of substrate may be substituted for the printed circuit board 40.
[0010] Before forming the molding 58, a compliant plastic film 70 is applied over the tops of the module 54, the component CI and the component C4, thus sealing off the tops of the components while compensating for the height differences between the respective components. The film 70 prevents mold compound from flowing over the top of any component. The film may be any high temperature plastic film, such as Kapton. The resin molding material 58 is applied thereafter, after which the film 70 is removed.
[0011] Figs. 4, 5 and 6 show the molding process. In this example, three T- PAC modules 54, 54a, 54b are disposed on the board 40. The film 70 is pressed onto the assembly of the modules and the board by tools 62, 64, and more particularly by a spring-loaded plate 66 on the tool 62, while the plastic molding compound is injected around the modules.
[0012] This molding arrangement successfully prevents mold compound from flowing over the tops of the components. However, it has been found that if the top surface of the conductive element 56 of a T-PAC 54 is excessively high above the printed circuit board 40, excess film material may spill over and form protrusions 57 at the sides of the conductive element, as shown in Figure 3. Then, when the molding material 58 is added, these protrusions may prevent the resin material from reaching the conductive element, forming a void between the material and the conductive element which reduces the structural integrity and strength of the MCM and its resistance to environmental hazards.
SUMMARY OF THE INVENTION [0013] To address the foregoing problem, a groove or "moat" may be formed in the top surface of the conductive element in a T-PAC module. When the film is applied, if there is any excess film material, for example due to the height of the conductive element, the excess material will be taken up by the groove so that it will not spill over the sides of the conductive element and interfere with the subsequent application of the resin mold.
[0014] According to one aspect of the invention, a semiconductor module may comprise a circuit substrate; a semiconductor device and an additional component, each having respective upper and lower electrodes, the lower electrodes being disposed in electrical contact with the circuit substrate; a conductive element being electrically connected to the circuit substrate and having a web portion that bridges over and contacts the respective upper electrodes of both said semiconductor device and the additional component; the web portion having an upward-facing web surface, and a recess being formed in the web surface. The recess advantageously comprises a groove formed in a peripheral region of the web surface.
[0015] According to another aspect of the invention, a multi-chip module may have a circuit substrate; a semiconductor module disposed on the circuit substrate; another component disposed on the circuit substrate; and molded material surrounding and sealing both the semiconductor module and the other component. The other component may be a semiconductor device, a passive component, or another semiconductor module, for example.
[0016] The invention is particularly advantageous when the upward-facing web surface of the semiconductor module is higher above the circuit substrate than a top surface of the other component, in which case the recess or groove receives any excess film material that may be present in the manufacturing method described herein. [0017] In a manufacturing method according to another aspect of the invention, a multi-chip module (MCM) may be made by disposing a plurality of components on a circuit substrate, each component having an upward-facing top surface; one of the components having a recess formed in its respective top surface; and applying a film so as to cover the top surfaces of the components and to enter into the recess. The recess is preferably formed as a groove in a peripheral region of the top surface. Then molding material may be injected so as to surround and seal side surfaces of the components, while not substantially covering the top surfaces thereof that are covered by the film. The recess may receive any excess film material that may be present, so as to prevent such excess film material from covering the respective side surfaces of the corresponding component and creating a void between the component and the molding material. This advantageous effect of the invention is particularly useful when the top component surface in which the recess is formed is higher above the circuit substrate than the respective top surface of another one of the components. [0018] Other features and advantages of the present invention will become apparent from the following description of an embodiment of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Fig. 1 is a side view of a prior art T-PAC module;
[0020] Fig. 2 is a plan view of a prior art multi-chip module (MCM);
[0021] Fig. 3 is a cross-section of the prior art MCM of Fig. 2;
[0022] Figs. 4, 5 and 6 show steps in a process of manufacturing the MCM of
Figs. 2 and 3;
[0023] Fig. 7 is a cross-sectional view of an intermediate product that is formed during the process of manufacturing an MCM according to an embodiment of the invention, Fig. 8 being a plan view thereof; and [0024] Fig. 9 is a schematic side view of a final product corresponding to the intermediate product disclosed in Fig. 7, Fig. 10 being a plan view thereof.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
[0025] An improvement which avoids the problem of the prior art is shown in Figures 7-10. A groove 75 is formed in the top surface of the conductive element 56 of a T-PAC module 54. When the film 70 is applied to the tops of the components C4, 54, and CI, any excess film material displaced by the excessive height of the module 54, instead of being displaced to the sides of the conductive element, instead is accommodated within the groove 75. This prevents the protrusions from forming at the sides of the conductive element and allows the resin material 58 to reach all portions of the sides of the conductive element 56. [0026] The final product is shown in Figure 9, after removal of the film 70. Some of the film material may remain in the groove 75. [0027] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, the present invention is not limited by the specific disclosure herein.

Claims

WHAT IS CLAIMED IS: 1. A semiconductor module comprising in combination: a circuit substrate; a semiconductor device and an additional component, each having respective upper and lower electrodes, said lower electrodes being disposed in electrical contact with said circuit substrate; a conductive element being electrically connected to said circuit substrate and having a web portion which bridges over and contacts the respective upper electrodes of both said semiconductor device and said additional component; said web portion having an upward-facing web surface, said web surface having a recess formed therein.
2. The module of claim 1, wherein said recess comprises a groove formed in a peripheral region of said web surface.
3. The module of claim 1, further comprising molded material surrounding and sealing said conductive element, said semiconductor device and said additional component.
4. The module of claim 3, wherein said upward-facing web surface is substantially free of said molded material.
5. The module of claim 1, wherein said additional component is a semiconductor device.
6. The module of claim 1, wherein said additional component is a passive component.
7. A multi-chip module (MCM) comprising in combination: a circuit substrate; the semiconductor module of claim 1 disposed on said circuit substrate; another component disposed on said circuit substrate; molded material surrounding and sealing both said semiconductor module and said other component.
8. The MCM of claim 7, wherein said other component is a second semiconductor module according to claim 1.
9. The MCM of claim 7, wherein said other component is a power semiconductor device.
10. The MCM of claim 7, wherein said other component is a passive component.
11. The MCM of claim 7, wherein the upward-facing web surface of said semiconductor module is higher above said circuit substrate than a top surface of said other component.
12. The MCM of claim 11 , wherein said recess formed in said web surface contains plastic film material.
13. A method of manufacturing a multi-chip module (MCM), comprising the steps of: disposing a plurality of components on a circuit substrate, each said component having an upward-facing top surface; one of said components having a recess formed in its respective top surface; applying a film so as to cover the top surfaces of the components and into said recess.
14. The method of claim 13, further comprising the step of forming said recess as a groove in a peripheral region of said top surface.
15. The method of claim 13, further comprising the step of injecting molding material so as to surround and seal side surfaces of said components, while avoiding said top surfaces thereof which are covered by said film.
16. The method of claim 15, wherein said recess receives excess film material so as to prevent said excess film material from covering the respective side surfaces of said one component.
17. The method of claim 13, wherein said top component surface having said recess is higher above said circuit substrate than the respective top surface of another one of said components.
18. The method of claim 17, wherein said recess receives excess film material so as to prevent said excess film material from covering the respective side surfaces of said one component.
PCT/US2005/019515 2003-07-14 2005-06-02 High power mcm package with improved planarity and heat dissipation WO2005122250A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007515599A JP2008502158A (en) 2004-06-03 2005-06-02 High output multichip module package with good flatness and heat dissipation

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US10/620,029 US6946740B2 (en) 2002-07-15 2003-07-14 High power MCM package
US57676604P 2004-06-03 2004-06-03
US60/576,766 2004-06-03
US58310404P 2004-06-25 2004-06-25
US60/583,104 2004-06-25
US11/141,861 2005-06-01
US11/141,861 US7453146B2 (en) 2003-07-14 2005-06-01 High power MCM package with improved planarity and heat dissipation

Publications (3)

Publication Number Publication Date
WO2005122250A2 true WO2005122250A2 (en) 2005-12-22
WO2005122250A3 WO2005122250A3 (en) 2007-01-18
WO2005122250B1 WO2005122250B1 (en) 2007-03-08

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PCT/US2005/019515 WO2005122250A2 (en) 2003-07-14 2005-06-02 High power mcm package with improved planarity and heat dissipation

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US (2) US7453146B2 (en)
WO (1) WO2005122250A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916958B2 (en) 2009-04-24 2014-12-23 Infineon Technologies Ag Semiconductor package with multiple chips and substrate in metal cap

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4319229B2 (en) * 2007-03-29 2009-08-26 シャープ株式会社 Semiconductor device
CN102082099B (en) * 2009-11-30 2013-11-27 万国半导体有限公司 Process method for packaging semiconductor with exposed pins
DE102014111930A1 (en) 2014-08-20 2016-02-25 Rupprecht Gabriel Thermally highly conductive, electrically insulating housing with electronic components and manufacturing processes
CN112447614A (en) * 2019-08-30 2021-03-05 朋程科技股份有限公司 Power device packaging structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545364B2 (en) * 2000-09-04 2003-04-08 Sanyo Electric Co., Ltd. Circuit device and method of manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7215022B2 (en) * 2001-06-21 2007-05-08 Ati Technologies Inc. Multi-die module

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545364B2 (en) * 2000-09-04 2003-04-08 Sanyo Electric Co., Ltd. Circuit device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916958B2 (en) 2009-04-24 2014-12-23 Infineon Technologies Ag Semiconductor package with multiple chips and substrate in metal cap

Also Published As

Publication number Publication date
US20050275112A1 (en) 2005-12-15
US20090035896A1 (en) 2009-02-05
US7453146B2 (en) 2008-11-18
US7745257B2 (en) 2010-06-29
WO2005122250A3 (en) 2007-01-18
WO2005122250B1 (en) 2007-03-08

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