DE102014111930A1 - Thermally highly conductive, electrically insulating housing with electronic components and manufacturing processes - Google Patents
Thermally highly conductive, electrically insulating housing with electronic components and manufacturing processes Download PDFInfo
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- DE102014111930A1 DE102014111930A1 DE102014111930.4A DE102014111930A DE102014111930A1 DE 102014111930 A1 DE102014111930 A1 DE 102014111930A1 DE 102014111930 A DE102014111930 A DE 102014111930A DE 102014111930 A1 DE102014111930 A1 DE 102014111930A1
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- leadframe
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- semiconductor package
- polyimide film
- housing
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- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000000465 moulding Methods 0.000 claims abstract description 24
- 229920001721 polyimide Polymers 0.000 claims abstract description 23
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 229920006332 epoxy adhesive Polymers 0.000 claims abstract description 5
- 239000004642 Polyimide Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000009745 resin transfer moulding Methods 0.000 claims description 3
- MEKOFIRRDATTAG-UHFFFAOYSA-N 2,2,5,8-tetramethyl-3,4-dihydrochromen-6-ol Chemical compound C1CC(C)(C)OC2=C1C(C)=C(O)C=C2C MEKOFIRRDATTAG-UHFFFAOYSA-N 0.000 claims 3
- 239000012778 molding material Substances 0.000 claims 2
- 239000000654 additive Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 claims 1
- 239000012811 non-conductive material Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract description 7
- 238000010292 electrical insulation Methods 0.000 abstract description 6
- 238000010276 construction Methods 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 239000004033 plastic Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 10
- 239000012790 adhesive layer Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000001721 transfer moulding Methods 0.000 description 5
- 238000005245 sintering Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- BUHVIAUBTBOHAG-FOYDDCNASA-N (2r,3r,4s,5r)-2-[6-[[2-(3,5-dimethoxyphenyl)-2-(2-methylphenyl)ethyl]amino]purin-9-yl]-5-(hydroxymethyl)oxolane-3,4-diol Chemical compound COC1=CC(OC)=CC(C(CNC=2C=3N=CN(C=3N=CN=2)[C@H]2[C@@H]([C@H](O)[C@@H](CO)O2)O)C=2C(=CC=CC=2)C)=C1 BUHVIAUBTBOHAG-FOYDDCNASA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004378 air conditioning Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229940125904 compound 1 Drugs 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004870 electrical engineering Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 229920006335 epoxy glue Polymers 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000013464 silicone adhesive Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000006228 supernatant Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Eine der wesentlichen Aufgabenstellungen an verlustbehaftete elektronische Schaltungen ist eine Aufbau- und Verbindungstechnik (AVT), die sowohl die einzelnen Potentiale elektrisch isoliert wie auch eine gute Wärmeabfuhr aus dem Halbleiter ermöglicht. Grundsätzlich ist das Prinzip aber bei allen Anforderungen in denen elektrische Isolation wie auch gute Wärmeleitung gefordert sind, einsetzbar und vorteilhaft. Aufgabe ist es, einen möglichst geringen thermischen Gesamtwiderstand zu erreichen, was nur durch extrem dünne Schichten oder sehr hohe Leitfähigkeiten des Schichtaufbaues zu erreichen ist. Aufgabe ist es ebenso, gute Isolationseigenschaften von passenden Kunststoffmaterialien durch Minimierung der Schichtdicke zur Reduzierung des thermischen Widerstandes zu nutzen. Vorgeschlagen wird dazu ein Halbleitergehäuse aus einem metallischen Leadframe (1), zumindest einem Halbleiter (3), der flächig auf dem strukturierten Leadframe (1) aufliegt und mit ihm elektrisch und thermisch verbunden ist. Eine 5µ bis 50µ dicke Polyimidfolie (2) ist vorgesehen, welche mit einem Epoxid-Kleber (7) mit einer Schichtdicke kleiner 20µm beschichtet ist und darüber mit dem Leadframe (1) auf der dem zumindest einen Halbleiter-Bauteil (3) gegenüber-liegenden Seite (1b) flächig verklebt ist und durch Einspritzen von Moldmasse ein Gehäuse bildet, bei dem der Polyimidfilm (2) nicht umspritzt an der Oberfläche bleibt und über die Fläche des Gehäusekörpers (6) hinausragt.One of the main tasks of lossy electronic circuits is a construction and connection technique (AVT), which enables both the individual potentials electrically isolated as well as a good heat dissipation from the semiconductor. In principle, however, the principle is applicable and advantageous for all requirements in which electrical insulation as well as good heat conduction are required. The task is to achieve the lowest possible total thermal resistance, which can be achieved only by extremely thin layers or very high conductivities of the layer structure. The task is also to use good insulation properties of suitable plastic materials by minimizing the layer thickness to reduce the thermal resistance. For this purpose, a semiconductor housing made of a metallic leadframe (1), at least one semiconductor (3), which rests flat on the structured leadframe (1) and is electrically and thermally connected to it, is proposed. A 5μ to 50μ thick polyimide film (2) is provided, which is coated with an epoxy adhesive (7) having a layer thickness of less than 20μm and above with the leadframe (1) on the at least one semiconductor component (3) opposite Side (1b) is adhesively bonded flat and forms by injecting molding compound a housing in which the polyimide film (2) is not overmolded on the surface and extends beyond the surface of the housing body (6).
Description
Diese Offenbarung (und die Ansprüche) betreffen Halbleitergehäuse aus einem metallischen Leadframe, zumindest einem Halbleiter, der flächig auf dem strukturierten Leadframe liegt und elektrisch und thermisch verbunden ist, sowie ein Verfahren zur Herstellung eines Halbleitergehäuses. Das Halbleitergehäuse hat einen metallischen Leadframe, zumindest einen Halbleiter, der flächig auf dem strukturierten Leadframe elektrisch und thermisch verbunden ist, sowie weitere Verbindungen auf einer Oberseite des Halbleiters zu dem Leadframe oder anderen Halbleitern auf dem Leadframe. Ein Leadframe ist ein lötbarer metallischer Leitungsträger in Form eines Rahmens oder Kamms zur maschinellen Herstellung von Halbleiterchips oder anderen elektronischen Komponenten, vgl. http://de.wikipedia.org/wiki/Leadframe This disclosure (and the claims) relate to semiconductor packages made of a metallic leadframe, at least one semiconductor, which lies flat on the structured leadframe and is electrically and thermally connected, and to a method for producing a semiconductor package. The semiconductor package has a metallic leadframe, at least one semiconductor electrically and thermally coupled to the patterned leadframe, and further interconnections on top of the semiconductor to the leadframe or other semiconductors on the leadframe. A leadframe is a solderable metallic conductor carrier in the form of a frame or comb for the machining of semiconductor chips or other electronic components, cf. http://de.wikipedia.org/wiki/Leadframe
Stand der Technik ist Prior art is
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WO 2008 090734 A1 WO 2008 090734 A1 -
JP 2009 123953 A JP 2009 123953 A -
DE 10 2009 014 794 B3DE 10 2009 014 794 B3 -
CN 101 847 589 ACN 101 847 589 A -
KR 2010 010 9369 AKR 2010 010 9369 A -
US 2009 035896 A1US 2009 035896 A1 -
US 2010 133684 A1US 2010 133684 A1
Ein Einsatz derartiger Gehäuse sind beispielsweise IPMs (Intelligent Power Modules) deren elektrische Komponenten die Leistungsbauteile und deren Ansteuerkomponenten für Motorsteuerungen beinhalten, vgl. auch die SPM – Smart Power Modules von Fairchild
Während in der Anfangszeit bei IPMs mit DCB (Direct Copper Bonding) oder IMS (Insulated Metal Substrates) vergossen in Modulen eingesetzt wurden hat wegen des kontinuierlichen Kostendrucks heute bei in großen Stückzahlen gefertigten IPMs die aus der IC Umhüllung bekannte Transfermoldingtechnik Einzug gefunden. Dabei wird die schlechte thermische Leitung der Umhüllungsmasse mit weniger als 0,5 °K/W durch die Integration von thermisch hoch leitfähigen DCB oder IMS Substraten erreicht, die in das Gehäuse mit integriert werden. While IPMs with DCB (Direct Copper Bonding) or IMS (Insulated Metal Substrates) were used as modules in the early days, the transfer molding technology known from the IC packaging has now found its way into large-volume IPMs due to the continuous cost pressure. In this case, the poor thermal conduction of the cladding compound is achieved at less than 0.5 ° K / W by the integration of thermally highly conductive DCB or IMS substrates, which are integrated into the housing.
"Hoch leitfähig" nach EIA/JESD 51 Standard bei Halbleitergehäusen werden Gehäuse mit einem Wärmeübergangs-Widerstand vom Halbleiter zum Kühlkörper (der thermische Widerstand) kleiner als 1 °K/W bezeichnet, während übliche Moldgehäuse typisch 10 °K/W also einen um den Faktor 10 schlechtere Kühlung bei gleicher Verlustleistung ermöglichen. "Highly conductive" according to EIA / JESD 51 Standard for semiconductor housings, housings with a heat transfer resistance from the semiconductor to the heat sink (the thermal resistance) are referred to as less than 1 ° K / W, while common mold housings typically refer to 10 ° K /
Die Transfermolding Technik, auch kurz Molding oder RTM (Resin Transfer Molding) bezeichnet, umhüllt dabei die Schaltungsträger mit duroplastischem Material. Die verwendeten Massen haben "sehr gute Isolationseigenschaften" mit einem Wert von größer als 100 kV/mm und lassen sich als dünnflüssige Masse, in die Kavität eines Werkzeuges einspritzen und umhüllen dort den Schaltungsträger. Heute werden monatlich Milliarden von Bauelementen wie ICs, Transistoren, Multichipmodulen mit Transfermolding umhüllt. The Transfermolding technique, also referred to as Molding or RTM (Resin Transfer Molding), encloses the circuit carriers with thermosetting material. The masses used have "very good insulation properties" with a value of greater than 100 kV / mm and can be injected as a liquid mass into the cavity of a tool and encase the circuit carrier there. Today billions of components such as ICs, transistors, multichip modules are covered with transfer molding every month.
Dabei wird aus einem Reservoir mit zunächst fester bzw. flüssiger Moldmasse eine Werkzeugkammer unter Druck und Wärme über Einspritzkanäle mit dünnflüssiger Masse gefüllt. Die Moldmasse wird unter Wärmezufuhr ausgehärtet. Das Transfermolding ist bekannt und umfasst sehr viele Anwendungen in der Elektrotechnik von Lampensockeln bis zum miniaturisierten Chip Size Package Gehäuse für Halbleiter. Grund für den Einsatz des Verfahrens ist eine sehr niedrige Viskosität in der Verarbeitung während des Umhüllungsprozesses und die hohe thermische Stabilität, die bis an die Funktionsgrenze von Halbleitern gewährleistet ist. Heute werden sowohl kleinste wie große Halbleiter in RTM Gehäusen hergestellt. Zumeist wird Epoxid als Bindemittel mit feinst gemahlenen isolierenden Feststoffen als Füllstoff eingesetzt. In this case, a tool chamber is filled under pressure and heat via injection channels with low-viscosity mass from a reservoir with initially solid or liquid molding compound. The molding compound is cured with heat. The transfer molding is well known and covers a great many applications in the field of electrical engineering, from lamp sockets to miniaturized chip size packages for semiconductors. The reason for the use of the method is a very low viscosity in the processing during the coating process and the high thermal stability, which is guaranteed up to the functional limit of semiconductors. Today, both small and large semiconductors are manufactured in RTM housings. In most cases, epoxy is used as a binder with very finely ground insulating solids as a filler.
Ein IPM ist im Sinne der Verbindungstechnik ein MCM (Multichipmodul) wie es in Bild 4 dargestellt ist. Dabei werden die Halbleiter (
Die flächige Verbindung des Halbleiters erfolgt mit hoher thermischer Leitfähigkeit durch Löten, Sintern oder Kleben. Um die Größenordnungen deutlich zu machen: Die Leadframes aus Kupfer haben eine thermische Leitfähigkeit von ca. 400W/mK, das Lot hat ca. 70W/mK, Silizium 150W/mK Moldmasse 1 bis 2W/mK, AluminiumOxid 30W/mK, Polyimid 0,3 bis 0,4W/mK, Luft 0,026W/mK. Damit hat man im Aufbau Leitfähigkeitsunterschiede von bis zu 1/15.000. The surface connection of the semiconductor is carried out with high thermal conductivity by soldering, sintering or gluing. To make the order of magnitude clear: The leadframes made of copper have a thermal conductivity of approx. 400W / mK, the solder has approx. 70W / mK, silicon 150W /
Eine der wesentlichen Aufgabenstellungen an verlustbehaftete elektronische Schaltungen ist eine Aufbau- und Verbindungstechnik (AVT), die sowohl die einzelnen Potentiale elektrisch isoliert wie auch eine gute Wärmeabfuhr aus dem Halbleiter ermöglicht. Beispiele sind IPMs (integrated Power Modules), die eine wesentliche Rolle in der energieeffizienten Steuerung z.B. in der Antriebstechnik, in der Photovoltaik und Klimatechnik spielen, aber auch die LED Technik für Beleuchtung hat ähnliche Anforderungen. Grundsätzlich ist das Prinzip aber bei allen Anforderungen in denen elektrische Isolation wie auch gute Wärmeleitung gefordert sind, einsetzbar und vorteilhaft. One of the main tasks of lossy electronic circuits is a construction and connection technique (AVT), which enables both the individual potentials electrically isolated as well as a good heat dissipation from the semiconductor. Examples are IPMs (Integrated Power Modules), which play an important role in energy efficient control, eg in drive technology, in photovoltaic and air conditioning technology, but also the LED technology for lighting has similar requirements. In principle, however, the principle is applicable and advantageous for all requirements in which electrical insulation as well as good heat conduction are required.
Diese Aufgabe soll einfach und kostengünstig gelöst werden. Aufgabe ist es weiterhin einen möglichst geringen thermischen Gesamtwiderstand zu erreichen, was nur durch extrem dünne Schichten oder sehr hohe Leitfähigkeiten des Schichtaufbaues zu erreichen ist. Aufgabe ist es ebenso, gute Isolationseigenschaften von passenden Kunststoffmaterialien durch Minimierung der Schichtdicke zur Reduzierung des thermischen Widerstandes zu nutzen. Dies stellt den Fachmann vor ein multikriterielles Optimierungsproblem. This task should be solved easily and inexpensively. The task is furthermore to achieve the lowest possible overall thermal resistance, which can only be achieved by means of extremely thin layers or very high conductivities of the layer structure. The task is also to use good insulation properties of suitable plastic materials by minimizing the layer thickness to reduce the thermal resistance. This presents the skilled person with a multi-criteria optimization problem.
Gelöst wird die Aufgabe mit Anspruch 1 oder Anspruch 10. The problem is solved with
Bei einem flächigen Aufbau aus Halbleiter, Lot, Leadframe, Isolationschicht bis zu einem Kühlkörper trägt damit bei gleicher Dicke das elektrisch isolierende Material den weitaus größten Anteil des Wärmewiderstandes bei. In the case of a planar structure comprising semiconductors, solder, leadframe, insulation layer up to a heat sink, the electrically insulating material contributes by far the largest part of the thermal resistance at the same thickness.
Polyimid hat etwa den 1.000 fachen Anteil an dem thermischen Widerstand, sofern das Material genauso dick ist. Selbst bei thermisch hoch-leitfähigen isolierenden Keramiken, z.B. Aluminiumoxid, trägt das Isolationsmaterial immer noch ca. 5fach zum thermischen Gesamtwiderstand bei gleicher Dicke bei. Aufgabe der Auslegung ist es, immer unter den Randbedingungen max. Halbleitertemperatur (an der Oberfläche) einen möglichst geringen thermischen Gesamtwiderstand zum Kühlkörper zu erreichen. Polyimide has approximately 1,000 times the thermal resistance, as long as the material is just as thick. Even with thermally highly conductive insulating ceramics, e.g. Alumina, the insulation material still contributes about 5 times the total thermal resistance at the same thickness. The task of the design is always under the boundary conditions max. Semiconductor temperature (on the surface) to achieve the lowest possible total thermal resistance to the heat sink.
Bei der DCB-Technik mit einer Durchschlagfestigkeit von zumindest 20 kV/mm nutzt man die relativ gute thermische Leitfähigkeit des Aluminiumoxids mit (zumindest) 30W/mK um eine gute Wärmeleitung zu erreichen. Beim IMS wird eine sehr dünne Schicht aus Epoxid oder Polyimid verwendet. Hier kommt die sehr hohe Durchschlagfestigkeit des Materials mit mehr als 200 kV/mm zum Tragen, die sehr dünne Schichten mit ausreichender Isolation nach
Da die Dicke der den Aufbau umhüllenden Schicht durch die Isolationseigenschaften des Materials und die Grenzen der Schichtdicken begrenzt sind, scheidet das übliche Umhüllen mit Moldmassen als gute Wärmeübertrager aus. Aus fertigungstechnischen Gründen kann die Wandstärke nicht wesentlich geringer als 1mm sein, da ansonsten die Moldkräfte ein Verbiegen des Schaltungsträgers (Leadframes) erzeugen würde und ein unkontrollierter Abstand zur Außenhülle das Ergebnis wäre. Mit den heute bekannten Technologien würde der thermische Widerstand des Moldgehäuses damit weiter mindestens 10fach höher sein als die aus einem 100 µm dicken Halbleiter gebildete Wärmequelle, die über ein 100µm dickes Lot und einem 300µm Kupfer-Leadframe an die Außenfläche übertragen wird. Since the thickness of the layer enveloping the structure is limited by the insulating properties of the material and the limits of the layer thicknesses, the usual encapsulation with molding compounds separates out as good heat exchangers. For manufacturing reasons, the wall thickness can not be significantly less than 1mm, otherwise the mold forces would produce bending of the circuit carrier (leadframes) and an uncontrolled distance to the outer shell would be the result. With the technologies known today, the thermal resistance of the mold housing would thus continue to be at least 10 times higher than the heat source formed from a 100 μm thick semiconductor, which is transferred to the outer surface via a 100 μm thick solder and a 300 μm copper leadframe.
Stand der Technik ist es bisher, einen isolierenden thermisch gut leitfähigen Träger (DCB/IMS Substrat) der Schaltung anstelle des Leadframes zu verwenden. Diese Schaltungsträger werden nicht komplett umhüllt und ragen auf der Oberseite des Moduls als Kontaktfläche zu einem Kühlkörper heraus. Beispiele sind in Datenblättern diverser Hersteller zu sehen. Durch diesen Kunstgriff kann man eine um den Faktor 10 bis 100 höhere thermische Leitfähigkeit erreichen und damit die Halbleiter ausreichend gut thermisch an eine Kühlfläche verbinden. Dabei hat die elektrisch isolierende aber gut thermisch leitfähige keramische Ebene typisch eine Dicke von 1/4mm bis 1mm. Diese Dicke ist erforderlich um die Durchschlagfestigkeit von 1kV bis 5kV, die in den typischen Anwendungen gefordert ist, zu erreichen. In dieser Technik werden bis heute die Mehrzahl der IPMs aufgebaut. Der Aufbau ist recht kompliziert, da das DCB Substrat zusätzlich über ein gelötetes Leadframe elektrisch nach außen geführt wird. Dies wird heute mit DIL Anschlussformen gemacht, wobei das Modul auf einer Leiterkarte durch Wellenlöten auf der Gegenseite der Komponentenbestückungsseite gelötet wird. Um heutzutage eine effektive Fertigungstechnik für die Bestückung zu erreichen sollte jedoch die Aufbautechnik vorzugsweise eine SMD Bestückung zulassen. Beide Probleme werden durch die Erfindung gelöste. The prior art has hitherto been to use an insulating, thermally well-conductive carrier (DCB / IMS substrate) of the circuit instead of the leadframe. These circuit carriers are not completely enveloped and protrude on the top of the module as a contact surface to a heat sink. Examples can be seen in datasheets of various manufacturers. Through this trick you can achieve a factor of 10 to 100 higher thermal conductivity and thus connect the semiconductor sufficiently good thermally to a cooling surface. The electrically insulating but good thermally conductive ceramic layer typically has a thickness of 1 / 4mm to 1mm. This thickness is required to achieve the dielectric strength of 1kV to 5kV required in typical applications. In this technique, the majority of IPMs are still being built. The structure is quite complicated, since the DCB substrate is additionally led electrically outwards via a soldered leadframe. This is done today with DIL terminal forms, where the module is soldered on a circuit board by wave soldering on the opposite side of the component assembly side. In order to achieve an effective production technology for assembly nowadays, however, the construction technique should preferably allow SMD assembly. Both problems are solved by the invention.
Bei den bekannten Anordnungen wird dann der Anschluss der Module auf eine Leiterkarte wieder über einen zusätzlich angebrachten Leadframe erzeugt, was die Material- und Prozesskosten erhöht. In the known arrangements, the connection of the modules to a printed circuit board is then generated again via an additionally attached leadframe, which increases the material and process costs.
Solche Umsetzungen sind in z.B.
Dieser Stand der Technik ist gegenüber der Erfindung aufwendiger und teurer und erfordert mehr Material. This prior art is more expensive and expensive than the invention and requires more material.
Auf die Figuren wird Bezug genommen. The figures are referred to.
Die Ausführungsformen der Erfindung sind anhand von Beispielen dargestellt und nicht auf eine Weise, in der Beschränkungen aus den Figuren in die Patentansprüche übertragen oder hineingelesen werden. Gleiche Bezugszeichen in den Figuren geben ähnliche Elemente an. The embodiments of the invention are illustrated by way of example and not in a manner in which limitations of the figures are transferred or read into the claims. Like reference numerals in the figures indicate similar elements.
Ein Beispiel der Erfindung betrifft ein Moldgehäuse für Halbleiter nach
Der sehr dünne, mit Kleber, insbes. Epoxidkleber
Vorteilhaft ist, dass der Isolationsfilm
Die Verbindung des Films
Um die elektrische Isolation zum Kühlkörper
Die Kontaktierung der Halbleiter
Unterschiedlich zu einem SO-Gehäuse ist ausschließlich, dass die Leads
Wesentliche Vorteile der Anordnung und des Fertigungsverfahrens sind, dass sie sehr preiswert sind, weil weniger Materialeinsatz und weniger Prozessschritte benötigt werden. The main advantages of the arrangement and the manufacturing process are that they are very inexpensive, because less material and fewer process steps are needed.
Das Verfahren lässt sich sehr einfach in Standard-Moldmaschinen integrieren, da nur ein zusätzlicher Film
Durch die flächige Abdeckung des Leadframe
Alle weiteren Prozesse wie das Freistanzen des Leadframe
Damit wird es möglich IPMs im Kostenrahmen von MCM Gehäusen zu erstellen wobei sowohl eine elektrische Isolation zu einem Kühlkörper
Die Polyimid-Schicht
Die Schichtdicke des Epoxidklebers
Um die thermische Kontaktierung des Kühlkörpers
Eine Anwendung ist eine mit Leistungs-Halbleitern bestückte mehrphasige Brücke. Jedem Halbleiter ist eine Treiberschaltung zugeordnet. Die Brücke bildet ein intelligentes Power-Modul für z. B. die Antriebstechnik. One application is a multi-phase bridge populated with power semiconductors. Each semiconductor is assigned a driver circuit. The bridge forms an intelligent power module for z. B. the drive technology.
ZITATE ENTHALTEN IN DER BESCHREIBUNG QUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- WO 2008090734 A1 [0002] WO 2008090734 A1 [0002]
- JP 2009123953 A [0002] JP 2009123953 A [0002]
- DE 102009014794 B3 [0002] DE 102009014794 B3 [0002]
- CN 101847589 A [0002] CN 101847589 A [0002]
- KR 20100109369 A [0002] KR 20100109369 A [0002]
- US 2009035896 A1 [0002] US 2009035896 A1 [0002]
- US 2010133684 A1 [0002] US 2010133684 A1 [0002]
- WO 2013/061183 [0017] WO 2013/061183 [0017]
- JP 2007165426 [0020] JP 2007165426 [0020]
Zitierte Nicht-PatentliteraturCited non-patent literature
- http://www.fairchildsemi.com/product-technology/spm/ [0003] http://www.fairchildsemi.com/product-technology/spm/ [0003]
- IEC 60243-1 [0015] IEC 60243-1 [0015]
- Michael Pecht, Handbook of Electronic Package Design, CRC Press, 1991 [0020] Michael Pecht, Handbook of Electronic Package Design, CRC Press, 1991 [0020]
Claims (15)
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