JP2007165426A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007165426A
JP2007165426A JP2005357172A JP2005357172A JP2007165426A JP 2007165426 A JP2007165426 A JP 2007165426A JP 2005357172 A JP2005357172 A JP 2005357172A JP 2005357172 A JP2005357172 A JP 2005357172A JP 2007165426 A JP2007165426 A JP 2007165426A
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chip
semiconductor device
insulating sheet
power chip
input
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Kenichi Hayashi
建一 林
Hiroyuki Ozaki
弘幸 尾崎
Hisashi Kawato
寿 川藤
Shinya Nakagawa
信也 中川
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for improving heat radiation properties and strength around a screw mounting hole. <P>SOLUTION: The semiconductor device includes a frame made of metal having a lead terminal 21 for input/output to and from a power chip and a lead terminal for input/output to and from an IC chip at opposing sides; a power chip mounted on the first surface of the power chip mount of the frame; an IC chip mounted on the first surface of the IC chip mount of the frame; a rectangular insulating sheet installed at the side of a second surface that opposes the first surface of the power chip mount; a mold resin 6 that allows the lead terminal to project, exposes one surface of the resin sheet to the outer surface, seals at least the IC chip and the power chip, and has thermal conductivity that is smaller than that of the insulating sheet; and a screw fastener 9 provided near an edge in the direction of a long side for screw-fastening the mold resin 6. A cutout is formed in the insulating sheet so that the screw fastener 9 is wrapped from two directions, and the length of the long side of the insulating sheet is made longer than the distance between the screw fasteners 9. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、パワーチップを含む電力用等の半導体装置に関するものである。   The present invention relates to a semiconductor device, and more particularly to a power semiconductor device including a power chip.

電力用等の半導体装置では、高い絶縁性を確保しながら、パワーチップで発生した熱を効率よく外部に放熱することが非常に重要である。放熱性能を高めるには、パワーチップ下の絶縁層を薄くすることが望ましいが、絶縁層を薄くすると絶縁特性が劣化することが懸念される。   In a semiconductor device for electric power or the like, it is very important to efficiently dissipate the heat generated in the power chip to the outside while ensuring high insulation. In order to improve the heat dissipation performance, it is desirable to make the insulating layer under the power chip thinner, but there is a concern that the insulating characteristics deteriorate if the insulating layer is made thinner.

また、全体を１種の樹脂でフルモールドする構造では、絶縁層を薄くするほど、絶縁層形成部への樹脂の回り込みが悪くなり、モールド性が極端に劣化するため、絶縁層を薄くすることは極めて困難である。従って、絶縁層はある程度厚くせざるを得ず、そのために放熱性が低下する。   In addition, in a structure where the whole is fully molded with one type of resin, the thinner the insulating layer, the worse the resin wraps around the insulating layer forming part, and the moldability deteriorates extremely. Is extremely difficult. Therefore, the insulating layer has to be thick to some extent, and thus heat dissipation is reduced.

絶縁層をある程度厚くして、放熱性を高めるためには、絶縁層に熱伝導率の良好な樹脂を用いる。熱伝導性の良好な樹脂は高価であり、不必要な部位にまで高価な高性能樹脂を用いるとコストが高くなる。   In order to increase the heat dissipation by increasing the thickness of the insulating layer, a resin having good thermal conductivity is used for the insulating layer. Resins with good thermal conductivity are expensive, and the cost increases when expensive high-performance resins are used even in unnecessary parts.

そこで、特許文献１に開示されているように、絶縁層として、ある程度の厚さで熱伝導性がよい絶縁シートを用いることで、絶縁性確保と高放熱性とを容易に両立させる方法が提案されている。この方法は、必要な部位のみにしか、高性能な絶縁樹脂シートを用いないので、コスト的にも有利である。   Therefore, as disclosed in Patent Document 1, a method for easily ensuring both insulation and high heat dissipation is proposed by using an insulating sheet having a certain thickness and good thermal conductivity as disclosed in Patent Document 1. Has been. This method is advantageous in terms of cost because a high-performance insulating resin sheet is used only for necessary portions.

特開２００５−１０９１００号公報（第４頁−第８頁、図３−図９）Japanese Patent Laying-Open No. 2005-109100 (pages 4 to 8, FIGS. 3 to 9)

上記特許文献１に開示された半導体装置では、通常、半導体装置を固定するためのネジ取り付け穴が設けられているため、ネジ取り付けに用いる穴によって、絶縁シートのシートサイズが制約されていた。   In the semiconductor device disclosed in Patent Document 1, since a screw attachment hole for fixing the semiconductor device is usually provided, the sheet size of the insulating sheet is restricted by the hole used for screw attachment.

シートサイズが大きくなるほど、放熱性は改善されるが、シートサイズが制約されることにより、放熱性が低下し、ひいては半導体装置の小型化が阻まれるという問題があった。   As the sheet size is increased, the heat dissipation is improved. However, since the sheet size is restricted, there is a problem that the heat dissipation is reduced and the miniaturization of the semiconductor device is hindered.

一般に、半導体装置には反りがあるため、放熱性を確保するためには、ネジ固定する締め付け力を反りの矯正力とすることにより、ヒートシンクとの間に介在させるグリースを薄くする必要がある。しかしながら、ネジ取り付け穴周囲の強度に制約がある場合、半導体装置に許容される反り量にに制限が生じるという問題があった。この場合、反り量を小さくするために、半導体装置を構成する材料、主に、モールド樹脂の選択に制約が生じるという問題があった。   In general, since a semiconductor device has a warp, in order to ensure heat dissipation, it is necessary to make the grease interposed between the heat sink thin by using a tightening force for fixing the screw as a correction force for the warp. However, when the strength around the screw mounting hole is limited, there is a problem that the amount of warpage allowed in the semiconductor device is limited. In this case, in order to reduce the amount of warpage, there is a problem that the selection of the material constituting the semiconductor device, mainly the mold resin, is restricted.

本発明は、上記のような問題を解決するものであり、放熱性とネジ取り付け穴周囲の強度とを改善した半導体装置を提供することを目的とする。   The present invention solves the above-described problems, and an object thereof is to provide a semiconductor device having improved heat dissipation and strength around a screw mounting hole.

本発明に係る半導体装置は、パワーチップへの入出力用リード端子とＩＣチップへの入出力用リード端子とを対向する辺に有する金属からなるフレームと、
上記フレームのパワーチップ搭載部の第１面に搭載されたパワーチップと、
上記フレームのＩＣチップ搭載部の第１面に搭載されたＩＣチップと、
上記パワーチップ搭載部の第１面と対向する第２面側に設置され、上記入出力用リード端子が並ぶ方向に長辺を有する矩形状で絶縁性の絶縁シートと、
上記リード端子を突出させ、上記絶縁シートの一面を外表面に露出させ、かつ、少なくとも上記ＩＣチップ及びパワーチップを封止し、上記絶縁シートよりも熱伝導率の小さな封止樹脂と、
上記封止樹脂をネジ止め固定するために、上記パワーチップへの入出力用リード端子とＩＣチップへの入出力用リード端子とが対向する方向と直交する方向の上記封止樹脂の両端部近傍に設けられたネジ止め部とを含む半導体装置において、
上記絶縁シートに、上記ネジ止め部を二方または三方から包むように切り欠き部が形成され、上記絶縁シートの長辺の長さが上記ネジ止め部の間の距離より長くなっているものである。 A semiconductor device according to the present invention comprises a metal frame having input / output lead terminals to a power chip and input / output lead terminals to an IC chip on opposite sides;
A power chip mounted on the first surface of the power chip mounting portion of the frame;
An IC chip mounted on the first surface of the IC chip mounting portion of the frame;
A rectangular insulating insulating sheet installed on the second surface side facing the first surface of the power chip mounting portion and having long sides in the direction in which the input / output lead terminals are arranged;
The lead terminal protrudes, one surface of the insulating sheet is exposed on the outer surface, and at least the IC chip and the power chip are sealed, and a sealing resin having a lower thermal conductivity than the insulating sheet;
Near both ends of the sealing resin in a direction orthogonal to the direction in which the input / output lead terminals to the power chip and the input / output lead terminals to the IC chip face each other in order to fix the sealing resin with screws. In a semiconductor device including a screwing portion provided in
The insulating sheet is formed with a notch so as to wrap the screwing part from two or three sides, and the length of the long side of the insulating sheet is longer than the distance between the screwing parts. .

本発明に係る半導体装置によれば、放熱性とネジ取り付け穴周囲の強度とを改善した半導体装置を提供することができる。   The semiconductor device according to the present invention can provide a semiconductor device with improved heat dissipation and strength around the screw mounting hole.

実施の形態１．
本発明では、絶縁シートの長辺の長さを、ネジ止め部の間の距離よりも長くし、特に、放熱性向上の効果が大きいパワーチップへの入出力用リード端子側の絶縁シートの辺の長さを長くし、さらに、ネジ止め部の間よりも外側に、フレームのパワーチップ搭載部を設置し、放熱性の向上による小型化と、ネジ止め部の周囲の強度を増大するようにしたものであり、半導体装置の反りに対する矯正力も増大し、半導体装置をグリースを介してヒートシンクに取り付けた場合のグリースの薄膜化が可能となる。 Embodiment 1 FIG.
In the present invention, the length of the long side of the insulating sheet is made longer than the distance between the screwing portions, and in particular, the side of the insulating sheet on the input / output lead terminal side to the power chip that has a large effect of improving heat dissipation In addition, the power chip mounting part of the frame is installed outside the space between the screwing parts to reduce the size by improving heat dissipation and increase the strength around the screwing parts. Therefore, the correction force against the warp of the semiconductor device is also increased, and it becomes possible to reduce the thickness of the grease when the semiconductor device is attached to the heat sink via the grease.

さらには、従来、反りを低減するために制限されていた材料選択や設計自由度が向上するので、コスト低減も期待できる。   Furthermore, since the selection of materials and the degree of design freedom that have been conventionally limited to reduce warpage are improved, cost reduction can also be expected.

以下に、本実施の形態１の具体的な例を、図に基づいて説明する。
図１は、本発明に係る半導体装置の実施の形態１を示す断面図であり、図２は、本発明に係る半導体装置の実施の形態１を示す平面図である。 Below, the specific example of this Embodiment 1 is demonstrated based on figures.
FIG. 1 is a cross-sectional view showing a first embodiment of the semiconductor device according to the present invention, and FIG. 2 is a plan view showing the first embodiment of the semiconductor device according to the present invention.

本実施の形態１の半導体装置は、銅などの電導性のよい金属からなり、あらかじめ所定の電気回路が形成されたフレーム１と、フレーム１の一部を曲げることにより一段低くなった部位に形成されているダイパッド１ａにはんだ（図示せず）で固着された、ＩＧＢＴ、ＦＷＤｉといったパワーチップ２と、フレーム１の他の部位にはんだ（図示せず）で固着された、ＩＧＢＴやＦＷＤｉを制御するためのＩＣチップ３と、ダイパッド１ａの裏面に固着された、封止樹脂よりも熱伝導率が大きい絶縁シート７とを備えている。パワーチップ２の裏面電極とフレーム１とは、はんだによる固着により電気的に接続されている。   The semiconductor device according to the first embodiment is made of a metal having good conductivity such as copper, and is formed in a frame 1 in which a predetermined electric circuit is formed in advance, and in a portion lowered by bending a part of the frame 1. The power chip 2 such as IGBT and FWDi fixed to the die pad 1a which is fixed by solder (not shown) and the IGBT and FWDi fixed to the other part of the frame 1 by solder (not shown) are controlled. And an insulating sheet 7 fixed to the back surface of the die pad 1a and having a higher thermal conductivity than the sealing resin. The back electrode of the power chip 2 and the frame 1 are electrically connected by fixing with solder.

パワーチップ２の表面電極とフレーム１、パワーチップ２の表面電極同士、さらには、フレーム１内部の所定部位同士が、アルミワイヤ４により必要に応じ電気的に接続されている。   The surface electrode of the power chip 2 and the frame 1, the surface electrodes of the power chip 2, and further, predetermined portions inside the frame 1 are electrically connected by an aluminum wire 4 as necessary.

ＩＣチップの表面電極と、フレーム１とは、アルミワイヤ４よりも線径の小さい金ワイヤ５により接続されている。   The surface electrode of the IC chip and the frame 1 are connected by a gold wire 5 having a smaller diameter than the aluminum wire 4.

フレーム１のダイパッド１ａと、ＩＣチップ３が搭載されたＩＣチップ搭載部とは略平行に形成されている。   The die pad 1a of the frame 1 and the IC chip mounting portion on which the IC chip 3 is mounted are formed substantially in parallel.

絶縁シート７のサイズは、ダイパッド１ａよりも大きく、また、絶縁シート７がダイパッド１ａと固着された面と反対の面には、銅箔８が設置されており、銅箔８の一面は全体をモールドするモールド樹脂６の外部に露出している。   The size of the insulating sheet 7 is larger than that of the die pad 1a, and a copper foil 8 is provided on the surface opposite to the surface on which the insulating sheet 7 is fixed to the die pad 1a. It is exposed outside the mold resin 6 to be molded.

パワーチップ２及びＩＣチップ３を含む半導体装置１００は、リード端子２１をモールド樹脂６から突出させている。   In the semiconductor device 100 including the power chip 2 and the IC chip 3, the lead terminal 21 is protruded from the mold resin 6.

リード端子２１の突出していない２辺に近い部分には、ネジ止め固定用のネジ止め部９が対向する形で２箇所存在する。   Two portions of the lead terminal 21 near the two sides that do not protrude are present in a form facing the screw fixing portions 9 for fixing with screws.

なお、絶縁シート７とダイパッド１ａは、直接固着されていることが望ましい。直接固着することができる絶縁シート７としては、例えば、Ｂステージ状態のエポキシ樹脂をベースとする樹脂に、熱伝導性の無機フィラー、例えば、Ａｌ２Ｏ３、ＢＮ、ＡｌＮ、Ｓｉ２Ｏ３、Ｓｉ３Ｎ４等を含むものが挙げられる。 It is desirable that the insulating sheet 7 and the die pad 1a are directly fixed. As the insulating sheet 7 that can be directly fixed, for example, a resin based on an epoxy resin in a B stage state, a heat conductive inorganic filler, such as Al 2 O 3 , BN, AlN, Si 2 O 3 , those containing Si 3 N 4, or the like can be mentioned.

図３は、半導体装置１００をネジ止め部９を用いてネジ固定することで、放熱グリース２３を介して冷却用ヒートシンク２２に組みつけた状況を示す断面図である。   FIG. 3 is a cross-sectional view illustrating a state in which the semiconductor device 100 is fixed to the cooling heat sink 22 via the heat dissipating grease 23 by screwing using the screwing portion 9.

図３に示したように、フレーム１は曲げフレームであるので、薄い絶縁シートを用いても、リード端子２１と冷却用ヒートシンク２２との絶縁距離ｈの確保が容易であり、コスト的にも放熱的にも有利である。   As shown in FIG. 3, since the frame 1 is a bent frame, it is easy to secure the insulation distance h between the lead terminal 21 and the cooling heat sink 22 even if a thin insulating sheet is used, and heat is also dissipated. This is also advantageous.

このように、半導体装置１００は、パワーチップ直下の絶縁特性を確保しながら、パワーチップで発生する熱を効率よく外部に放出することができる構造となっている。   As described above, the semiconductor device 100 has a structure capable of efficiently releasing the heat generated in the power chip to the outside while ensuring the insulating characteristics directly under the power chip.

図２に示したように、この半導体装置１００において、パワーチップへの入出力リード端子２１とＩＣチップへの入出力リード端子とが対向する辺に設けられ、パワーチップへの入出力リード端子２１側において、絶縁シート（銅箔８と同一位置）のパワーチップへの入出力リード端子２１とＩＣチップへの入出力リード端子とが対向する方向と直交する方向の絶縁シートの辺（長辺）の長さＬは、パワーチップへの入出力リード端子２１とＩＣチップへの入出力リード端子とが対向する方向と直交する方向の端部近傍に設けられた２箇所のネジ止め部９の間の距離Ｄよりも大きい。   As shown in FIG. 2, in the semiconductor device 100, the input / output lead terminal 21 to the power chip and the input / output lead terminal to the IC chip are provided on opposite sides, and the input / output lead terminal 21 to the power chip is provided. Side of the insulating sheet (long side) in a direction orthogonal to the direction in which the input / output lead terminal 21 to the power chip and the input / output lead terminal to the IC chip face each other. The length L is between the two screwing portions 9 provided in the vicinity of the end in the direction orthogonal to the direction in which the input / output lead terminal 21 to the power chip and the input / output lead terminal to the IC chip face each other. Is greater than the distance D.

このような構成とすることにより、ネジ止め部９周囲にまで、放熱面積を広げることができるので、放熱性が向上する。   By setting it as such a structure, since a thermal radiation area can be expanded to the periphery of the screwing part 9, heat dissipation is improved.

電力用半導体装置では、装置サイズを決定する上で放熱性は重要なファクターであるので、放熱性を向上させると装置の小型化にもつながる。   In a power semiconductor device, heat dissipation is an important factor in determining the size of the device, so improving the heat dissipation leads to miniaturization of the device.

また、パワーチップへの入出力用のリード端子２１側において、絶縁シートの長辺長さＬをネジ止め部９の間の距離Ｄよりも大きくすることによって、特に、放熱性が向上する効果が大きくなる。   Further, on the lead terminal 21 side for input / output to / from the power chip, by making the long side length L of the insulating sheet larger than the distance D between the screwing portions 9, the effect of improving the heat dissipation is particularly improved. growing.

さらに、ネジ止め部９の間の外側にまで絶縁シートを設置することにより、絶縁シートを超えない範囲で、ダイパッドもネジ止め部９の間の外側にまで設置できる。   Furthermore, by installing the insulating sheet to the outside between the screwing portions 9, the die pad can be installed to the outside between the screwing portions 9 as long as the insulating sheet is not exceeded.

このように、ダイパッドもネジ止め部９の間の外側の範囲まで設置することによって、ネジ止め部９の周辺における封止樹脂６中に、フレーム部が存在する領域が増えるので、ネジ止め部９の周辺の強度が大幅に上昇する。   In this way, by installing the die pad to the outer area between the screwing portions 9, the area where the frame portion exists in the sealing resin 6 around the screwing portions 9 is increased. The strength of the surrounding area will increase significantly.

ネジ止め部９を用いてネジ締め固定する場合、ネジ締め力によりネジ止め部周囲のモールド樹脂６に応力がかかるが、面積の広いフレーム全体で応力を分散させながら受けることになるので、ネジ締め固定する場合の樹脂われに対する強度が大幅に向上する。   When screwing and fixing using the screwing part 9, stress is applied to the mold resin 6 around the screwing part due to the screwing force, but since the stress is distributed throughout the wide frame, The strength against resin cracking when fixing is greatly improved.

これは、本発明者らが行った実験によっても確かめられている。すなわち、本発明を適用することで、放熱性を向上させて装置を小型化することができるばかりではなく、さらに、ネジ締めによる樹脂われ耐量をも向上させることができることが分かった。   This is confirmed by experiments conducted by the present inventors. That is, it was found that by applying the present invention, not only can the heat dissipation be improved and the apparatus can be reduced in size, but also the resin breakage resistance by screw tightening can be improved.

また、ネジ締め耐量を向上させたことにより、従来よりも強く締め付けることができるので、反り矯正に対する効果の向上が期待される。   Moreover, since the tightening tolerance can be tightened more strongly than before, an improvement in the effect on warping correction is expected.

図３に示したように、冷却用ヒートシンク２２と半導体装置１００の間には、放熱用グリ−ス２３を介在させるが、ネジ締め耐量を向上させたことにより、放熱用グリース２３の厚さを、半導体装置の反り強制して薄くすることができる。   As shown in FIG. 3, a heat dissipating grease 23 is interposed between the cooling heat sink 22 and the semiconductor device 100. By improving the screw tightening resistance, the thickness of the heat dissipating grease 23 is increased. The warp of the semiconductor device can be forcibly thinned.

一般に、放熱用グリースの熱伝導性は高くないので、薄くすることが放熱性を確保する上で非常に重要である。   In general, the thermal conductivity of the heat dissipating grease is not high, so it is very important to reduce the thickness in order to ensure the heat dissipating property.

さらに、視点を変えれば、本発明によれば、半導体装置の反りに対する許容度が増すことになるので、設計自由度や、材料選定の自由度が増し、結果として小型化や低コスト化も達成できるという効果もある。   Furthermore, from a different perspective, according to the present invention, the tolerance for warping of the semiconductor device is increased, so that the degree of freedom in design and material selection is increased, resulting in a reduction in size and cost. There is also an effect that can be done.

実施の形態２．
図４は、本発明に係る半導体装置の実施の形態２を示す平面図である。
上記実施の形態１では、ネジ止め部９の二方を包むような切り欠きを、絶縁シートの短辺に設けたが、本実施の形態２では、図４に示したように、電力用半導体装置１０１のネジ止め部９の三方を包むような切り欠きを、絶縁シートの短辺に設けることにより、絶縁シートの長辺の長さＬを、ネジ止め部９の間の距離Ｄよりも大きくしたものである。 Embodiment 2. FIG.
FIG. 4 is a plan view showing a second embodiment of the semiconductor device according to the present invention.
In the first embodiment, the notches that wrap around the two sides of the screwing portion 9 are provided on the short side of the insulating sheet. However, in the second embodiment, as shown in FIG. By providing notches that wrap around three sides of the screwing portion 9 of the apparatus 101 on the short side of the insulating sheet, the length L of the long side of the insulating sheet is larger than the distance D between the screwing portions 9. It is what.

この場合、ネジ締め部９の三方を包むように、フレームを存在させることができるようになるので、さらに、ネジ止め部９の周辺の強度が向上する。   In this case, since the frame can be present so as to wrap around the three sides of the screw fastening portion 9, the strength around the screw fastening portion 9 is further improved.

実施の形態３．
図５は、本発明に係る半導体装置の実施の形態３を示す平面図である。
図５に示したように、本実施の形態３では、電力用半導体装置１０２のネジ止め部８の三方を包むような切り欠きを、絶縁シートの短辺に設けることにより、絶縁シートの長辺長さＬを、ネジ止め部９の間の距離Ｄよりも大きくし、さらに、絶縁シートに設けた切り欠きを結ぶ線に対して絶縁シートを対称形にしたものである。 Embodiment 3 FIG.
FIG. 5 is a plan view showing a third embodiment of the semiconductor device according to the present invention.
As shown in FIG. 5, in the third embodiment, a long side of the insulating sheet is provided by providing notches that wrap around three sides of the screwing portion 8 of the power semiconductor device 102 on the short side of the insulating sheet. The length L is made larger than the distance D between the screwing portions 9, and the insulating sheet is made symmetrical with respect to a line connecting notches provided in the insulating sheet.

この場合、絶縁シートが切り欠きを結ぶ線に対して対称形であるので、半導体装置１０２の製造時において、絶縁シートの設置方向に対する方向性がなくなるため、製造が容易になるという効果がある。   In this case, since the insulating sheet is symmetrical with respect to the line connecting the notches, there is no directivity with respect to the installation direction of the insulating sheet when the semiconductor device 102 is manufactured.

なお、上記実施の形態１ないし３において、パワーチップ、ＩＣチップは、それぞれ１個でも複数個でもよい。   In the first to third embodiments, one or more power chips and IC chips may be used.

また、パワーチップ及びＩＣチップのフレームへの接合材は、はんだに限られるものではなく、銀ペーストでもよい。また、アルミワイヤや金ワイヤは、材料を特定するものではない。例えば、アルミニウムや金を主成分とする合金や、銅等のアルミニウムや金以外の金属からなるワイヤでも良い。   Further, the bonding material to the power chip and IC chip frame is not limited to solder, but may be silver paste. In addition, the aluminum wire and the gold wire do not specify the material. For example, an alloy mainly composed of aluminum or gold, or a wire made of metal other than aluminum or gold such as copper may be used.

また、ワイヤボンディングに代えて、金属板を用いた電気的接続としてもよい。
ＩＣチップとパワーチップ間を、直接金属ワイヤや金属板で接続してもよい。 Further, instead of wire bonding, electrical connection using a metal plate may be used.
The IC chip and the power chip may be directly connected by a metal wire or a metal plate.

絶縁シートの絶縁材料としては、エポキシ樹脂に無機フィラーを混ぜたものを例示したが、これに限られるものではなく、モールド樹脂よりも熱伝導率が高く絶縁性を有する材料であって、機能を満足するものであればよい。例えば、絶縁シートの絶縁部が多層構造になっていても良い。具体的には、固着層と絶縁確保層との多層構造であって、固着層としては接着剤やＢステージ樹脂、絶縁確保層としてはＣステージ樹脂やセラミック板、あるいはそれらの組み合わせなどであってもよい。   The insulating material of the insulating sheet is exemplified by an epoxy resin mixed with an inorganic filler, but is not limited to this, and is a material having a higher thermal conductivity than a mold resin and having an insulating property. If it is satisfactory. For example, the insulating part of the insulating sheet may have a multilayer structure. Specifically, it has a multilayer structure of a fixing layer and an insulation ensuring layer, and the fixing layer is an adhesive or B stage resin, the insulation ensuring layer is a C stage resin, a ceramic plate, or a combination thereof. Also good.

本発明に係る半導体装置は、電力用等に有効に利用することができる。   The semiconductor device according to the present invention can be effectively used for electric power.

本発明に係る半導体装置の実施の形態１を示す断面図である。It is sectional drawing which shows Embodiment 1 of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の実施の形態１を示す平面図である。1 is a plan view showing a first embodiment of a semiconductor device according to the present invention. 半導体装置をネジ止め部を用いて冷却用ヒートシンクに組みつけた状況を示す断面図である。It is sectional drawing which shows the condition which assembled | attached the semiconductor device to the heat sink for cooling using the screwing part. 本発明に係る半導体装置の実施の形態２を示す平面図である。It is a top view which shows Embodiment 2 of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の実施の形態３を示す平面図である。It is a top view which shows Embodiment 3 of the semiconductor device which concerns on this invention.

符号の説明Explanation of symbols

１ フレーム、１ａ ダイパッド、２ パワーチップ、３ ＩＣチップ、
４ アルミワイヤ、５ 金ワイヤ、６ モールド樹脂、７ 絶縁シート、８ 銅箔、
９ ネジ止め部、２１ リード端子、２２ ヒートシンク、２３ 放熱グリース、
１００，１０２，１０２ 半導体装置。 1 frame, 1a die pad, 2 power chip, 3 IC chip,
4 Aluminum wire, 5 Gold wire, 6 Mold resin, 7 Insulating sheet, 8 Copper foil,
9 Screw fixing part, 21 Lead terminal, 22 Heat sink, 23 Thermal grease,
100, 102, 102 Semiconductor device.

Claims (5)

パワーチップへの入出力用リード端子とＩＣチップへの入出力用リード端子とを対向する辺に有する金属からなるフレームと、
上記フレームのパワーチップ搭載部の第１面に搭載されたパワーチップと、
上記フレームのＩＣチップ搭載部の第１面に搭載されたＩＣチップと、
上記パワーチップ搭載部の第１面と対向する第２面側に設置され、上記入出力用リード端子が並ぶ方向に長辺を有する矩形状で絶縁性の絶縁シートと、
上記リード端子を突出させ、上記絶縁シートの一面を外表面に露出させ、かつ、少なくとも上記ＩＣチップ及びパワーチップを封止し、上記絶縁シートよりも熱伝導率の小さな封止樹脂と、
上記封止樹脂をネジ止め固定するために、上記パワーチップへの入出力用リード端子とＩＣチップへの入出力用リード端子とが対向する方向と直交する方向の上記封止樹脂の両端部近傍に設けられたネジ止め部とを含む半導体装置において、
上記絶縁シートに、上記ネジ止め部を二方または三方から包むように切り欠き部が形成され、上記絶縁シートの長辺の長さが上記ネジ止め部の間の距離より長くなっていることを特徴とする半導体装置。 A metal frame having input / output lead terminals to the power chip and input / output lead terminals to the IC chip on opposite sides;
A power chip mounted on the first surface of the power chip mounting portion of the frame;
An IC chip mounted on the first surface of the IC chip mounting portion of the frame;
A rectangular insulating insulating sheet installed on the second surface side facing the first surface of the power chip mounting portion and having long sides in the direction in which the input / output lead terminals are arranged;
The lead terminal protrudes, one surface of the insulating sheet is exposed on the outer surface, and at least the IC chip and the power chip are sealed, and a sealing resin having a lower thermal conductivity than the insulating sheet;
Near both ends of the sealing resin in a direction orthogonal to the direction in which the input / output lead terminals to the power chip and the input / output lead terminals to the IC chip face each other in order to fix the sealing resin with screws. In a semiconductor device including a screwing portion provided in
The insulating sheet is formed with a notch so as to wrap the screwing part from two or three sides, and the length of the long side of the insulating sheet is longer than the distance between the screwing parts. A semiconductor device. 上記切り欠き部が、二方から上記ネジ止め部を包むように、上記ＩＣチップへの入出力用リード端子側の長辺の両端に形成されたことを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the notch is formed at both ends of the long side on the input / output lead terminal side to the IC chip so as to wrap the screwing portion from two sides. 上記切り欠き部は三方から上記ネジ止め部を包むように長辺方向の両端に形成されていることを特徴とする請求項１の半導体装置。 2. The semiconductor device according to claim 1, wherein the notch is formed at both ends in the long side direction so as to wrap the screwing portion from three directions. 上記絶縁シートは、上記切り欠き部の中心間を結ぶ線に対して対称形になっていることを特徴とする請求項３記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the insulating sheet is symmetrical with respect to a line connecting the centers of the notches. 上記パワーチップへの入出力用リード端子と上記ＩＣチップへの入出力用リード端子とが対向する方向と直交する方向において、上記ネジ止め部の間よりも外側の範囲に、上記パワーチップ搭載部を設置したことを特徴とする請求項１記載の半導体装置。 In the direction perpendicular to the direction in which the input / output lead terminals to the power chip and the input / output lead terminals to the IC chip face each other, the power chip mounting portion is located outside the space between the screwing portions. The semiconductor device according to claim 1, wherein:
JP2005357172A 2005-12-12 2005-12-12 Semiconductor device Pending JP2007165426A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009059923A (en) * 2007-08-31 2009-03-19 Mitsubishi Electric Corp Semiconductor device
DE102012104377A1 (en) 2011-05-30 2012-12-06 Denso Corporation Semiconductor device and drive device comprising a semiconductor device
WO2013061183A1 (en) 2011-09-27 2013-05-02 Rupprecht Gabriel Molded electrically insulating housing for semiconductor components or assemblies and production method
DE102014109515A1 (en) 2013-08-02 2015-02-05 Denso Corporation Semiconductor device to be attached to a heat radiating element
DE102014111930A1 (en) 2014-08-20 2016-02-25 Rupprecht Gabriel Thermally highly conductive, electrically insulating housing with electronic components and manufacturing processes
JP7237258B1 (en) * 2022-07-07 2023-03-10 三菱電機株式会社 Semiconductor equipment and power conversion equipment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206365A (en) * 1992-01-30 1993-08-13 Fuji Electric Co Ltd Semiconductor device and its lead frame for assembling
JP2002043496A (en) * 2000-07-21 2002-02-08 Hitachi Ltd Semiconductor device
JP2002083927A (en) * 2000-09-07 2002-03-22 Matsushita Electric Ind Co Ltd Semiconductor device
JP2005109100A (en) * 2003-09-30 2005-04-21 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206365A (en) * 1992-01-30 1993-08-13 Fuji Electric Co Ltd Semiconductor device and its lead frame for assembling
JP2002043496A (en) * 2000-07-21 2002-02-08 Hitachi Ltd Semiconductor device
JP2002083927A (en) * 2000-09-07 2002-03-22 Matsushita Electric Ind Co Ltd Semiconductor device
JP2005109100A (en) * 2003-09-30 2005-04-21 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009059923A (en) * 2007-08-31 2009-03-19 Mitsubishi Electric Corp Semiconductor device
DE102012104377A1 (en) 2011-05-30 2012-12-06 Denso Corporation Semiconductor device and drive device comprising a semiconductor device
US8680726B2 (en) 2011-05-30 2014-03-25 Denso Corporation Semiconductor device and driving apparatus including semiconductor device
WO2013061183A1 (en) 2011-09-27 2013-05-02 Rupprecht Gabriel Molded electrically insulating housing for semiconductor components or assemblies and production method
DE102014109515A1 (en) 2013-08-02 2015-02-05 Denso Corporation Semiconductor device to be attached to a heat radiating element
US9196561B2 (en) 2013-08-02 2015-11-24 Denso Corporation Semiconductor device to be attached to heat radiation member
DE102014111930A1 (en) 2014-08-20 2016-02-25 Rupprecht Gabriel Thermally highly conductive, electrically insulating housing with electronic components and manufacturing processes
JP7237258B1 (en) * 2022-07-07 2023-03-10 三菱電機株式会社 Semiconductor equipment and power conversion equipment
WO2024009458A1 (en) * 2022-07-07 2024-01-11 三菱電機株式会社 Semiconductor device and power converter

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