JP2002083927A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2002083927A JP2002083927A JP2000272194A JP2000272194A JP2002083927A JP 2002083927 A JP2002083927 A JP 2002083927A JP 2000272194 A JP2000272194 A JP 2000272194A JP 2000272194 A JP2000272194 A JP 2000272194A JP 2002083927 A JP2002083927 A JP 2002083927A
- Authority
- JP
- Japan
- Prior art keywords
- power switching
- semiconductor device
- semiconductor
- switching element
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01037—Rubidium [Rb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、モータ、照明等の駆動用に用いられる出力用
半導体素子（スイッチング素子）及びその制御用の半導
体素子を同一パッケージ内に内蔵した樹脂封止型半導体
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a resin in which an output semiconductor element (switching element) used for driving a motor, lighting, and the like and a semiconductor element for controlling the same are housed in the same package. The present invention relates to a sealed semiconductor device.
【０００２】[0002]
【従来の技術】モータ等の駆動用に用いられる出力用半
導体素子（電力スイッチング素子）及びその制御用半導
体素子（制御素子）はそれぞれ、図１０及び図１１のよ
うな樹脂封止パッケージに搭載されて、モータ駆動回路
や照明回路等に使用されていた。2. Description of the Related Art An output semiconductor element (power switching element) and a control semiconductor element (control element) used for driving a motor or the like are mounted on a resin-sealed package as shown in FIGS. 10 and 11, respectively. Thus, they have been used in motor drive circuits, lighting circuits, and the like.
【０００３】図１０（ａ）は電力スイッチング用半導体
装置の外観平面図であり、３は外部装置との接続リード
部、５は封止樹脂を示す。封止樹脂５が付設される前の
状態を、図１０（ｂ）に示す。図１０（ｂ）において、
１０は電力スイッチング素子であり、金属細線１２によ
り接続リード部３と接続されている。電力スイッチング
素子１０としては、ＩＧＢＴ（絶縁ゲート型バイポーラ
トランジスタ）やパワーＭＯＳＦＥＴ（金属酸化型電界
効果トランジスタ）等が用いられる。FIG. 10A is an external plan view of a power switching semiconductor device, in which reference numeral 3 denotes a connection lead portion with an external device, and reference numeral 5 denotes a sealing resin. FIG. 10B shows a state before the sealing resin 5 is attached. In FIG. 10B,
Reference numeral 10 denotes a power switching element, which is connected to the connection lead 3 by a thin metal wire 12. As the power switching element 10, an IGBT (insulated gate bipolar transistor), a power MOSFET (metal oxide field effect transistor), or the like is used.
【０００４】図１１（ａ）は、図１０に示す電力スイッ
チング素子を制御するための制御用半導体装置（ＩＣ）
の外観平面図であり、３は外部装置との接続リード部、
５は封止樹脂を示す。封止樹脂５が付設される前の状態
を、図１１（ｂ）に示す。１１は制御素子であり、金属
細線１２により接続リード部３と接続されている。FIG. 11A shows a control semiconductor device (IC) for controlling the power switching element shown in FIG.
FIG. 3 is an external plan view of the device, 3 is a connection lead portion with an external device,
Reference numeral 5 denotes a sealing resin. FIG. 11B shows a state before the sealing resin 5 is attached. Reference numeral 11 denotes a control element, which is connected to the connection lead 3 by a thin metal wire 12.
【０００５】また、他の従来例として、図１２に示すよ
うに、電力スイッチング素子及びその制御素子が絶縁金
属基板を用いた一体型モジュールに搭載されたものがあ
る。As another conventional example, as shown in FIG. 12, a power switching element and its control element are mounted on an integrated module using an insulating metal substrate.
【０００６】図１２（ａ）は、絶縁金属基板を用いた一
体型モジュールの構成を示す外観平面図であり、図１２
（ｂ）は、図１２（ａ）の一体型モジュールを線分Ａ−
Ａ’に沿って切断した断面図である。FIG. 12A is an external plan view showing the structure of an integrated module using an insulating metal substrate.
FIG. 12B shows the integrated module of FIG.
It is sectional drawing cut | disconnected along A '.
【０００７】かかる一体型モジュールでは、外部装置に
取り付けるための取付け穴４を有した金属板６上に絶縁
膜７を形成し、その上に選択的に銅板８を形成した絶縁
金属基板を用いていた。このような絶縁金属基板に、電
力スイッチング素子１０と電力スイッチング素子１０を
制御するための制御素子１１を半田９にて銅板８に接着
し、その後、電力スイッチング素子１０と制御素子１１
を外部装置に接続するためのリード部３に金線等の金属
細線で配線し、しかるのち、樹脂ケース５にてパッケー
ジングしていた。[0007] Such an integrated module uses an insulating metal substrate in which an insulating film 7 is formed on a metal plate 6 having a mounting hole 4 for mounting to an external device, and a copper plate 8 is selectively formed thereon. Was. A power switching element 10 and a control element 11 for controlling the power switching element 10 are bonded to the copper plate 8 by solder 9 on such an insulated metal substrate, and then the power switching element 10 and the control element 11
Is wired with a thin metal wire such as a gold wire to a lead portion 3 for connecting to an external device, and then packaged in a resin case 5.
【０００８】次に、図１０及び図１１に示すような単体
の半導体装置、もしくは図１２に示すような一体型モジ
ュールを用いたモータの駆動制御について説明する。Next, the drive control of a motor using a single semiconductor device as shown in FIGS. 10 and 11 or an integrated module as shown in FIG. 12 will be described.
【０００９】図１３は、３相モータ駆動用インバータ回
路の構成を示す等価回路図である。FIG. 13 is an equivalent circuit diagram showing a configuration of an inverter circuit for driving a three-phase motor.
【００１０】図１３において、７１は３相モータ、７２
−１〜７２−６は電力スイッチング素子であるパワーＭ
ＯＳＦＥＴであり、パワーＭＯＳＦＥＴ７２−１と７２
−２の対、パワーＭＯＳＦＥＴ７２−３と７２−４の
対、およびパワーＭＯＳＦＥＴ７２−５と７２−６の対
として３対配置されている。７３−１〜７３−３は制御
ＩＣであり、それぞれ、７２−１と７２−２の対、パワ
ーＭＯＳＦＥＴ７２−３と７２−４の対、およびパワー
ＭＯＳＦＥＴ７２−５と７２−６の対のそれぞれを制御
するように３個配置されている。In FIG. 13, reference numeral 71 denotes a three-phase motor;
-1 to 72-6 are power M which is a power switching element.
OSFETs and power MOSFETs 72-1 and 72-1
2 pairs, a pair of power MOSFETs 72-3 and 72-4, and a pair of power MOSFETs 72-5 and 72-6. 73-1 to 73-3 are control ICs, each of which controls a pair of 72-1 and 72-2, a pair of power MOSFETs 72-3 and 72-4, and a pair of power MOSFETs 72-5 and 72-6. Three are arranged to control.
【００１１】３対のパワーＭＯＳＦＥＴは出力段回路を
構成し、調整した電力を負荷である３相モータ７１に出
力する。各対における高圧側のパワーＭＯＳＦＥＴ７２
−１、７２−３、７２−５のドレイン端子に対して、そ
れぞれ直流の高電位Ｖｐが印加され、各対における低圧
側のパワーＭＯＳＦＥＴ７２−２、７２−４、７２−６
のソース端子に対して、直流の基準電位Ｖｎが印加さ
れ、それにより出力回路に対して電力が供給される。The three pairs of power MOSFETs constitute an output stage circuit, and output the adjusted power to a three-phase motor 71 as a load. High-side power MOSFET 72 in each pair
DC high potential Vp is applied to the drain terminals of -1, 72-3, and 72-5, and the low-voltage-side power MOSFETs 72-2, 72-4, and 72-6 in each pair.
, A DC reference potential Vn is applied to the source terminal, thereby supplying power to the output circuit.
【００１２】パワーＭＯＳＦＥＴ７２−１〜７２−６
は、３相モータ７１へ供給する電流の遮断および導通を
反復して行うことで、入力された電力を３相モータ７１
の各相に対応して制御し、制御された電力を各対の出力
端子を通して３相モータ７１へ出力する。Power MOSFETs 72-1 to 72-6
Repeatedly cuts off and conducts the current supplied to the three-phase motor 71, thereby converting the input power to the three-phase motor 71.
And outputs the controlled power to the three-phase motor 71 through the output terminals of each pair.
【００１３】制御ＩＣ７３−１〜７３−３は、それぞ
れ、外部よりＨｉｎ端子、及びＬｉｎ端子に入力される
ＰＷＭ（パルス幅変調）信号に応答して、パワーＭＯＳ
ＦＥＴ７２−１と７２−２のゲート、パワーＭＯＳＦＥ
Ｔ７２−３と７２−４のゲート、およびパワーＭＯＳＦ
ＥＴ７２−５と７２−６のゲートにゲート電圧信号を送
出する。パワーＭＯＳＦＥＴ７２−１〜７２−６はこれ
らのゲート電圧信号に応答して、各ソースとドレイン間
の電流の遮断及び導通を行う。The control ICs 73-1 to 73-3 respond to a PWM (pulse width modulation) signal inputted from the outside to a Hin terminal and a Lin terminal, respectively, and respond to the power MOS.
Gates of FETs 72-1 and 72-2, power MOSFE
Gates of T72-3 and T72-3 and power MOSF
A gate voltage signal is sent to the gates of ETs 72-5 and 72-6. The power MOSFETs 72-1 to 72-6 cut off and conduct current between each source and drain in response to these gate voltage signals.
【００１４】[0014]
【発明が解決しようとする課題】しかしながら、従来の
半導体装置を用いて３相モータ駆動用インバータ回路を
構成した場合、以下のような問題点がある。However, when a conventional semiconductor device is used to form a three-phase motor driving inverter circuit, there are the following problems.
【００１５】図１０に示すような電力スイッチング用半
導体装置と図１１に示すような制御用半導体装置を用い
た場合、 （１）電力スイッチング素子（図１３のパワーＭＯＳＦ
ＥＴ７２−１〜７２−６６）及びその制御素子（図１３
の制御用ＩＣ７３−１〜７３−３）を樹脂封止型パッケ
ージに個別に実装しているため、モータ駆動用半導体装
置の小型、軽量化が困難であった。 （２）電力スイッチング素子およびその制御素子を樹脂
封止型パッケージに個別に実装しているため、パッケー
ジの材料費が高くなり、モータ駆動用や照明用の回路と
して構成した場合、製造プロセス費が高くなる。 （３）モータ駆動用半導体装置としてプリント基板に電
力スイッチング素子およびその制御素子を半田等で接着
して構成すると、各素子のパッケージ内の金属細線長、
接続リード長、プリント基板上の金属配線パターン長を
含めたゲート電極、ソース電極につながる配線ループ、
すなわちゲートループ長さが数ｍｍ以上になるため、配
線のインダクタンスＬ値が大きくなる。このため、電力
スイッチング素子（パワーＭＯＳＦＥＴやＩＧＢＴ）の
モータへの出力電流値の時間変化をｄｉ／ｄｔとする
と、誘起電圧として大きさがＬ×（ｄｉ／ｄｔ）のノイ
ズ電圧がゲート端子とソース端子間に発生して電力スイ
ッチング素子が誤動作するおそれがある。さらに、外部
からのノイズも、配線ループのＬ値が大きい程大きなノ
イズとなって、電力スイッチング素子の誤動作の要因と
なる。When a power switching semiconductor device as shown in FIG. 10 and a control semiconductor device as shown in FIG. 11 are used, (1) a power switching element (the power MOSFET shown in FIG. 13)
ET 72-1 to 72-66) and its control element (FIG. 13)
Since the control ICs 73-1 to 73-3) are individually mounted in a resin-sealed package, it has been difficult to reduce the size and weight of the motor driving semiconductor device. (2) Since the power switching element and its control element are individually mounted in the resin-encapsulated package, the material cost of the package increases, and if the circuit is configured as a motor drive or lighting circuit, the manufacturing process cost is reduced. Get higher. (3) When a power switching element and its control element are bonded to a printed circuit board by soldering or the like as a motor driving semiconductor device, the length of a thin metal wire in a package of each element can be reduced.
Wiring loops connected to the gate electrode and source electrode, including the connection lead length, metal wiring pattern length on the printed circuit board,
That is, since the gate loop length becomes several mm or more, the inductance L value of the wiring increases. Therefore, assuming that the time change of the output current value of the power switching element (power MOSFET or IGBT) to the motor is di / dt, a noise voltage of magnitude L × (di / dt) is generated as the induced voltage by the gate terminal and the source. The power switching element may malfunction between terminals. Further, external noise also becomes larger as the L value of the wiring loop becomes larger, and causes a malfunction of the power switching element.
【００１６】また、図１２に示すような絶縁金属基板を
有する一体型モジュールを用いた場合には、 （１）絶縁金属基板を用いた一体型モジュールでは、電
力スイッチング素子の駆動時に発生した熱を銅板、絶縁
膜を介して例えばアルミ板等の金属板に放熱している。
また、電力スイッチング素子搭載部、制御素子搭載部、
および素子間配線部には銅板を使用し、放熱板である金
属基板にはアルミ板を使用しているため、高価な金属板
が２種類必要となる。また、アルミ板には、銅板や、外
部との接続を行うためのリード搭載部、樹脂ケース等を
搭載するため、面積が大きくなり、低コスト化が困難で
あった。 （２）電力スイッチング素子の駆動時に発生した熱は、
銅板、絶縁膜を介してアルミ板に放熱し、アルミ板に伝
わった熱は、外部装置への取付け穴によって取り付けら
れた装置の放熱板に伝わるが、モジュール内の取付け穴
は、電力スイッチング素子を搭載している銅板とは絶縁
膜を介しての接触であり、かつ、締め付け部とは離れて
いるため、放熱効果が少なく、絶縁金属基板のアルミ板
を厚くしたり、広くする必要があるというような問題が
あった。When an integrated module having an insulated metal substrate as shown in FIG. 12 is used, (1) In an integrated module using an insulated metal substrate, heat generated when the power switching element is driven is reduced. Heat is radiated to a metal plate such as an aluminum plate via a copper plate and an insulating film.
In addition, the power switching element mounting section, the control element mounting section,
In addition, since a copper plate is used for the inter-element wiring portion and an aluminum plate is used for the metal substrate serving as a heat radiating plate, two types of expensive metal plates are required. Further, since the aluminum plate is mounted with a copper plate, a lead mounting portion for connection with the outside, a resin case, and the like, the area is increased, and it has been difficult to reduce the cost. (2) The heat generated when driving the power switching element is:
Heat is radiated to the aluminum plate via the copper plate and insulating film, and the heat transmitted to the aluminum plate is transmitted to the heat radiating plate of the device installed by the mounting hole to the external device, but the mounting hole in the module is used for the power switching element. It is said that the mounted copper plate is in contact via the insulating film and is away from the tightening part, so there is little heat dissipation effect, and it is necessary to make the aluminum plate of the insulating metal substrate thicker or wider There was such a problem.
【００１７】本発明は、上記の問題点に鑑みてなされた
ものであり、その目的は、電力スイッチング素子と制御
素子を１つの樹脂パッケージに内蔵し、小型、軽量、低
価格化を可能にするとともに、ノイズによる誤動作を低
減した半導体装置を提供することにある。The present invention has been made in view of the above problems, and an object of the present invention is to incorporate a power switching element and a control element in a single resin package, thereby enabling a reduction in size, weight, and cost. Another object of the present invention is to provide a semiconductor device in which malfunction due to noise is reduced.
【００１８】また、本発明の他の目的は、電力スイッチ
ング素子と制御素子を１つの樹脂パッケージに内蔵した
際に生じる、高電力を扱う電力スイッチング素子による
発熱の影響を軽減することにある。It is another object of the present invention to reduce the influence of heat generated by a power switching element that handles high power when the power switching element and the control element are incorporated in one resin package.
【００１９】[0019]
【課題を解決するための手段】前記の目的を達成するた
め、本発明に係る半導体装置は、リードフレームに搭載
された複数の半導体素子が樹脂パッケージ内に封止され
た半導体装置であって、リードフレームは、第１半導体
素子が搭載される第１素子搭載部、および第１素子搭載
部の一端に形成され、外部との電気的な接続を行うため
の第１外部リードを有する第１金属板と、第１半導体素
子よりも小さな電力で動作する第２半導体素子が搭載さ
れる第２素子搭載部、および第２素子搭載部の一端に形
成され、外部との電気的な接続を行うための第２外部リ
ードを有する第２金属板とを備え、第１金属板は、半導
体装置を外部装置に取り付けるために、第１素子搭載部
と第１外部リードとの間に設けられた取付け穴を有する
ことを特徴とする。In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which a plurality of semiconductor elements mounted on a lead frame are sealed in a resin package, The lead frame includes a first element mounting portion on which the first semiconductor element is mounted, and a first metal formed at one end of the first element mounting portion and having a first external lead for making an electrical connection to the outside. A plate, a second element mounting portion on which a second semiconductor element that operates with less power than the first semiconductor element is mounted, and one end of the second element mounting portion for electrically connecting to the outside. A second metal plate having a second external lead, wherein the first metal plate has a mounting hole provided between the first element mounting portion and the first external lead for mounting the semiconductor device to the external device. Characterized by having
【００２０】この半導体装置において、第１半導体素子
は電力スイッチング素子であり、第２半導体素子は前記
電力スイッチング素子の駆動を制御するための制御素子
である。In this semiconductor device, the first semiconductor element is a power switching element, and the second semiconductor element is a control element for controlling driving of the power switching element.
【００２１】また、第１外部リードは複数の外部リード
からなることが好ましい。Further, it is preferable that the first external lead comprises a plurality of external leads.
【００２２】また、樹脂パッケージの封止樹脂は、第１
および第２半導体素子が搭載されるリードフレームの表
面側およびその裏面側の両方に形成され、４０×１０-4
ｃａｌ／ｓｅｃ・ｃｍ・℃以上の熱伝導率を有し、裏面
側における樹脂パッケージの厚みが５０μｍから６００
μｍであり、かつ、第１金属板に設けられた前記取付け
穴と同心で、前記取付け穴の半径よりも５０μｍから６
００μｍだけ小さい半径を有する貫通孔が設けられるこ
とが好ましい。Also, the sealing resin of the resin package is
And 40 × 10 −4 formed on both the front side and the back side of the lead frame on which the second semiconductor element is mounted.
cal / sec · cm · ° C. or higher, and the thickness of the resin package on the back side is 50 μm to 600 μm.
μm, and concentric with the mounting hole provided in the first metal plate, and having a diameter of 50 μm to 6
Preferably, a through hole having a radius smaller by 00 μm is provided.
【００２３】上記の構成によれば、従来の電力スイッチ
ング素子と制御素子を個別の単体パッケージでインバー
タ回路構成したものに比べ、容易に、電力スイッチング
素子と制御素子を一体型樹脂封止パッケージ内に搭載す
ることができ、半導体装置の小型、軽量化が可能にな
る。According to the above configuration, the power switching element and the control element can be easily housed in an integrated resin-sealed package as compared with the conventional power switching element and the control element which are configured as an inverter circuit in separate single packages. The semiconductor device can be mounted, and the size and weight of the semiconductor device can be reduced.
【００２４】また、一体型パッケージに搭載すること
で、パッケージの材料費や製造プロセス費が安価にな
る。Further, by mounting the package on an integrated package, material costs of the package and manufacturing process costs are reduced.
【００２５】また、従来の絶縁金属基板を用いた一体型
モジュールに比べ、電力スイッチング素子を駆動した場
合に発生する熱は、電力スイッチング素子搭載部（第１
素子搭載部）と第１外部リードとの間に設けられた取付
け穴、樹脂パッケージの貫通孔、および固定部材を介し
て外部装置へと放散され、放熱効果を向上させることが
できる。In addition, as compared with a conventional integrated module using an insulated metal substrate, the heat generated when the power switching element is driven is reduced by the power switching element mounting portion (first
The heat is radiated to an external device via a mounting hole provided between the element mounting portion) and the first external lead, a through hole of the resin package, and a fixing member, so that a heat radiation effect can be improved.
【００２６】また、電力スイッチング素子搭載部と第１
外部リードが第１金属板に一体成型されていることか
ら、スイッチング素子搭載部の有効面積が増大し、よ
り、放熱効果を上げることか可能となる。The power switching element mounting portion and the first
Since the external leads are integrally molded with the first metal plate, the effective area of the switching element mounting portion is increased, and it is possible to further enhance the heat radiation effect.
【００２７】また、一体型樹脂封止パッケージの実現に
より、電力スイッチング素子と制御素子、電力スイッチ
ング素子と外部リード、および制御素子と外部リードを
接続するための金属細線の接続距離を最小限にすること
ができ、材料費の削減や製造プロセスの簡素化が図れ
る。Further, by realizing the integrated resin-sealed package, the connection distance between the power switching element and the control element, the power switching element and the external lead, and the thin metal wire for connecting the control element and the external lead can be minimized. As a result, material costs can be reduced and the manufacturing process can be simplified.
【００２８】また、金属細線の距離を最小限にすること
で、電力スイッチング素子と制御素子の配線ループ長
（ゲートループ長）が最小になるため、配線のインダク
タンス値が最小になり、ノイズの影響が低減でき、スイ
ッチ素子の誤動作を防止することができる。Also, by minimizing the distance between the thin metal wires, the wiring loop length (gate loop length) of the power switching element and the control element is minimized, so that the inductance value of the wiring is minimized and the influence of noise is reduced. Can be reduced, and malfunction of the switch element can be prevented.
【００２９】さらに、金属細線の距離を最小限にするこ
とで、金属細線の変形も小さくすることが可能になり、
完成品の環境試験、特に、熱衝撃テスト等の信頼性レベ
ルの向上も図ることができる。Further, by minimizing the distance between the thin metal wires, it is possible to reduce the deformation of the thin metal wires.
It is also possible to improve the reliability level of the completed product in environmental tests, particularly in thermal shock tests and the like.
【００３０】[0030]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００３１】（第１実施形態）図１は、本発明の第１実
施形態による半導体装置の構成を示す外観平面図で、図
１（ａ）は樹脂パッケージが形成された後、図１（ｂ）
は樹脂パッケージが形成される前の状態を示す。また、
図２は、図１の半導体装置の等価回路図である。(First Embodiment) FIG. 1 is an external plan view showing the structure of a semiconductor device according to a first embodiment of the present invention. FIG. 1A shows a state after a resin package is formed. )
Indicates a state before the resin package is formed. Also,
FIG. 2 is an equivalent circuit diagram of the semiconductor device of FIG.
【００３２】図１（ａ）において、３は外部との電気的
な接続を行うための複数の外部リード、５は樹脂パッケ
ージ、４−１、４−２は半導体装置を外部装置に取り付
けるための樹脂パッケージ５の貫通孔を示す。In FIG. 1A, reference numeral 3 denotes a plurality of external leads for making an electrical connection to the outside, 5 denotes a resin package, and 4-1 and 4-2 denote a semiconductor device mounted on the external device. 2 shows a through hole of the resin package 5.
【００３３】図１（ｂ）において、リードフレームは、
樹脂パッケージ５内において、２つの電力スイッチング
素子１０−１、１０−２がそれぞれ搭載される電力スイ
ッチング素子搭載部１−１、１−２（第１素子搭載
部）、および電力スイッチング素子搭載部１−１、１−
２のそれぞれと一体に形成された外部リード３−１、３
−２（第１外部リード）を有する２つの金属板１３−
１、１３−２（第１金属板）と、電力スイッチング素子
１０−１、１０−２を制御する制御素子１１が搭載され
る制御素子搭載部２（第２素子搭載部）、および制御素
子搭載部２と一体に形成された外部リード３−３（第２
外部リード）を有する金属板１３−３（第２金属板）と
を含む複数の金属板からなる。In FIG. 1B, the lead frame is
In the resin package 5, the power switching element mounting sections 1-1 and 1-2 (first element mounting section) on which the two power switching elements 10-1 and 10-2 are mounted, respectively, and the power switching element mounting section 1 -1, 1-
2 and external leads 3-1 and 3 formed integrally with each other.
-2 (first external leads) two metal plates 13-
1, 13-2 (first metal plate), control element mounting section 2 (second element mounting section) on which control elements 11 for controlling power switching elements 10-1, 10-2 are mounted, and control element mounting The external lead 3-3 (the second lead) formed integrally with the portion 2
And a metal plate 13-3 (second metal plate) having external leads).
【００３４】また、電力スイッチング素子搭載部１−
１、１−２をそれぞれ有する金属板１３−１、１３−２
には、半導体装置を外部装置に取り付け、電力スイッチ
ング素子１０−１、１０−２により発生する熱を放散さ
せるための取付け穴１４−１、１４−２が設けられてい
る。The power switching element mounting section 1-
Metal plates 13-1 and 13-2 each having 1, 1-2
Are provided with mounting holes 14-1 and 14-2 for attaching the semiconductor device to an external device and dissipating heat generated by the power switching elements 10-1 and 10-2.
【００３５】電力スイッチング素子１０−１、１０−２
としては、パワーＭＯＳＦＥＴやＩＧＢＴ等が用いられ
る。各素子と外部リード３、あるいは各素子間は、図２
に示す回路構成となるようにＡｕ等からなる金属細線１
２により配線されている。Power switching elements 10-1 and 10-2
For example, a power MOSFET, IGBT, or the like is used. FIG. 2 shows each element and external lead 3 or between each element.
Metal wire 1 made of Au or the like so as to have the circuit configuration shown in FIG.
2 are wired.
【００３６】９−１、９−２は電力スイッチング素子接
着用半田であり、電力スイッチング素子１０−１、１０
−２は、接着面側がドレイン電極になっており、各ドレ
イン電極は、半田９−１、９−２により外部リード３−
１（Ｖｐ）、３−２（Ｖｏ）とそれぞれ接続されてい
る。また、２つの電力スイッチング素子１０−１、１０
−２は、電力スイッチング素子１０−１のソース電極が
電力スイッチング素子１０−２のドレイン電極であるＶ
ｏに金線で接続されたトーテムポール接続構造を有して
いる。Reference numerals 9-1 and 9-2 denote solder for bonding the power switching elements, and the power switching elements 10-1 and 10-2.
-2, the adhesive surface side is a drain electrode, and each drain electrode is connected to an external lead 3 by solder 9-1 and 9-2.
1 (Vp) and 3-2 (Vo). Also, two power switching elements 10-1, 10
-2, V indicates that the source electrode of the power switching element 10-1 is the drain electrode of the power switching element 10-2.
o has a totem pole connection structure connected by a gold wire.
【００３７】図３は、本実施形態による半導体装置の各
製造工程を示す平面図である。FIG. 3 is a plan view showing the steps of manufacturing the semiconductor device according to the present embodiment.
【００３８】まず、図３（ａ）に示すようなリードフレ
ームを準備する。このリードフレームは、例えば厚さ
０．５ｍｍの銅板からプレス成型により形成され、電力
スイッチング素子搭載部１−１、１−２、制御素子搭載
部２、および複数の外部リード３からなる。また、リー
ドフレームには、電力スイッチング素子搭載部１−１、
１−２と外部リード３−１、３−２との間にそれぞれ取
付け穴１４−１、１４−２がプレス成型段階で開けられ
ている。First, a lead frame as shown in FIG. 3A is prepared. This lead frame is formed from a copper plate having a thickness of, for example, 0.5 mm by press molding, and includes power switching element mounting sections 1-1 and 1-2, a control element mounting section 2, and a plurality of external leads 3. Also, the power switching element mounting section 1-1,
Attachment holes 14-1 and 14-2 are formed in the press molding stage between 1-2 and the external leads 3-1 and 3-2, respectively.
【００３９】次に、図３（ｂ）に示すように、リードフ
レームの２つの電力スイッチング素子搭載部１−１、１
−２にそれぞれ電力スイッチング素子１０−１、１０−
２を半田９−１、９−２により接着し、１つの制御素子
搭載部２に制御素子１１を半田９−３により接着する。
その後、外部リード３と電力スイッチング素子１０−
１、１０−２、電力スイッチング素子１０−１、１０−
２と制御素子１１、外部リード３と制御素子１１とを金
属細線１２により配線する。Next, as shown in FIG. 3B, the two power switching element mounting portions 1-1, 1
-2 are the power switching elements 10-1 and 10-, respectively.
2 are bonded by solders 9-1 and 9-2, and the control element 11 is bonded to one control element mounting section 2 by solder 9-3.
Then, the external lead 3 and the power switching element 10-
1, 10-2, power switching elements 10-1, 10-
2 and the control element 11, and the external leads 3 and the control element 11 are wired by thin metal wires 12.
【００４０】ここで、電力スイッチング素子１０−１
は、その接着面側がドレイン電極になっており、半田９
−１により接着されることで、そのドレイン電極は、電
力スイッチング素子搭載部１−１と一体に形成された外
部リード３−１の駆動用電源電圧端子Ｖｐに接続され
る。また、電力スイッチング素子１０−１のソース電極
は、電力スイッチング素子搭載部１−２に接着された電
力スイッチング素子１０−２のドレイン電極に金属細線
１２を介して接続され、電力スイッチング素子搭載部１
−２と一体に形成された外部リード３−２の出力端子Ｖ
ｏに接続される。さらに、電力スイッチング素子１０−
２のソース電極は、外部リード３の駆動用基準電圧端子
Ｖｎに接続される。Here, the power switching element 10-1
Has a drain electrode on the bonding surface side, and the solder 9
By being bonded by -1, the drain electrode is connected to the drive power supply voltage terminal Vp of the external lead 3-1 formed integrally with the power switching element mounting portion 1-1. The source electrode of the power switching element 10-1 is connected to the drain electrode of the power switching element 10-2 bonded to the power switching element mounting section 1-2 via the thin metal wire 12, and the power switching element mounting section 1
-2 output terminal V of external lead 3-2 integrally formed
o. Further, the power switching element 10-
The source electrode 2 is connected to the drive reference voltage terminal Vn of the external lead 3.
【００４１】最後に、図３（ｃ）に示すように、エポキ
シ樹脂を用いた樹脂パッケージ５により、電力スイッチ
ング素子１０−１、１０−２および制御素子１１を封止
して、しかるのち、複数の外部リード３を接続している
不要な銅板を加工することで、半導体装置が完成する。Finally, as shown in FIG. 3 (c), the power switching elements 10-1 and 10-2 and the control element 11 are sealed with a resin package 5 using an epoxy resin. By processing an unnecessary copper plate to which the external leads 3 are connected, a semiconductor device is completed.
【００４２】ここで、図４に図１のＡ−Ａ’に沿った断
面図で示すように、樹脂パッケージ５は、電力スイッチ
ング素子１０−１、１０−２および制御素子１１が搭載
されるリードフレームの表面側およびその裏面側の両方
に形成され、例えば、エポキシ樹脂に結晶シリカ等を混
合することで４０×１０-4ｃａｌ／ｓｅｃ・ｃｍ・℃以
上の高い熱伝導率を有し、裏面側における樹脂パッケー
ジ５の厚みＴ１が５０μｍから６００μｍに設定され
る。また、樹脂パッケージ５には、半導体装置を外部装
置に取り付けるために固定部材用の貫通孔４−１、４−
２が設けられるが、この貫通孔４−１、４−２の半径
は、リードフレームに設けられた取付け穴１４−１、１
４−２の半径よりも５０μｍから６００μｍ（Ｔ２）だ
け小さく設定される。Here, as shown in FIG. 4 as a cross-sectional view taken along the line AA ′ of FIG. 1, the resin package 5 includes a lead on which the power switching elements 10-1 and 10-2 and the control element 11 are mounted. It is formed on both the front side and the back side of the frame, and has a high thermal conductivity of 40 × 10 −4 cal / sec · cm · ° C. or more by mixing crystalline silica or the like with an epoxy resin. The thickness T1 of the resin package 5 on the side is set from 50 μm to 600 μm. The resin package 5 has through holes 4-1 and 4- for fixing members for attaching the semiconductor device to an external device.
2 are provided, and the radii of the through holes 4-1 and 4-2 are the same as those of the mounting holes 14-1 and 14-1 provided in the lead frame.
The radius is set to be smaller than the radius of 4-2 by 50 μm to 600 μm (T2).
【００４３】これにより、電力スイッチング素子１０−
１、１０−２を動作させた際に発生する熱は、それぞ
れ、リードフレームの電力スイッチング素子搭載部１−
１、１−２から取付け穴１４−１、１４−２、樹脂パッ
ケージ５の貫通孔４−１、４−２、および固定部材（不
図示）を介して外部装置の放熱板へと、また電力スイッ
チング素子搭載部１−１、１−２と一体に形成された外
部リード３−１、３−２を介して外部装置のプリント基
板へと良好に放散させることができる。Thus, the power switching element 10-
1, 10-2 are generated by operating the power switching element mounting portion 1- 1 of the lead frame, respectively.
1, 1-2 from the mounting holes 14-1, 14-2, the through holes 4-1 and 4-2 of the resin package 5, and the fixing member (not shown) to the heat sink of the external device, Through the external leads 3-1 and 3-2 formed integrally with the switching element mounting portions 1-1 and 1-2, the radiation can be satisfactorily radiated to the printed circuit board of the external device.
【００４４】次に、このように構成された半導体装置の
動作について、図５を用いて説明する。Next, the operation of the semiconductor device thus configured will be described with reference to FIG.
【００４５】図５は、本実施形態による半導体装置をモ
ータ駆動用インバータ回路に用いた場合の等価回路図で
ある。図５において、３相モータ７１のＵ相、Ｖ相、Ｗ
相端子はそれぞれ半導体装置１５−１、１５−２、１５
−３のＶｏ端子に接続されている。FIG. 5 is an equivalent circuit diagram when the semiconductor device according to the present embodiment is used in a motor driving inverter circuit. In FIG. 5, the U-phase, V-phase and W-phase of the three-phase motor 71 are shown.
The phase terminals are respectively semiconductor devices 15-1, 15-2, 15
-3 Vo terminal.
【００４６】まず、各半導体装置１５−１〜１５−３の
Ｖｃｃ端子とＧｎｄ端子間に制御用電圧Ｖａを印加した
後、各ＶＢ端子と各Ｖｏ端子間にも、制御用電圧Ｖａと
は基準電位の異なる電圧レベルの制御用電圧Ｖｂを印加
する。First, after a control voltage Va is applied between the Vcc terminal and the Gnd terminal of each of the semiconductor devices 15-1 to 15-3, the control voltage Va is also applied between each VB terminal and each Vo terminal. Control voltages Vb of different voltage levels are applied.
【００４７】次に、Ｖｐ端子とＶｎ端子間に３相モータ
７１を駆動するための駆動用主電源電圧を印加する。Next, a driving main power supply voltage for driving the three-phase motor 71 is applied between the Vp terminal and the Vn terminal.
【００４８】次に、外部のマイクロコンピュータ（不図
示）等より、各半導体装置１５−１〜１５−３のＨｉｎ
とＬｉｎ端子にＰＷＭ制御信号を送信することで、ＰＷ
Ｍ制御信号に従って各半導体装置１５−１〜１５−３の
Ｖｏ端子の電位が変化して、３相モータ７１のＵ相、Ｖ
相、Ｗ相に流れる電流が制御され、３相モータ７１を所
定通りに駆動制御することができる。Next, Hin of each of the semiconductor devices 15-1 to 15-3 is supplied from an external microcomputer (not shown) or the like.
And the PWM control signal to the Lin terminal,
The potential of the Vo terminal of each of the semiconductor devices 15-1 to 15-3 changes according to the M control signal, and the U-phase and V-phase of the three-phase motor 71 change.
The current flowing in the phase and the W phase is controlled, so that the drive of the three-phase motor 71 can be controlled as predetermined.
【００４９】ここで、上記したように、樹脂パッケージ
５に４０×１０-4ｃａｌ／ｓｅｃ・ｃｍ・℃以上の熱伝
導率が必要である理由について述べる。Here, as described above, the reason why the resin package 5 needs a thermal conductivity of 40 × 10 −4 cal / sec · cm · ° C. or more will be described.
【００５０】図５に示すインバータ回路により、例えば
３００Ｗの３相モータ７１をインバータ変換効率９０％
で駆動した場合、３０Ｗの損失（Ｐｒｏｓｓ）が発生す
る。また、システムの周囲温度の最大値（Ｔａｍａｘ）
を６０℃とした場合、半導体素子の接合温度の動作上限
値（Ｔｊｍａｘ）は通常１５０℃であるため、半導体素
子が動作しうる最大昇温値（ΔＴｍａｘ）は９０ｄｅｇ
となる。よって、樹脂パッケージ５に必要とされる熱抵
抗の上限値は、ΔＴｍａｘ／Ｐｒｏｓｓ＝３．０℃／Ｗ
となり、この熱抵抗の上限値３．０℃／Ｗに相当する熱
伝導率が、図６に示す熱抵抗−熱伝導率のグラフから、
４０×１０-4ｃａｌ／ｓｅｃ・ｃｍ・℃となる。The inverter circuit shown in FIG. 5 allows a three-phase motor 71 of, for example, 300 W to have an inverter conversion efficiency of 90%.
, A loss (Pross) of 30 W occurs. Also, the maximum value of the ambient temperature of the system (Tamax)
Is 60 ° C., the operating upper limit (Tjmax) of the junction temperature of the semiconductor element is usually 150 ° C., and the maximum temperature rise (ΔTmax) at which the semiconductor element can operate is 90 deg.
Becomes Therefore, the upper limit of the thermal resistance required for the resin package 5 is ΔTmax / Pros = 3.0 ° C./W
The thermal conductivity corresponding to the upper limit of 3.0 ° C./W of the thermal resistance is obtained from the graph of thermal resistance-thermal conductivity shown in FIG.
It becomes 40 × 10 −4 cal / sec · cm · ° C.
【００５１】図６に示すように、樹脂パッケージ５の熱
伝導率が４０×１０-4ｃａｌ／ｓｅｃ・ｃｍ・℃より小
さい場合、熱抵抗は３．０℃／Ｗより大きくなり（図６
の領域Ｒａ）、半導体素子の接合温度が上限値を超えて
素子破壊につながる。一方、樹脂パッケージ５の熱伝導
率が４０×１０-4ｃａｌ／ｓｅｃ・ｃｍ・℃以上であれ
ば、熱抵抗は３．０℃／Ｗ以下となり（図６の領域Ｒ
ｂ）、良好な放熱特性が得られることになる。As shown in FIG. 6, when the thermal conductivity of the resin package 5 is smaller than 40 × 10 −4 cal / sec · cm · ° C., the thermal resistance becomes larger than 3.0 ° C./W (FIG. 6).
In the region Ra), the junction temperature of the semiconductor element exceeds the upper limit, leading to element destruction. On the other hand, if the thermal conductivity of the resin package 5 is 40 × 10 −4 cal / sec · cm · ° C. or more, the thermal resistance becomes 3.0 ° C./W or less (region R in FIG. 6).
b) Good heat radiation characteristics can be obtained.
【００５２】また、上記したように、リードフレームの
裏面側における樹脂パッケージ５の厚みＴ１が５０μｍ
から６００μｍに設定される理由について述べる。な
お、樹脂パッケージ５の貫通孔４−１、４−２の半径
が、リードフレームに設けられた取付け穴１４−１、１
４−２の半径よりも５０μｍから６００μｍ（Ｔ２）だ
け小さく設定される理由についても同様であるので、こ
れについては説明を省略する。Further, as described above, the thickness T1 of the resin package 5 on the back side of the lead frame is 50 μm.
The reason for setting the thickness to 600 μm will be described. Note that the radius of the through holes 4-1 and 4-2 of the resin package 5 is equal to the mounting holes 14-1, 1 and 2 provided in the lead frame.
The same applies to the reason that the radius is set to be smaller by 50 μm to 600 μm (T2) than the radius of 4-2, and therefore the description thereof is omitted.
【００５３】樹脂パッケージ５の厚みが５０μｍより小
さい場合は、図７に示す熱抵抗−樹脂厚みのグラフか
ら、熱抵抗は十分に小さく放熱効果はある（図７の領域
Ｒ１）が、樹脂形成性が悪くなり、絶縁不良が発生する
可能性がある。一方、樹脂パッケージ５の厚みが６００
μｍより大きい場合は、熱抵抗が３．０℃／Ｗを超える
（図７の領域Ｒ３）ため、放熱特性が悪くなり、半導体
素子の接合温度が上限値を超えて素子破壊につながるこ
とになる。よって、樹脂パッケージ５の厚みとして５０
μｍから６００μｍの範囲（図７の領域Ｒ２）が、絶縁
不良の防止と放熱特性の両面から好適となる。When the thickness of the resin package 5 is smaller than 50 μm, the heat resistance is sufficiently small and the heat radiation effect is obtained (region R1 in FIG. 7) from the heat resistance-resin thickness graph shown in FIG. And insulation failure may occur. On the other hand, when the thickness of the resin package 5 is 600
If it is larger than μm, the thermal resistance exceeds 3.0 ° C./W (region R3 in FIG. 7), so that the heat radiation characteristic deteriorates, and the junction temperature of the semiconductor element exceeds the upper limit, which leads to element destruction. . Therefore, the thickness of the resin package 5 is 50
The range of μm to 600 μm (region R2 in FIG. 7) is preferable in terms of both prevention of insulation failure and heat dissipation characteristics.
【００５４】以上のように、従来では、図１０および図
１１に示すような単体の半導体装置を用いてモータ駆動
用インバータ回路を構成した場合、半導体部品点数とし
て、６個の電力スイッチング用半導体装置と３個の制御
用半導体装置の合計９個必要であったのが、本実施形態
によれば、図５に示すように、３個の半導体装置１５−
１、１５−２、１５−３で構成できるので、セットの小
型化、軽量化を実現できる。As described above, conventionally, when an inverter circuit for driving a motor is formed using a single semiconductor device as shown in FIGS. 10 and 11, six semiconductor devices for power switching are used as semiconductor components. According to the present embodiment, a total of nine control semiconductor devices 15 and three control semiconductor devices are required, as shown in FIG.
1, 15-2 and 15-3, the set can be reduced in size and weight.
【００５５】また、図１２に示すような絶縁金属基板を
用いた一体型モジュールでは、高価な絶縁金属基板（金
属基板に絶縁膜及び銅板を全面に張り付け、その後選択
エッチにて素子搭載部を形成）に半導体素子を搭載し、
その後、外部装置に接続するためのリード及び樹脂ケー
スを接着しているが、本実施形態によれば、プレス加工
によるリードフレームの使用によるコストダウンだけで
なく、電力スイッチング素子搭載部と外部リードとの間
に取付け穴を形成し、その取付け穴と同心でそれより径
が小さい貫通孔を樹脂パッケージに設けることで、放熱
特性の性能改善も可能となる。In an integrated module using an insulated metal substrate as shown in FIG. 12, an expensive insulated metal substrate (an insulating film and a copper plate are adhered to the entire surface of the metal substrate, and then an element mounting portion is formed by selective etching. ) With a semiconductor element
After that, the lead for connecting to the external device and the resin case are bonded, but according to the present embodiment, not only the cost reduction due to the use of the lead frame by press working, but also the power switching element mounting portion and the external lead By forming a mounting hole between them and providing a through hole concentric with the mounting hole and having a smaller diameter in the resin package, the performance of heat radiation characteristics can be improved.
【００５６】さらに、本実施形態では、電力スイッチン
グ素子と制御素子、電力スイッチング素子と外部リー
ド、および制御素子と外部リードを接続するための金属
細線の接続距離を最小限にすることができ、材料費の削
減や製造プロセスの簡素化が図れる。Furthermore, in the present embodiment, the connection distance between the power switching element and the control element, the connection distance between the power switching element and the external lead, and the thin metal wire for connecting the control element and the external lead can be minimized. The cost can be reduced and the manufacturing process can be simplified.
【００５７】また、金属細線の距離を最小限にすること
で、スイッチング素子と制御ＩＣのゲートループ長さが
最小になるため、インダクタンスＬ値が最小になりノイ
ズの影響が削減でき、スイッチ素子の誤動作が防止でき
る。Further, by minimizing the distance between the thin metal wires, the gate loop length between the switching element and the control IC is minimized, so that the inductance L value is minimized and the influence of noise can be reduced. Malfunction can be prevented.
【００５８】さらに、金属細線の距離を最小限にするこ
とで、金属細線の変形も小さくすることが可能になり、
完成品の環境試験、特に、熱衝撃テスト等の信頼性レベ
ルの向上を図ることができる。Further, by minimizing the distance between the fine metal wires, the deformation of the fine metal wires can be reduced.
It is possible to improve the reliability level of an environmental test of the completed product, particularly, a thermal shock test or the like.
【００５９】なお、本実施形態では、半導体装置を３相
モータ駆動用インバータ回路に適用するために、電力ス
イッチング素子として、トーテムポール接続された一対
のパワーＭＯＳＦＥＴを半導体装置に搭載したが、例え
ば電源用回路の場合は、電力スイッチング素子として
は、例えば１個のパワーＭＯＳＦＥＴが用いられる。そ
の場合でも同様に、本発明を適用することができる。In this embodiment, in order to apply the semiconductor device to a three-phase motor drive inverter circuit, a pair of totem-pole-connected power MOSFETs are mounted on the semiconductor device as power switching elements. In the case of an application circuit, for example, one power MOSFET is used as a power switching element. In this case, the present invention can be applied similarly.
【００６０】（第２実施形態）図８は、本発明の第２実
施形態による半導体装置の構成を示す外観平面図で、図
８（ａ）は樹脂パッケージが形成された後、図８（ｂ）
は樹脂パッケージが形成される前の状態を示す。(Second Embodiment) FIG. 8 is an external plan view showing the structure of a semiconductor device according to a second embodiment of the present invention. FIG. 8A shows a state after a resin package is formed. )
Indicates a state before the resin package is formed.
【００６１】なお、本実施形態が第１実施形態と異なる
のは、リードフレームの金属板１３’−１、１３’−２
がそれぞれ、電力スイッチング素子搭載部１−１、１−
２と一体で一端に形成された複数の外部リード３’−
１、３’−２を有している点にあり、製造方法、半導体
装置の動作方法等は第１実施形態と同じであるので、詳
細な説明は省略する。The present embodiment is different from the first embodiment in that the metal plates 13'-1, 13'-2 of the lead frame are different.
Are the power switching element mounting units 1-1 and 1-, respectively.
A plurality of external leads 3'-
1 and 3′-2, and the manufacturing method, the operation method of the semiconductor device, and the like are the same as those of the first embodiment.
【００６２】本実施形態によれば、第１実施形態の利点
に加えて、電力スイッチング素子で発生した熱を、複数
の外部リード３’−１、３’−２を通じて外部装置のプ
リント基板に放散することで、放熱特性をさらに向上さ
せることができる。According to this embodiment, in addition to the advantages of the first embodiment, the heat generated by the power switching element is dissipated to the printed circuit board of the external device through the plurality of external leads 3'-1, 3'-2. By doing so, the heat radiation characteristics can be further improved.
【００６３】[0063]
【発明の効果】以上説明したように、本発明によれば、
電力スイッチング素子と制御素子を１つの樹脂パッケー
ジに内蔵し、小型、軽量、低価格化を可能にするととも
に、ノイズによる誤動作を低減した半導体装置を実現す
ることができると共に、電力スイッチング素子と制御素
子を１つの樹脂パッケージに内蔵した際に生じる、高電
力を扱う電力スイッチング素子による発熱の影響を軽減
することが可能になるという格別の効果を奏する。As described above, according to the present invention,
The power switching element and the control element are built in a single resin package, so that the semiconductor device can be reduced in size, weight, and cost, and malfunctions due to noise can be reduced. Has a special effect that it is possible to reduce the influence of heat generated by a power switching element that handles high power, which is generated when the semiconductor device is incorporated in one resin package.
【図１】 本発明の第１実施形態による、封止樹脂が形
成された後（ａ）および封止樹脂が形成される前（ｂ）
の半導体装置の構成を示す外観平面図FIG. 1 shows a state after a sealing resin is formed (a) and before a sealing resin is formed (b) according to a first embodiment of the present invention.
Plan view showing the configuration of the semiconductor device of FIG.
【図２】 図１に示す半導体装置の回路構成を示す等価
回路図FIG. 2 is an equivalent circuit diagram showing a circuit configuration of the semiconductor device shown in FIG.
【図３】 図１に示す半導体装置の製造工程を示す平面
図FIG. 3 is a plan view showing a manufacturing process of the semiconductor device shown in FIG. 1;
【図４】 図１に示す半導体装置のＡ−Ａ’線に沿った
断面図4 is a cross-sectional view of the semiconductor device shown in FIG. 1, taken along line AA ′.
【図５】 図１に示す半導体装置を適用した３相モータ
駆動用インバータ回路の構成を示す回路図FIG. 5 is a circuit diagram showing a configuration of an inverter circuit for driving a three-phase motor to which the semiconductor device shown in FIG. 1 is applied;
【図６】 樹脂パッケージ５の熱抵抗−熱伝導率特性を
示すグラフFIG. 6 is a graph showing thermal resistance-thermal conductivity characteristics of the resin package 5;
【図７】 樹脂パッケージ５の熱抵抗−樹脂厚み特性を
示すグラフFIG. 7 is a graph showing thermal resistance-resin thickness characteristics of the resin package 5;
【図８】 本発明の第２実施形態による、封止樹脂が形
成された後（ａ）および封止樹脂が形成される前（ｂ）
の半導体装置の構成を示す外観平面図FIG. 8 shows a state after a sealing resin is formed (a) and before a sealing resin is formed (b) according to a second embodiment of the present invention.
Plan view showing the configuration of the semiconductor device of FIG.
【図９】 図８に示す半導体装置の製造工程を示す平面
図FIG. 9 is a plan view showing a manufacturing process of the semiconductor device shown in FIG. 8;
【図１０】 樹脂封止後（ａ）および樹脂封止前（ｂ）
における従来の電力スイッチング用半導体装置の構成を
示す外観平面図FIG. 10 (a) after resin encapsulation and (b) before resin encapsulation
Plan view showing the configuration of a conventional semiconductor device for power switching in Japan
【図１１】 樹脂封止後（ａ）および樹脂封止前（ｂ）
における従来の制御用半導体装置の構成を示す外観平面
図FIG. 11 (a) after resin encapsulation and (b) before resin encapsulation
Plan view showing the configuration of a conventional control semiconductor device in a semiconductor device.
【図１２】 他の従来の一体型モジュールによる半導体
装置の構成を示す外観平面図（ａ）およびＡ−Ａ’線に
沿った断面図（ｂ）12A and 12B are an external plan view and a cross-sectional view taken along line AA ′ showing a configuration of a semiconductor device using another conventional integrated module.
【図１３】 従来の半導体装置を適用した３相モータ駆
動用インバータ回路の構成を示す回路図FIG. 13 is a circuit diagram showing a configuration of a three-phase motor driving inverter circuit to which a conventional semiconductor device is applied.
１−１、１−２ 電力スイッチング素子搭載部（第１素
子搭載部） ２ 制御素子搭載部（第２素子搭載部） ３、３’ 複数の外部リード ３−１、３−２、３’−１、３’−２ 第１外部リード ３−３ 第２外部リード ４−１、４−２ 貫通孔 ５ 樹脂パッケージ ６ 金属基板 ７ 絶縁膜 ８ 銅板 ９、９−１、９−２ 素子接着用半田 １０、１０−１、１０−２ 電力スイッチング素子 １１ 制御素子 １２ 金属細線 １３−１、１３−２、１３’−１、１３’−２ 第１金
属板 １３−３ 第２金属板 １４−１、１４−２ 取付け穴 １５−１、１５−２、１５−３ 半導体装置1-1, 1-2 Power switching element mounting section (first element mounting section) 2 Control element mounting section (second element mounting section) 3, 3 'Plural external leads 3-1, 3-2, 3'- 1, 3'-2 First external lead 3-3 Second external lead 4-1, 4-2 Through hole 5 Resin package 6 Metal substrate 7 Insulating film 8 Copper plate 9, 9-1, 9-2 Solder for element bonding 10, 10-1, 10-2 Power switching element 11 Control element 12 Fine metal wire 13-1, 13-2, 13'-1, 13'-2 First metal plate 13-3 Second metal plate 14-1, 14-2 Mounting Hole 15-1, 15-2, 15-3 Semiconductor Device
Claims (4)
体素子が樹脂パッケージ内に封止された半導体装置であ
って、 前記リードフレームは、 第１半導体素子が搭載される第１素子搭載部、および前
記第１素子搭載部の一端に形成され、外部との電気的な
接続を行うための第１外部リードを有する第１金属板
と、 前記第１半導体素子よりも小さな電力で動作する第２半
導体素子が搭載される第２素子搭載部、および前記第２
素子搭載部の一端に形成され、外部との電気的な接続を
行うための第２外部リードを有する第２金属板とを備
え、 前記第１金属板は、前記半導体装置を外部装置に取り付
けるために、前記第１素子搭載部と前記第１外部リード
との間に設けられた取付け穴を有することを特徴とする
半導体装置。1. A semiconductor device in which a plurality of semiconductor elements mounted on a lead frame are sealed in a resin package, wherein the lead frame includes a first element mounting portion on which a first semiconductor element is mounted, and A first metal plate formed at one end of the first element mounting portion and having a first external lead for making an electrical connection to the outside; a second semiconductor operating with less power than the first semiconductor element A second element mounting portion on which the element is mounted;
A second metal plate formed at one end of the element mounting portion and having a second external lead for making an electrical connection to the outside, wherein the first metal plate is for attaching the semiconductor device to an external device. A mounting hole provided between the first element mounting portion and the first external lead.
素子であり、前記第２半導体素子は前記電力スイッチン
グ素子の駆動を制御するための制御素子であることを特
徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said first semiconductor element is a power switching element, and said second semiconductor element is a control element for controlling driving of said power switching element. .
からなることを特徴とする請求項１または２記載の半導
体装置。3. The semiconductor device according to claim 1, wherein said first external lead comprises a plurality of external leads.
第１および第２半導体素子が搭載される前記リードフレ
ームの表面側およびその裏面側の両方に形成され、４０
×１０-4ｃａｌ／ｓｅｃ・ｃｍ・℃以上の熱伝導率を有
し、前記裏面側における樹脂パッケージの厚みが５０μ
ｍから６００μｍであり、かつ、前記第１金属板に設け
られた前記取付け穴と同心で、前記取付け穴の半径より
も５０μｍから６００μｍだけ小さい半径を有する貫通
孔が設けられたことを特徴とする請求項１から３のいず
れか一項記載の半導体装置。4. The sealing resin for the resin package is formed on both the front side and the back side of the lead frame on which the first and second semiconductor elements are mounted,
Having a thermal conductivity of × 10 -4 cal / sec · cm · ° C. or more, and the thickness of the resin package on the back side is 50 μm
and a through hole having a radius of 50 to 600 μm, which is from 50 m to 600 μm, and which is concentric with the mounting hole provided in the first metal plate and smaller than the radius of the mounting hole. The semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000272194A JP2002083927A (en) | 2000-09-07 | 2000-09-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000272194A JP2002083927A (en) | 2000-09-07 | 2000-09-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002083927A true JP2002083927A (en) | 2002-03-22 |
Family
ID=18758354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000272194A Pending JP2002083927A (en) | 2000-09-07 | 2000-09-07 | Semiconductor device |
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| Country | Link |
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