US20170103904A1 - Integrated circuit package mold assembly - Google Patents
Integrated circuit package mold assembly Download PDFInfo
- Publication number
- US20170103904A1 US20170103904A1 US14/880,976 US201514880976A US2017103904A1 US 20170103904 A1 US20170103904 A1 US 20170103904A1 US 201514880976 A US201514880976 A US 201514880976A US 2017103904 A1 US2017103904 A1 US 2017103904A1
- Authority
- US
- United States
- Prior art keywords
- mold
- substrates
- substrate
- assembly
- leadframe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 150000001875 compounds Chemical class 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 18
- 238000004891 communication Methods 0.000 claims description 5
- 239000012530 fluid Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- HUWSZNZAROKDRZ-RRLWZMAJSA-N (3r,4r)-3-azaniumyl-5-[[(2s,3r)-1-[(2s)-2,3-dicarboxypyrrolidin-1-yl]-3-methyl-1-oxopentan-2-yl]amino]-5-oxo-4-sulfanylpentane-1-sulfonate Chemical compound OS(=O)(=O)CC[C@@H](N)[C@@H](S)C(=O)N[C@@H]([C@H](C)CC)C(=O)N1CCC(C(O)=O)[C@H]1C(O)=O HUWSZNZAROKDRZ-RRLWZMAJSA-N 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 235000013619 trace mineral Nutrition 0.000 description 1
- 239000011573 trace mineral Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- An integrated circuit (“IC”) package mold assembly includes an upper mold platen defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side faces upwardly.
- a lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.
- FIG. 2 is a cross-sectional elevation view of an example embodiment of a mold assembly that includes a mold with a double cavity configuration.
- FIG. 3 is a cross-sectional elevation view of another example embodiment of a double cavity mold assembly.
- FIG. 5 is a cross-sectional elevation view of a portion of another example embodiment of a double cavity mold assembly.
- FIG. 6 is a flow chart that illustrates a method of making integrated circuit (“IC”) packages.
- FIG. 1 is a cross-sectional elevation view of a prior art mold assembly 10 .
- the mold assembly 10 includes a mold 11 , such as an injection mold, that has an upper mold platen 12 and a lower mold platen 14 .
- the upper mold platen 12 has a mold cavity 16 therein in fluid communication with a mold runner 18 .
- the mold assembly 10 also includes a leadframe sheet 22 that is positioned within the mold cavity 16 .
- the mold assembly 10 further includes a plurality of integrated circuit (IC) dies 24 , 26 , 28 , etc., which are attached to different portions 25 , 27 , 29 , etc., of the leadframe sheet 22 .
- IC integrated circuit
- the mold 10 After insertion of the leadframe sheet 22 and attached wire bonded dies 24 , etc., the mold 10 is closed and the mold cavity 16 is filled with molten mold compound 40 .
- the mold compound 40 flows under pressure into the cavity 16 through the runner 18 , which is conventionally connected to a pressurized source of molten mold compound 40 .
- curing of the mold compound commences, initially while the mold 10 is closed, and subsequently after it is has been opened and the entire assembly of leadframe sheet 22 , dies 24 , etc. and mold compound 40 has been removed.
- the portion of the mold compound 40 that was in the runner 18 is removed from the portion of the mold compound covering the leadframe sheet 22 .
- the portion of the mold compound that was in the runner is scrapped as waste. This waste is typically around 40% of the total amount of mold compound injected in a molding operation.
- FIG. 2 is a cross-sectional elevation view of an example embodiment of a mold assembly 110 that includes a mold 111 with a double cavity configuration.
- the mold 111 includes upper and lower mold platens 112 , 114 having upper and lower mold cavities 116 , 118 , respectively.
- a single mold runner 120 is in fluid communication with both mold cavities 116 , 118 .
- the mold assembly 110 includes an upper substrate 122 , which may be a leadframe sheet substrate.
- leadframe sheet substrate is referred to by the shorter phrase “leadframe sheet.” It is to be understood that substrates other than leadframe sheets may be used in the embodiments described in FIGS. 2, 3 and 5 .
- the substrate 122 has a first end 124 and a second end 126 and has a die attach side 128 and an opposite or “non-attach side” 129 .
- a lower substrate 132 which in this embodiment may be a leadframe sheet, has a first end 134 and a second end 136 and also includes a die attach side 138 and an opposite or non-attach side 139 .
- the upper substrate 122 and the lower substrate 132 each comprise a plurality of corresponding separate substrate portions 140 and 142 , respectively, which are vertically aligned.
- the mold assembly 110 also includes upper and lower substrate dies.
- the upper substrate dies 152 are mounted on the upper substrate portions 140 of the upper substrate 124 and are electrically connected thereto, as by upper bond wires 154 .
- lower substrate dies 162 are attached to the separate substrate portions 142 of the lower substrate 134 and are connected thereto by lower leadframe bond wires 164 .
- a liner 170 may be used in some embodiments to separate the upper and lower substrates. In some embodiments when the respective substrates are, for example, nFBGA (New Fine Pitch Ball Grid Array packages) substrates or uBGA (Ultra FineLine Ball-Grid Array packages) substrates, rather than leadframe sheets, no liner is needed.
- the liner 170 engages the non-attach sides 129 , 139 of the substrates 122 , 132 .
- the mold assembly also includes heated mold compound 178 that is injected into the single mold runner and flows therethrough to fill both the upper and lower mold cavities 116 , 118 .
- the mold compound 178 is initially allowed to cure within the mold cavities 116 , 118 .
- the entire substrate/die/bond wire/mold compound assembly, including the mold compound 178 within the runner 120 is removed from the mold 111 .
- the solidified mold compound 178 within the runner 120 is then removed and scrapped. Because there is a single runner 120 associated with both mold cavities 116 , 118 , the scrap produced by this new process is substantially reduced as compared to the scrap produced in the conventional process illustrated in FIG. 1 .
- each substrate 122 , etc., 132 , and associated dies and mold compound, etc. is then singulated by conventional methods to provide a plurality of separate IC packages.
- upper and lower passive components 253 , 255 are also operably mounted on each substrate portion 240 or 242 and electrically connected to the die(s) on the associated portion 240 or 242 .
- Another difference in the assembly of FIG. 3 from that of FIG. 2 is that holes 280 have been bored through the two substrates 222 , 232 and liner sheet 270 after initially sandwiching the liner sheet 270 between the two substrates 222 , 232 and before insertion of this substrate/liner assembly into the mold 210 . These holes 280 may be bored at each corner intersection of the substrates when they comprise leadframe sheets 222 , 232 . Four separate leadframe portions are integrally connected.
- the illustrated embodiment shows the holes located at corner intersections of the sheets 222 , 232 , but the holes 280 may be provided at other locations.
- the binding feature is larger than corner space allows, several of the dies may be eliminated and the holes can be located on the leadframes, or other substrates, where the dies have been eliminated.
- FIG. 4 is a detail isometric view illustrating a portion of structure located around the holes 280 shown in FIG. 3 .
- This structure includes a rectangular frame structure 284 .
- the rectangular frame structure laterally connects first, second, third and fourth upper leadframe portions 286 , 288 , 290 , 292 , respectively, of the upper leadframe sheet 222 .
- the lower leadframe sheet 232 has an identical configuration (not shown) lying directly below that of sheet 222 .
- the hole 280 passes through the center of this rectangular frame portion 284 and an aligned portion 282 of the liner 270 .
- the corner structure remains intact until singulation and the two connected molded leadframe sheets 222 , 232 and liner 270 are all singulated simultaneously with deeper singulation cuts.
- the upper and lower IC package pairs, thus formed, are then separated. In this case, singulation removes the corner structure and connecting mold compound structure.
- the prior art structure as shown by FIG. 1 , has a metal leadframe sheet 22 on one side of the assembly, and epoxy encapsulant compound 40 on the other side. Due to a mismatch in thermal expansion of these two materials, when the assembly is ejected from the mold 11 and cools down from a high mold temperature, the encapsulated leadframe sheet 22 tends to warp. Such warping makes the prior art leadframe sheet 22 difficult to work with and, in some cases, is so severe that the molded leadframe sheet 22 must be scrapped.
- the connecting structure formed by the mold compound 278 after it solidifies in holes 280 combined with the symmetry of the two substrates, prevents warping of the substrates 222 , 232 .
- FIG. 5 is a cross-sectional elevation view of a portion of another example embodiment of a double-sided mold assembly 310 .
- the mold assembly 310 includes a mold 311 that comprises upper and lower mold platens 312 , 314 having upper and lower mold cavities 316 , 318 , respectively.
- the mold 311 may be identical to the mold 211 illustrated in FIG. 3 , except that upper projections 317 and lower projections 319 extends from the upper and lower mold platens, like symmetrical stalactites and stalagmites, to form a clamping assembly that sandwiches and holds upper and lower leadframes/substrates 322 , 332 therebetween.
- projections 317 , 319 may be provided by ribs that are integrally formed with the respective upper and lower mold platens 312 , 314 or may be provided by pins inserted through the walls of the mold platens or may be formed by other means.
- the projections may engage the leadframes/substrates 322 , 332 at the boundaries of adjacent substrate portions, such that any irregularities in the mold compound layer formed by the projections 317 , 319 is trimmed off during subsequent singulation.
- This clamping assembly 317 , 319 vertically supports the leadframes 322 , 332 , counteracting a tendency of the leadframes to droop under their own weight prior to the inflow of mold compound (not shown in FIG. 5 ).
- FIG. 6 is a flow chart that illustrates a method of making integrated circuit (“IC”) packages.
- the method includes, as shown at 601 , placing first and second IC package substrates having a plurality of individual portions associated with individual IC packages in non-attach side facing, mirror image relationship.
- the method also includes, as shown at 602 , placing the first and second substrates in a mold having upper and lower cavities with the first substrate positioned in an upper mold platen cavity and the second substrate positioned in a lower mold platen cavity that is in fluid communication with the upper mold platen cavity.
- the method further includes filling the upper and lower mold cavities with molten mold compound.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.
Description
- Integrated circuits, also referred to as “IC's” or “semiconductor chips” or simply “chips,” are electronic circuits made by diffusion of trace elements into the surface of thin substrates of semiconductor material. Integrated circuits were first produced in the mid 20th Century. Because of their small size and relatively low production cost, integrated circuits are now used in most modern electronics. Semiconductor chips are typically mass produced in the form of a single wafer that contains a large number of identical integrated circuits. The wafer is cut (“singulated”) into a number of individual semiconductor chips referred to as “dies” or “dice.”
- Dies and sometimes other components such as passive devices are “packaged” to prevent damage to the dies and to facilitate attachment of the dies to circuit boards. Various packaging materials and processes have been used to package integrated circuit dies. One conventional packaging method involves mounting individual dies in a predetermined pattern on a substrate strip. The dies mounted on the substrate strip are then encapsulated in a plastic material, such as by a transfer molding process. Next, the encapsulated dies are singulated into individual integrated circuit packages by cutting the encapsulated die/substrate strip in accordance with the predetermined die mounting pattern. Typical cutting tools include saws and punches. Each integrated circuit package generally includes at least one die and the underlying portion of the substrate strip on which it was mounted. The underlying substrate strip is sometimes a leadframe to which the die is electrically connected.
- An integrated circuit (“IC”) package mold assembly includes an upper mold platen defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.
-
FIG. 1 is a cross-sectional elevation view of a prior art mold assembly. -
FIG. 2 is a cross-sectional elevation view of an example embodiment of a mold assembly that includes a mold with a double cavity configuration. -
FIG. 3 is a cross-sectional elevation view of another example embodiment of a double cavity mold assembly. -
FIG. 4 is a detail isometric view of a portion of the double cavity mold assembly ofFIG. 3 . -
FIG. 5 is a cross-sectional elevation view of a portion of another example embodiment of a double cavity mold assembly. -
FIG. 6 is a flow chart that illustrates a method of making integrated circuit (“IC”) packages. -
FIG. 1 is a cross-sectional elevation view of a priorart mold assembly 10. Themold assembly 10 includes a mold 11, such as an injection mold, that has anupper mold platen 12 and alower mold platen 14. Theupper mold platen 12 has amold cavity 16 therein in fluid communication with amold runner 18. Themold assembly 10 also includes aleadframe sheet 22 that is positioned within themold cavity 16. Themold assembly 10 further includes a plurality of integrated circuit (IC) dies 24, 26, 28, etc., which are attached todifferent portions leadframe sheet 22. Each of theseportions leadframe sheet 22. - Each of the
dies leadframe portion leadframe sheet 22. In theassembly 10 ofFIG. 2 the dies are electrically connected to theleadframe sheet 22 bybond wires 30. Eachbond wire 30 has afirst end 32 attached to an associated die, e.g., die 24, and asecond end 34 attached to the leadframe portion, e.g.,portion 25, on which the die is mounted. - After insertion of the
leadframe sheet 22 and attached wire bonded dies 24, etc., themold 10 is closed and themold cavity 16 is filled withmolten mold compound 40. Themold compound 40 flows under pressure into thecavity 16 through therunner 18, which is conventionally connected to a pressurized source ofmolten mold compound 40. After themold compound 40 has filled the cavity, curing of the mold compound commences, initially while themold 10 is closed, and subsequently after it is has been opened and the entire assembly ofleadframe sheet 22, dies 24, etc. andmold compound 40 has been removed. After removal from themold 10, the portion of themold compound 40 that was in therunner 18 is removed from the portion of the mold compound covering theleadframe sheet 22. The portion of the mold compound that was in the runner is scrapped as waste. This waste is typically around 40% of the total amount of mold compound injected in a molding operation. - After the molded leadframe assembly has completed curing it is singulated along saw
streets FIG. 1 , into separate IC package units. -
FIG. 2 is a cross-sectional elevation view of an example embodiment of amold assembly 110 that includes a mold 111 with a double cavity configuration. The mold 111 includes upper andlower mold platens lower mold cavities single mold runner 120 is in fluid communication with bothmold cavities - The
mold assembly 110 includes anupper substrate 122, which may be a leadframe sheet substrate. Hereafter “leadframe sheet substrate” is referred to by the shorter phrase “leadframe sheet.” It is to be understood that substrates other than leadframe sheets may be used in the embodiments described inFIGS. 2, 3 and 5 . - The
substrate 122 has afirst end 124 and asecond end 126 and has adie attach side 128 and an opposite or “non-attach side” 129. Alower substrate 132, which in this embodiment may be a leadframe sheet, has afirst end 134 and asecond end 136 and also includes adie attach side 138 and an opposite ornon-attach side 139. Theupper substrate 122 and thelower substrate 132 each comprise a plurality of correspondingseparate substrate portions - The
mold assembly 110 also includes upper and lower substrate dies. The upper substrate dies 152 are mounted on theupper substrate portions 140 of theupper substrate 124 and are electrically connected thereto, as byupper bond wires 154. Similarly lower substrate dies 162 are attached to theseparate substrate portions 142 of thelower substrate 134 and are connected thereto by lowerleadframe bond wires 164. As illustrated inFIG. 2 , aliner 170 may be used in some embodiments to separate the upper and lower substrates. In some embodiments when the respective substrates are, for example, nFBGA (New Fine Pitch Ball Grid Array packages) substrates or uBGA (Ultra FineLine Ball-Grid Array packages) substrates, rather than leadframe sheets, no liner is needed. Theliner 170 engages thenon-attach sides substrates - As further illustrated by
FIG. 2 , the mold assembly also includes heatedmold compound 178 that is injected into the single mold runner and flows therethrough to fill both the upper andlower mold cavities mold compound 178 is initially allowed to cure within themold cavities mold compound 178 within therunner 120, is removed from the mold 111. The solidifiedmold compound 178 within therunner 120 is then removed and scrapped. Because there is asingle runner 120 associated with bothmold cavities FIG. 1 . - Next the upper and lower
molded substrates 122, etc., 132, etc., are separated and theliner 170, if used, is removed. Eachsubstrate 122, etc., 132, and associated dies and mold compound, etc., is then singulated by conventional methods to provide a plurality of separate IC packages. -
FIG. 3 is a cross-sectional elevation view of another example embodiment of a double-sided mold assembly 210 including a mold 211 that has upper andlower mold platens lower mold cavities assembly 210 illustrated inFIG. 3 is similar to that illustrated inFIG. 2 , and similar structures therein are given the identical reference numerals as inFIG. 2 , except that the reference numerals are 200 series rather than 100 series. The structures include: runner 220,upper substrate 222 having a first and second ends 224, 226 and die attachside 228 andnon-attach side 229 and upper leadframe portions 240; alower substrate 232 with a first and second ends 234, 236 and with a die attachside 238 andnon-attach side 139 and separate upper and lower substrate portions 240 and 242; upper dies 252, which may be electrically connected to the upper substrate bybond wires 254; lower dies withbond wires 264;liner 270; and mold compound 278. One difference in the assembly ofFIG. 3 is that upper and lowerpassive components 253, 255 (e.g., resistors, capacitors and/or inductors) are also operably mounted on each substrate portion 240 or 242 and electrically connected to the die(s) on the associated portion 240 or 242. Another difference in the assembly ofFIG. 3 from that ofFIG. 2 is thatholes 280 have been bored through the twosubstrates liner sheet 270 after initially sandwiching theliner sheet 270 between the twosubstrates mold 210. Theseholes 280 may be bored at each corner intersection of the substrates when they compriseleadframe sheets sheets holes 280 may be provided at other locations. For example, if the binding feature is larger than corner space allows, several of the dies may be eliminated and the holes can be located on the leadframes, or other substrates, where the dies have been eliminated.) -
FIG. 4 is a detail isometric view illustrating a portion of structure located around theholes 280 shown inFIG. 3 . This structure includes arectangular frame structure 284. The rectangular frame structure laterally connects first, second, third and fourthupper leadframe portions upper leadframe sheet 222. Thelower leadframe sheet 232 has an identical configuration (not shown) lying directly below that ofsheet 222. Thehole 280 passes through the center of thisrectangular frame portion 284 and an alignedportion 282 of theliner 270. - With reference to
FIG. 3 , theholes 280 through the assembledsheets holes 280 forms a connecting structure that holds the twosheets holes 280 may also help to provide pressure equalization between the upper andlower mold cavities corner frame structure 284 and the mold compound 278 passing through theholes 280 are bored or cut out and removed after curing to allow theleadframe sheets leadframe sheets liner 270 are all singulated simultaneously with deeper singulation cuts. The upper and lower IC package pairs, thus formed, are then separated. In this case, singulation removes the corner structure and connecting mold compound structure. - The prior art structure, as shown by
FIG. 1 , has ametal leadframe sheet 22 on one side of the assembly, andepoxy encapsulant compound 40 on the other side. Due to a mismatch in thermal expansion of these two materials, when the assembly is ejected from the mold 11 and cools down from a high mold temperature, the encapsulatedleadframe sheet 22 tends to warp. Such warping makes the priorart leadframe sheet 22 difficult to work with and, in some cases, is so severe that the moldedleadframe sheet 22 must be scrapped. In the assembly ofFIG. 3 , the connecting structure formed by the mold compound 278 after it solidifies inholes 280, combined with the symmetry of the two substrates, prevents warping of thesubstrates -
FIG. 5 is a cross-sectional elevation view of a portion of another example embodiment of a double-sided mold assembly 310. Themold assembly 310 includes a mold 311 that comprises upper andlower mold platens lower mold cavities 316, 318, respectively. The mold 311 may be identical to the mold 211 illustrated inFIG. 3 , except thatupper projections 317 andlower projections 319 extends from the upper and lower mold platens, like symmetrical stalactites and stalagmites, to form a clamping assembly that sandwiches and holds upper and lower leadframes/substrates projections lower mold platens substrates projections - This clamping
assembly leadframes FIG. 5 ). - As used herein terms such as up, down, above, under, vertical, horizontal, etc., are used in a relative sense to explain the physical relationship between various structures shown in the drawings, rather than in an absolute sense indicating an orientation of objects within a gravitational field.
-
FIG. 6 is a flow chart that illustrates a method of making integrated circuit (“IC”) packages. The method includes, as shown at 601, placing first and second IC package substrates having a plurality of individual portions associated with individual IC packages in non-attach side facing, mirror image relationship. The method also includes, as shown at 602, placing the first and second substrates in a mold having upper and lower cavities with the first substrate positioned in an upper mold platen cavity and the second substrate positioned in a lower mold platen cavity that is in fluid communication with the upper mold platen cavity. As shown at 603, the method further includes filling the upper and lower mold cavities with molten mold compound. - Certain specific embodiments of double cavity mold assemblies and methods of use thereof have been expressly described in detail herein to aid those reading this disclosure to understand the inventive concepts involved. Alternative embodiments of such mold assemblies and methods will occur to those skilled in the art after reading this disclosure. It is intended that the language of the appended claims be broadly construed to cover such alternative embodiments, except as limited by the prior art.
Claims (20)
1. An integrated circuit (“IC”) package mold assembly comprising:
an upper mold platen defining an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon, wherein said die attach side is facing upwardly; and
a lower mold platen defining a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon, wherein said die attach side of said lower substrate is facing downwardly.
2. The assembly of claim 1 wherein said upper and lower mold platens comprises at least one pair of aligned projections extending into said mold cavities for engaging said upper and lower substrates therebetween.
3. The assembly of claim 1 further comprising a single runner in fluid communication with said upper and lower mold cavities.
4. An integrated circuit (“IC”) package mold assembly comprising:
an upper mold platen defining an upper mold cavity;
a lower mold platen defining a lower mold cavity;
an upper substrate positioned in said upper mold cavity and having a plurality of integrally connected substrate portions, each said upper substrate portion having a die attach side and a non-attach side, IC dies being mounted on said die attach sides of said plurality of upper substrate portions; and
a lower substrate positioned in said lower mold cavity and having a plurality of integrally connected lower substrate portions, each lower substrate portion having a die attach side and a non-attach side, IC dies being mounted on said die attach sides of said plurality of lower substrate portions;
wherein said upper and lower substrates are positioned with said non-attach sides of said substrate portions thereof positioned in facing relationship.
5. The assembly of claim 4 wherein said upper and lower substrates comprise upper and lower leadframe substrates and further comprising a liner positioned between said upper and lower leadframe substrates.
6. The assembly of claim 4 wherein said upper and lower substrates comprises nFBGA (New Fine Pitch Ball Grid Array) substrates.
7. The assembly of claim 4 wherein said upper and lower substrates comprises flex-tape substrates.
8. The assembly of claim 4 wherein said upper and lower substrates have aligned holes extending therethrough.
9. The assembly of claim 8 further comprising a liner positioned between said upper and lower substrates and having holes therein aligned with said holes in said upper and lower substrates.
10. The assembly of claim 9 wherein each of said upper and lower substrates comprise leadframe sheet substrates with leadframe corner connection structures that connect leadframe portions on each corresponding leadframe sheet substrate;
wherein said leadframe corner connection structures have openings therein that are aligned with corresponding ones of said holes extending through said liner.
11. The assembly of claim 8 , said upper and lower mold cavities being filled with mold compound that fills said aligned holes extending through said substrates.
12. A method of making integrated circuit (“IC”) packages comprising:
placing first and second IC package substrates having a plurality of individual portions associated with individual IC packages in non-attach side facing, mirror image relationship;
placing the first and second substrates in a mold having upper and lower cavities with the first substrate positioned in an upper mold platen cavity and the second substrate positioned in a lower mold platen cavity that is in fluid communication with the upper mold platen cavity; and
filling the upper and lower mold cavities with molten mold compound.
13. The method of claim 12 further comprising engaging aligned portions of the first and second IC package substrates with opposite mold platen projections.
14. The method of claim 13 further comprising producing a plurality of holes extending through aligned portions of the first and second substrates.
15. The method of claim 14 further comprising flowing mold compound into the mold to mold the two substrates including flowing mold compound through the plurality of holes to form connecting structures to hold the two molded substrates together.
16. The method of claim 15 further comprising:
curing the mold compound; and
removing connecting structures holding the molded substrates together.
17. The method of claim 16 further comprising separating the molded substrates.
18. The method of claim 17 further comprising dicing the separated molded substrates.
19. The method of claim 15 further comprising dicing the connected molded substrates.
20. The method of claim 19 further comprising removing the connecting structure during said dicing.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/880,976 US20170103904A1 (en) | 2015-10-12 | 2015-10-12 | Integrated circuit package mold assembly |
CN201610892127.8A CN106920757A (en) | 2015-10-12 | 2016-10-12 | Integrated circuit packaging mould sub-assembly |
US15/899,203 US10186431B2 (en) | 2015-10-12 | 2018-02-19 | Integrated circuit package mold assembly |
US16/254,059 US10573537B2 (en) | 2015-10-12 | 2019-01-22 | Integrated circuit package mold assembly |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/880,976 US20170103904A1 (en) | 2015-10-12 | 2015-10-12 | Integrated circuit package mold assembly |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/899,203 Division US10186431B2 (en) | 2015-10-12 | 2018-02-19 | Integrated circuit package mold assembly |
Publications (1)
Publication Number | Publication Date |
---|---|
US20170103904A1 true US20170103904A1 (en) | 2017-04-13 |
Family
ID=58499896
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/880,976 Abandoned US20170103904A1 (en) | 2015-10-12 | 2015-10-12 | Integrated circuit package mold assembly |
US15/899,203 Active US10186431B2 (en) | 2015-10-12 | 2018-02-19 | Integrated circuit package mold assembly |
US16/254,059 Active US10573537B2 (en) | 2015-10-12 | 2019-01-22 | Integrated circuit package mold assembly |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/899,203 Active US10186431B2 (en) | 2015-10-12 | 2018-02-19 | Integrated circuit package mold assembly |
US16/254,059 Active US10573537B2 (en) | 2015-10-12 | 2019-01-22 | Integrated circuit package mold assembly |
Country Status (2)
Country | Link |
---|---|
US (3) | US20170103904A1 (en) |
CN (1) | CN106920757A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180108619A1 (en) * | 2016-10-18 | 2018-04-19 | Advanced Semiconductor Engineering, Inc. | Substrate structure, packaging method and semiconductor package structure |
US10347509B1 (en) | 2018-02-09 | 2019-07-09 | Didrew Technology (Bvi) Limited | Molded cavity fanout package without using a carrier and method of manufacturing the same |
US20190273040A1 (en) * | 2016-11-23 | 2019-09-05 | Abb Schweiz Ag | Manufacturing of a power semiconductor module |
US10424524B2 (en) | 2018-02-15 | 2019-09-24 | Chengdu Eswin Sip Technology Co., Ltd. | Multiple wafers fabrication technique on large carrier with warpage control stiffener |
JP2020096014A (en) * | 2018-12-10 | 2020-06-18 | 日亜化学工業株式会社 | Method of manufacturing semiconductor device and method of manufacturing package member |
CN111341747A (en) * | 2018-12-19 | 2020-06-26 | 恩智浦美国有限公司 | Lead shortening to improve creepage distance |
US10734326B2 (en) | 2018-02-15 | 2020-08-04 | Didrew Technology (Bvi) Limited | Hermetic flat top integrated heat spreader (IHS)/electromagnetic interference (EMI) shield package and method of manufacturing thereof for reducing warpage |
US20210242038A1 (en) * | 2019-08-06 | 2021-08-05 | Texas Instruments Incorporated | Universal semiconductor package molds |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170103904A1 (en) * | 2015-10-12 | 2017-04-13 | Texas Instruments Incorporated | Integrated circuit package mold assembly |
CN111029265B (en) * | 2019-12-26 | 2021-11-23 | 珠海格力电器股份有限公司 | Plastic package mold and method for preventing QFN (quad Flat No lead) mold package frame from warping |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090093088A1 (en) * | 2007-10-05 | 2009-04-09 | Texas Instruments Incorporated | Roll-on encapsulation method for semiconductor packages |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060255479A1 (en) * | 2005-05-10 | 2006-11-16 | Texas Instruments Incorporated | Magnetic assist manufacturing to reduce mold flash and assist with heat slug assembly |
US7371673B2 (en) | 2005-05-17 | 2008-05-13 | Texas Instruments Incorporated | Method and apparatus for attaching an IC package to a PCB assembly |
US8359927B2 (en) * | 2009-08-12 | 2013-01-29 | Freescale Semiconductor, Inc. | Molded differential PRT pressure sensor |
US8587123B2 (en) | 2011-09-27 | 2013-11-19 | Broadcom Corporation | Multi-chip and multi-substrate reconstitution based packaging |
US20130140737A1 (en) * | 2011-12-06 | 2013-06-06 | Texas Instruments Incorporated | Stacked substrate molding |
US20130299955A1 (en) * | 2012-05-08 | 2013-11-14 | Nxp B.V. | Film based ic packaging method and a packaged ic device |
US20170103904A1 (en) * | 2015-10-12 | 2017-04-13 | Texas Instruments Incorporated | Integrated circuit package mold assembly |
-
2015
- 2015-10-12 US US14/880,976 patent/US20170103904A1/en not_active Abandoned
-
2016
- 2016-10-12 CN CN201610892127.8A patent/CN106920757A/en active Pending
-
2018
- 2018-02-19 US US15/899,203 patent/US10186431B2/en active Active
-
2019
- 2019-01-22 US US16/254,059 patent/US10573537B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090093088A1 (en) * | 2007-10-05 | 2009-04-09 | Texas Instruments Incorporated | Roll-on encapsulation method for semiconductor packages |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180108619A1 (en) * | 2016-10-18 | 2018-04-19 | Advanced Semiconductor Engineering, Inc. | Substrate structure, packaging method and semiconductor package structure |
US10833024B2 (en) * | 2016-10-18 | 2020-11-10 | Advanced Semiconductor Engineering, Inc. | Substrate structure, packaging method and semiconductor package structure |
US11189556B2 (en) * | 2016-11-23 | 2021-11-30 | Abb Power Grids Switzerland Ag | Manufacturing of a power semiconductor module |
US20190273040A1 (en) * | 2016-11-23 | 2019-09-05 | Abb Schweiz Ag | Manufacturing of a power semiconductor module |
US10347509B1 (en) | 2018-02-09 | 2019-07-09 | Didrew Technology (Bvi) Limited | Molded cavity fanout package without using a carrier and method of manufacturing the same |
WO2019156695A1 (en) * | 2018-02-09 | 2019-08-15 | Didrew Technology (Bvi) Limited | Method of manufacturing fan out package with carrier-less molded cavity |
US10424524B2 (en) | 2018-02-15 | 2019-09-24 | Chengdu Eswin Sip Technology Co., Ltd. | Multiple wafers fabrication technique on large carrier with warpage control stiffener |
US10734326B2 (en) | 2018-02-15 | 2020-08-04 | Didrew Technology (Bvi) Limited | Hermetic flat top integrated heat spreader (IHS)/electromagnetic interference (EMI) shield package and method of manufacturing thereof for reducing warpage |
JP2020096014A (en) * | 2018-12-10 | 2020-06-18 | 日亜化学工業株式会社 | Method of manufacturing semiconductor device and method of manufacturing package member |
JP7206483B2 (en) | 2018-12-10 | 2023-01-18 | 日亜化学工業株式会社 | Semiconductor device manufacturing method and package member manufacturing method |
CN111341747A (en) * | 2018-12-19 | 2020-06-26 | 恩智浦美国有限公司 | Lead shortening to improve creepage distance |
US20210242038A1 (en) * | 2019-08-06 | 2021-08-05 | Texas Instruments Incorporated | Universal semiconductor package molds |
US11791170B2 (en) * | 2019-08-06 | 2023-10-17 | Texas Instruments Incorporated | Universal semiconductor package molds |
Also Published As
Publication number | Publication date |
---|---|
US20190157110A1 (en) | 2019-05-23 |
CN106920757A (en) | 2017-07-04 |
US10573537B2 (en) | 2020-02-25 |
US10186431B2 (en) | 2019-01-22 |
US20180190509A1 (en) | 2018-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10573537B2 (en) | Integrated circuit package mold assembly | |
US8058098B2 (en) | Method and apparatus for fabricating a plurality of semiconductor devices | |
US7132311B2 (en) | Encapsulation of a stack of semiconductor dice | |
US6910874B2 (en) | Apparatus for encapsulating a multi-chip substrate array | |
CN101964311B (en) | Method of forming integrated circuit and integrated circuit structure | |
US8283251B2 (en) | Method of manufacturing wafer level package | |
US8652384B2 (en) | Method for molding semiconductor device | |
TWI395304B (en) | Thermally enhanced semiconductor package and method of producing the same | |
US20140291822A1 (en) | Integrated circuit package | |
US20040158978A1 (en) | Molding method and mold for encapsulating both sides of PCB module with wafer level package mounted PCB | |
US7208346B2 (en) | Methods of forming interposers on surfaces of dies of a wafer | |
US9076802B1 (en) | Dual-sided film-assist molding process | |
US10453760B2 (en) | Lid array panel, package with lid and method of making the same | |
JP2006269786A (en) | Resin sealing metal mold, and resin sealing metal apparatus and resin sealing method using it | |
US7701073B2 (en) | Locking feature and method for manufacturing transfer molded IC packages | |
JP2010192541A (en) | Resin sealing mold and resin sealing method | |
JP4500435B2 (en) | Semiconductor aggregate substrate resin sealing body, manufacturing method and manufacturing apparatus thereof | |
CN111863772B (en) | Positioning method, packaging assembly and packaging structure | |
CN101859736A (en) | Semiconductor packaging semi-finished product and semiconductor packaging process | |
JP2001044225A (en) | Manufacture of resin-sealed semiconductor device | |
US20060284286A1 (en) | Flashless molding of integrated circuit devices | |
JP3293105B2 (en) | Semiconductor intermediate structure and resin molding device therefor | |
JP6093834B2 (en) | Dummy frame, resin mold evaluation method, mold die evaluation method, and mold die manufacturing method | |
US9252124B2 (en) | Circuit module having a substrate, semiconductor chip, and molding material formed by dicing | |
CN116364562A (en) | Chip packaging method and packaging structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NGUYEN, HIEP XUAN;REEL/FRAME:036837/0146 Effective date: 20151005 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |