CN109727922B - 包括绝热壁的半导体封装 - Google Patents

包括绝热壁的半导体封装 Download PDF

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CN109727922B
CN109727922B CN201810775987.2A CN201810775987A CN109727922B CN 109727922 B CN109727922 B CN 109727922B CN 201810775987 A CN201810775987 A CN 201810775987A CN 109727922 B CN109727922 B CN 109727922B
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semiconductor chip
semiconductor
package
molding layer
insulating wall
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CN109727922A (zh
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姜敃圭
孙在现
申志爀
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SK Hynix Inc
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SK Hynix Inc
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Abstract

包括绝热壁的半导体封装。一种半导体封装包括并排设置在封装基板的表面上的第一半导体芯片和第二半导体芯片。绝热壁被设置在第一半导体芯片与第二半导体芯片之间。绝热壁将第一半导体芯片与第二半导体芯片热隔离。

Description

包括绝热壁的半导体封装
技术领域
本公开涉及半导体封装技术，更具体地讲，涉及包括将一个半导体芯片与另一半导体芯片热隔离的绝热壁的半导体封装。
背景技术
可在单个半导体封装中采用各种类型的半导体芯片。单个半导体封装中所采用的半导体芯片可具有不同的功能。即，单个半导体封装中所采用的半导体芯片可能不同地消耗电力。因此，由单个半导体封装中的半导体芯片产生的热的量也可能彼此不同。
与消耗相对低的电力的低功率半导体芯片相比，消耗相对高的电力的高功率半导体芯片可产生相对大量的热。由高功率半导体芯片产生的热可被传导到与高功率半导体芯片相邻的低功率半导体芯片。在这种情况下，低功率半导体芯片的性能可能由于高功率半导体芯片所产生的热而下降。因此，在至少两种不同类型的半导体芯片被嵌入在单个半导体封装中的情况下，可能有必要开发用于控制或处理单个半导体封装中的热分布和热传导的技术。
发明内容
根据实施方式，提供了一种半导体封装。该半导体封装包括：第一封装基板；内置封装，其被设置在第一封装基板上并被配置为包括第一半导体芯片以及用于将第一半导体芯片热隔离的绝热壁；以及第二半导体芯片，其被设置在第一封装基板上以与内置封装间隔开。
根据另一实施方式，提供了一种半导体封装。该半导体封装包括：第一半导体芯片和第二半导体芯片，它们被并排设置在封装基板的表面上以彼此间隔开；第一模制层，其覆盖第一半导体芯片；第二模制层，其覆盖第二半导体芯片；以及绝热壁，其被设置在第一模制层与第二模制层之间以将第一半导体芯片热隔离。
附图说明
鉴于附图和所附详细描述，本公开的各种实施方式将变得更显而易见，附图中：
图1是示出根据实施方式的半导体封装的平面图；
图2是沿着图1的线A-A’截取的横截面图；
图3是沿着图1的线B-B’截取的横截面图；
图4是示出嵌入在图1的半导体封装中的内置封装的横截面图；
图5是示出没有绝热壁的一般半导体封装作为比较例的平面图；
图6是示出采用包括根据实施方式的半导体封装的存储卡的电子系统的框图；以及
图7是示出包括根据实施方式的半导体封装的另一电子系统的框图。
具体实施方式
本文所使用的术语可对应于考虑其在实施方式中的功能而选择的词语，术语的含义可被解释为根据实施方式所属领域的普通技术人员而不同。如果详细定义，则可根据定义来解释术语。除非另外定义，否则本文所使用的术语(包括技术术语和科学术语)可具有实施方式所属领域的普通技术人员通常理解的相同含义。
将理解，尽管本文中可使用术语“第一”、“第二”、“第三”等来描述各种元件，但是这些元件不应受这些术语限制。这些术语仅用于将一个元件与另一元件相区分，而非用于仅限定元件本身或者意指特定顺序。
还将理解，当元件或层被称为在另一元件或层“上”、“上方”、“下面”、“下方”或“外侧”时，该元件或层可与另一元件或层直接接触，或者可存在中间元件或层。用于描述元件或层之间的关系的其它词语应该以类似的方式解释(例如，“在...之间”与“直接在...之间”或者“相邻”与“直接相邻”之间)。
诸如“在...之下”、“在...下面”、“下”、“上面”、“上”、“顶部”、“底部”等的空间相对术语可用于描述元件和/或特征与另一元件和/或特征的关系(例如，如图中所示)。将理解，除了附图中所描绘的取向之外，空间相对术语旨在涵盖装置在使用和/或操作中的不同取向。例如，当附图中的装置翻转时，被描述为在其它元件或特征下面和/或之下的元件将被取向为在其它元件或特征上面。装置可按照其它方式取向(旋转90度或处于其它取向)并且相应地解释本文中所使用的空间相对描述符。
半导体封装可包括诸如半导体芯片或半导体晶片的电子器件。半导体芯片或半导体晶片可通过使用划片工艺将诸如晶圆的半导体基板分离成多片来获得。半导体芯片可对应于存储器芯片、逻辑芯片(包括专用集成电路(ASIC)芯片)或系统芯片(SoC)。存储器芯片可包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存电路、NOR型闪存电路、磁随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可包括集成在半导体基板上的逻辑电路。半导体封装可用在诸如移动电话的通信系统、与生物技术或保健关联的电子系统或可穿戴电子系统中。
以下将参照附图描述本公开的各种实施方式。贯穿说明书，相同的标号表示相同的元件。即使标号未参照一幅图提及或描述，该标号也可参照另一幅图提及或描述。另外，即使标号未在一幅图中示出，其也可参照另一幅图提及或描述。
图1示出根据实施方式的半导体封装10的平面图。图2是沿着图1的线A-A’截取的横截面图，图3是沿着图1的线B-B’截取的横截面图。图4示出嵌入在图1的半导体封装10中的内置封装100的横截面图。图5是示出没有绝热壁的一般半导体封装10R作为比较例的平面图。
参照图1，半导体封装10可被配置为具有多芯片封装(MCP)形状或球栅阵列固态驱动器(BGA SSD)封装形状。半导体封装10可被配置为包括多个半导体芯片110、200、300和400。半导体芯片110、200、300和400可具有不同的功能。
如果半导体封装10被配置为具有BGA SSD封装形状，则第一半导体芯片110可对应于控制器芯片。在这种情况下，第二半导体芯片200可包括缓冲存储器，第三半导体芯片300可包括构成SSD的非易失性存储器。与控制器芯片对应的第一半导体芯片110可被配置为控制具有BGA SSD封装形状的半导体封装10的总体操作。控制器芯片(即，第一半导体芯片110)可以是系统芯片。控制器芯片110可包括控制缓冲存储器(即，第二半导体芯片200)和非易失性存储器(即，第三半导体芯片300)的操作的逻辑器件。
第四半导体芯片400可包括电源管理集成电路(PMIC)器件。第二半导体芯片200可包括充当缓冲存储器的易失性存储器(例如，DRAM器件)。缓冲存储器可暂时地存储要写到非易失性存储器(即，第三半导体芯片300)中的数据。即，数据可基本上存储在非易失性存储器(即，第三半导体芯片300)中。非易失性存储器(即，第三半导体芯片300)可使用NAND型存储器件来实现。第三半导体芯片300可包括多个层叠物(例如，第一层叠物301和第二层叠物302)以增加第三半导体芯片300的数据存储容量。
第一至第四半导体芯片110、200、300和400可被安装在第一封装基板500上。第一至第四半导体芯片110、200、300和400可被设置在第一封装基板500的顶表面501上。第一至第四半导体芯片110、200、300和400可被设置在第一封装基板500的顶表面501上，其中第一至第四半导体芯片110、200、300和400可彼此间隔开。此外，第二至第四半导体芯片200、300和400可与内置封装100间隔开。此外，至少第一半导体芯片110和第二半导体芯片200可并排设置在封装基板500的表面上。
充当控制器芯片的第一半导体芯片110可利用相对高的驱动电压来操作，并且在操作期间可产生相对大量的热。即，第一半导体芯片110可以是高功率半导体芯片。相比之下，第二半导体芯片200或第三半导体芯片300可以是产生相对少量的热的低功率半导体芯片。例如，充当控制器芯片的第一半导体芯片110可消耗大约1.5瓦的电力，而包括DRAM器件的第二半导体芯片200可消耗大约0.15瓦的电力。此外，第一半导体芯片110可产生比第二半导体芯片200和第三半导体芯片300更大量的热。
参照图1和图2，绝热壁190可被设置在第一半导体芯片110与第二半导体芯片200之间。绝热壁190可被引入到半导体封装10中以将第二半导体芯片200与第一半导体芯片110热隔离。如图3所示，绝热壁190可延伸以将第三半导体芯片300与第一半导体芯片110热隔离。
参照图5，一般半导体封装10R可被示出作为比较例并且可被配置为没有绝热壁190。第一半导体芯片110R可设置在封装基板500R上。第二半导体芯片200R、第三半导体芯片300R和第四半导体芯片400R可设置在第一半导体芯片110R的周边区域处。第一半导体芯片110R可以是在操作期间产生相对大量的热的高功率器件。
第一半导体芯片110R所产生的热可被传导到沿着第一热传导路径802R和第二热传导路径803R设置在第一半导体芯片110R的周边区域处的第二半导体芯片200R和第三半导体芯片300R。因此，由于第一半导体芯片110R所产生的热，第二半导体芯片200R和第三半导体芯片300R的温度可能不期望地升高。
传导到第二半导体芯片200R的热可使第二半导体芯片200R的特性劣化。即，构成第二半导体芯片200R的DRAM器件的特性可能由于传导到第二半导体芯片200R的热而劣化。例如，构成第二半导体芯片200R的DRAM器件中的晶体管可能被从第一半导体芯片110R产生的热加热，从而使DRAM器件的刷新特性、操作速度和可靠性劣化。如果DRAM器件的温度升高，则用于防止DRAM器件的单元数据丢失的刷新操作的循环时间可能减小，从而导致刷新操作的执行次数增加。
另外，传导到第三半导体芯片300R的热可使构成第三半导体芯片300R的NAND型存储器件的特性劣化。例如，如果NAND型器件的温度升高，则NAND型器件的数据保持特性和可靠性可劣化。
再参照图1和图2，绝热壁190可延伸以环绕第一半导体芯片110的周边，如图1所示。当从平面图看时，绝热壁190可具有矩形闭环形状以环绕第一半导体芯片110。因此，绝热壁190可对从第一半导体芯片110的操作产生的热通过与图5所示的第一热传导路径802R和第二热传导路径803R对应的热传导路径传导到第二半导体芯片200和第三半导体芯片300进行阻断。即，绝热壁190可被设置为阻挡从第一半导体芯片110朝着第一半导体芯片110的周边区域的热传导。
由于从第一半导体芯片110朝着第一半导体芯片110的周边区域的热传导被绝热壁190抑制，所以绝热壁190可防止第二半导体芯片200和第三半导体芯片300的特性由于第二半导体芯片200和第三半导体芯片300的温度增加而劣化。
参照图2，绝热壁190可被设置为使得绝热壁190的内侧表面191面向第一半导体芯片110的侧表面113。绝热壁190的内侧表面191可与覆盖第一半导体芯片110的侧表面113的第一模制层710的侧表面713接触。绝热壁190与第一半导体芯片110的侧表面113之间的间隙区域可利用第一模制层710的部分填充。绝热壁190的多个外侧表面193中的一个可面向第二半导体芯片200。绝热壁190的外侧表面193可与第二模制层720接触。绝热壁190的多个外侧表面193中的另一个可面向第三半导体芯片300，如图3所示。
绝热壁190可被设置在第一封装基板500的顶表面501上方，并且可向上延伸，使得绝热壁190的上端195位于与第一模制层710的顶表面711相同的水平处。绝热壁190可向上延伸以到达第二模制层720的顶表面721。第一模制层710的顶表面711可位于与第二模制层720的顶表面721基本上相同的水平处。绝热壁190可延伸以具有高度T2，该高度T2大于第一半导体芯片110的厚度T1，其中绝热壁190可在与第一封装基板500的顶表面501正交的法线相同的方向上延伸。例如，绝热壁190的上端195可在第一模制层710的顶表面711和第二模制层720的顶表面721之间的界面处暴露。绝热壁190的与上端195相对的下端196可位于比第一半导体芯片110的底表面112低的水平处。
绝热壁190可垂直延伸，使得绝热壁190的下端196位于比第一半导体芯片110的底表面112低的水平处，并且绝热壁190的上端195位于比第一半导体芯片110的顶表面111高的水平处。由于绝热壁190的内侧表面191的总面积大于第一半导体芯片110的侧表面113的总面积，所以绝热壁190可有效地阻挡从第一半导体芯片110朝着第二半导体芯片200和第三半导体芯片300传导的热。
第二模制层720可被设置在第一封装基板500的顶表面501上以覆盖第二半导体芯片200、第三半导体芯片300和第四半导体芯片400。第一模制层710可被设置为覆盖第一半导体芯片110的至少一部分。第一模制层710和第二模制层720中的每一个可包括保护材料(例如，环氧模塑化合物(EMC)材料)以保护第一至第四半导体芯片110、200、300和400免受外部环境影响。绝热壁190的下端196可与第一封装基板500的顶表面501间隔开。第二模制层720可延伸以填充绝热壁190的下端196与第一封装基板500的顶表面501之间的间隙。
绝热壁190可包括热导率低于第一模制层710和第二模制层720的热导率的绝热材料。例如，绝热壁190可包括具有大约0.02W/mK至大约0.60W/mK的热导率的绝热材料。绝热壁190可包括具有至多0.4W/mK的热导率的绝热材料。在一些实施方式中，绝热壁190可包括无机绝热材料或有机绝热材料。无机绝热材料可包括粉状碳酸镁、粉状氧化镁、硅酸钙等，有机绝热材料可包括聚氨酯泡沫、聚苯乙烯泡沫等。另选地，绝热壁190可包括二氧化硅气凝胶材料。
再参照图1和图2，绝热壁190可被设置为环绕第一半导体芯片110的侧表面113。因此，通过第一半导体芯片110的操作产生的热可被基本上保持在由绝热壁190环绕的空间中。因此，充当散热器的热导体130可被设置在第一半导体芯片110上以提供将第一半导体芯片110所产生的热传导到半导体封装10的外部区域的热传导路径。
热导体130可附接到第一半导体芯片110，使得热导体130的底表面132与第一半导体芯片110的顶表面111接触。热导体130的与第一半导体芯片110相对的顶表面131可暴露于半导体封装10的外部区域。因此，热导体130可构成将第一半导体芯片110所产生的热传递到半导体封装10的外部区域的第三热传导路径805。结果，第一半导体芯片110所产生的热可通过第三热传导路径805有效地发射到半导体封装10的外部区域。
参照图3，构成第三半导体芯片300的第一层叠物301和第二层叠物302中的每一个可包括垂直地层叠的多个第三半导体晶片310以增加第三半导体芯片300的数据存储容量。第三半导体晶片310可垂直地层叠以提供具有阶梯结构的第一层叠物301或第二层叠物302。第一层叠物301和第二层叠物302中的每一个中的第三半导体晶片310可通过接合线320电连接到第一封装基板500。
热导体130可基本上穿透第一模制层710以充当从第一半导体芯片110的顶表面111延伸到第一模制层710的顶表面711的第三热传导路径805。热导体130可被形成为包括热导率高于第一模制层710的热导率的材料。热导体130可被形成为包括各种导热材料中的至少一种。
热导体130可通过将虚拟芯片附接到第一半导体芯片110来形成。与热导体130对应的虚拟芯片可以是没有任何集成电路的半导体虚拟芯片(例如，硅虚拟芯片)。热导体130的半导体材料(例如，硅材料)的热导率可高于第一模制层710的EMC材料的热导率。因此，第一半导体芯片110所产生的热可通过热导体130有效地发射。用作热导体130的硅虚拟芯片可具有大约149W/mK的相对高的热导率。相比之下，第一模制层710的EMC材料可具有大约3W/mK的热导率，其低于热导体130的热导率。如果热导体130是硅虚拟芯片并且第一半导体芯片110是硅芯片，则热导体130和第一半导体芯片110可具有基本上相同的热膨胀系数。在这种情况下，即使第一半导体芯片110由于操作而变热，在热导体130与第一半导体芯片110之间的界面处也不形成热应力。结果，第一半导体芯片110不会遭受诸如裂缝的缺陷。
尽管图中未示出，热界面材料层可被设置在热导体130与第一半导体芯片110之间以改进热导体130与第一半导体芯片110之间的热传导效率。
再参照图2，第一半导体芯片110可被设置在第一封装基板500上并且可被嵌入在内置封装100中。内置封装100可被配置为包括设置在第一封装基板500上方的第二封装基板150、安装在第二封装基板150的表面上的第一半导体芯片110以及覆盖并保护第一半导体芯片110的第一模制层710，如图2和图4所示。第一模制层710和第二模制层720可被形成为包括基本上相同的材料。即使第一模制层710和第二模制层720分别在两个不同的模制步骤形成，第一模制层710和第二模制层720可构成半导体封装10的模制层。
参照图2和图4，第二封装基板150可包括互连构件以将第一半导体芯片110电连接到第一封装基板500。第二封装基板150可以是印刷电路板(PCB)。第一半导体芯片110和第二封装基板150可通过第一球连接器161彼此电连接。第一封装基板500和第二封装基板150可通过第二球连接器165彼此电连接。
参照图4，可通过在第一模制层710的侧表面713(与内置封装100的侧表面对应)和第一模制层710的顶表面711(与内置封装100的顶表面对应)上沉积绝热膜或绝热层并通过去除绝热膜或绝热层的一部分199以暴露第一模制层710的顶表面711来形成绝热壁190。绝热壁190可覆盖第一模制层710的侧表面713(与内置封装100的侧表面对应)并且可延伸以覆盖第二封装基板150的侧表面153。因此，绝热壁190可延伸以环绕内置封装100的所有侧表面。作为去除绝热膜或绝热层的部分199的结果，绝热壁190可被形成为使第一模制层710的顶表面711(与内置封装100的侧表面对应)暴露。
再参照图2，绝热壁190可被设置在第二模制层720与第一模制层710的侧表面713之间。换言之，第二模制层720可使第一模制层710的顶表面711暴露。热导体130的顶表面131也可在第一模制层710的顶表面711处暴露。热导体130可被设置为基本上穿透第一模制层710的一部分以接触第一半导体芯片110的顶表面111。
内置封装100的第二封装基板150可抑制从第一半导体芯片110到第一封装基板500的热传导。第二封装基板150可包括具有相对低的热导率的有机材料。因此，第二封装基板150可更有效地抑制从第一半导体芯片110到第二半导体芯片200和第三半导体芯片300的热传导。
此外，第二球连接器165可附接到第一封装基板500的顶表面501，第三球连接器600可附接到第一封装基板500的与第二球连接器165相对的底表面502。第三球连接器600可充当将半导体封装10电连接到外部装置或外部系统的连接构件。
根据上述实施方式，绝热壁可被设置在半导体封装中以将包括在半导体封装中的高功率半导体芯片与包括在半导体封装中的至少一个低功率半导体器件热隔离。
图6是示出包括采用根据实施方式的多个半导体封装中的至少一个的存储卡7800的电子系统的框图。存储卡7800可包括诸如非易失性存储器装置的存储器7810以及存储控制器7820。存储器7810和存储控制器7820可存储数据或者读出所存储的数据。存储器7810和存储控制器7820中的至少一个可包括根据实施方式的多个半导体封装中的至少一个。
存储器7810可包括应用了本公开的实施方式的技术的非易失性存储器装置。存储控制器7820可控制存储器7810，使得响应于来自主机7830的读/写请求，读出所存储的数据或者存储数据。
图7是示出包括根据实施方式的多个半导体封装中的至少一个的电子系统8710的框图。电子系统8710可包括控制器8711、输入/输出单元8712和存储器8713。控制器8711、输入/输出单元8712和存储器8713可通过提供数据移动的路径的总线8715彼此联接。
在实施方式中，控制器8711可包括微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同的功能的逻辑器件中的一个或更多个。控制器8711或存储器8713可包括根据本公开的实施方式的多个半导体封装中的至少一个。输入/输出单元8712可包括选自键区、键盘、显示装置、触摸屏等中的至少一个。存储器8713是用于存储数据的装置。存储器8713可存储要由控制器8711执行的数据和/或命令等。
存储器8713可包括诸如DRAM的易失性存储器装置和/或诸如闪存的非易失性存储器装置。例如，闪存可被安装到诸如移动终端或台式计算机的信息处理系统。闪存可构成固态盘(SSD)。在这种情况下，电子系统8710可在闪存系统中稳定地存储大量数据。
电子系统8710还可包括被配置为向通信网络发送数据以及从通信网络接收数据的接口8714。接口8714可为有线或无线型。例如，接口8714可包括天线或者有线或无线收发器。
电子系统8710可被实现为移动系统、个人计算机、工业计算机或者执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任一个。
如果电子系统8710是能够执行无线通信的设备，则电子系统8710可用在使用诸如CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDAM(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信系统中。
出于例示性目的公开了本公开的实施方式。本领域技术人员将理解，在不脱离本公开和所附权利要求的范围和精神的情况下，可进行各种修改、添加和替换。
相关申请的交叉引用
本申请要求2017年10月27日提交的韩国申请No.10-2017-0141341的优先权，其整体通过引用并入本文。

Claims (17)

1.一种半导体封装，该半导体封装包括：
第一封装基板；
内置封装，该内置封装被设置在所述第一封装基板上并被配置为包括第一半导体芯片以及用于将所述第一半导体芯片热隔离的绝热壁；以及
第二半导体芯片，该第二半导体芯片被设置在所述第一封装基板上以与所述内置封装间隔开，
其中，所述内置封装还包括填充所述第一半导体芯片与所述绝热壁之间的间隙的第一模制层，并且
其中，所述内置封装还包括热导体，所述热导体与所述第一半导体芯片接触并且在所述第一模制层的表面上被暴露。
2.根据权利要求1所述的半导体封装，
其中，所述内置封装还包括设置在所述第一封装基板上方的第二封装基板，并且
其中，所述第一半导体芯片被安装在所述第二封装基板上并由所述第一模制层覆盖。
3.根据权利要求1所述的半导体封装，其中，所述绝热壁包括热导率低于所述第一模制层的热导率的绝热材料。
4.根据权利要求3所述的半导体封装，其中，所述绝热壁具有0.4W/mK或更小的热导率。
5.根据权利要求1所述的半导体封装，其中，所述热导体包括热导率高于所述第一模制层的热导率的材料。
6.根据权利要求5所述的半导体封装，其中，所述热导体包括硅虚拟芯片。
7.根据权利要求1所述的半导体封装，该半导体封装还包括第二模制层，该第二模制层覆盖所述第一封装基板和所述第二半导体芯片并使所述第一模制层的顶表面暴露。
8.根据权利要求7所述的半导体封装，其中，所述绝热壁延伸，使得所述绝热壁的上端在所述第二模制层的顶表面处暴露。
9.根据权利要求7所述的半导体封装，其中，所述绝热壁被设置在所述第二模制层与所述内置封装的至少一个侧表面之间。
10.根据权利要求1所述的半导体封装，其中，所述绝热壁延伸，使得所述绝热壁的下端位于比所述第一半导体芯片的底表面低的水平处。
11.根据权利要求1所述的半导体封装，其中，所述绝热壁延伸以环绕所述内置封装的所有侧表面。
12.根据权利要求1所述的半导体封装，其中，所述第一半导体芯片是比所述第二半导体芯片产生更大量的热的高功率芯片，其中，所述第二半导体芯片是低功率芯片。
13.根据权利要求1所述的半导体封装，该半导体封装还包括被设置为与所述第二半导体芯片间隔开的第三半导体芯片，
其中，所述第二半导体芯片包括构成缓冲存储器的易失性存储器，
其中，所述第三半导体芯片包括构成固态驱动器SSD的非易失性存储器，并且
其中，所述第一半导体芯片包括控制所述缓冲存储器和所述固态驱动器的操作的控制器芯片。
14.一种半导体封装，该半导体封装包括：
并排设置在封装基板的表面上以彼此间隔开的第一半导体芯片和第二半导体芯片；
覆盖所述第一半导体芯片的第一模制层；
覆盖所述第二半导体芯片的第二模制层；
设置在所述第一模制层与所述第二模制层之间以将所述第一半导体芯片热隔离的绝热壁；以及
热导体，所述热导体穿透所述第一模制层以与所述第一半导体芯片接触并且在所述第一模制层的表面上被暴露。
15.根据权利要求14所述的半导体封装，其中，所述绝热壁延伸，使得所述绝热壁的上端在所述第一模制层和所述第二模制层的顶表面处暴露。
16.根据权利要求14所述的半导体封装，其中，所述绝热壁延伸，使得所述绝热壁的下端位于比所述第一半导体芯片的底表面低的水平处。
17.根据权利要求14所述的半导体封装，其中，所述绝热壁延伸以环绕所述第一半导体芯片。
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