CN107026155A - 混合系统 - Google Patents

混合系统 Download PDF

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Publication number
CN107026155A
CN107026155A CN201610940076.1A CN201610940076A CN107026155A CN 107026155 A CN107026155 A CN 107026155A CN 201610940076 A CN201610940076 A CN 201610940076A CN 107026155 A CN107026155 A CN 107026155A
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CN
China
Prior art keywords
crystal grain
dynamic random
random access
access memory
memory crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201610940076.1A
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English (en)
Inventor
张圣明
张峻玮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
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Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN107026155A publication Critical patent/CN107026155A/zh
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
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    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
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    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G11C14/0018—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
    • G—PHYSICS
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Abstract

本发明实施例公开了一种混合系统，包括：电路板，具有主表面；封装上封装，含有底部封装，安装于该电路板的该主表面上，以及顶部封装，堆叠在该底部封装上，其中，该底部封装包括：片上系统，以及该顶部封装包括至少一个能够被该片上系统存取的封装上动态随机存取存储器晶粒；以及多芯片封装，直接安装在该电路板的该主表面上，其中该多芯片封装包括至少一个板上动态随机存取存储器晶粒，能够被该片上系统经由电路板走线来存取。本发明实施例，可以确保存储密度的同时，不用受PoP的高度限制或者遭受MCP字节方式的速度衰减。

Description

混合系统
技术领域
本发明涉及半导体封装技术，尤其涉及一种混合系统。
背景技术
近来，电子产品趋于具有更高的效率以及更小的体积。因此，持续地微型化安装于PCB上的半导体芯片的尺寸，同时不断增大PCB上传送的电子信号的频率。
现代的个人电子设备，诸如移动电话，一般具有高整合度和低功耗设计。这些设备使用SoC(System-on-Chip，片上系统)，PoP(Package-on-Package，封装上封装或堆叠封装)以及非易失性NAND(与非门)闪存。SoC将多种功能整合于一个芯片上，诸如通用处理，加速处理，存储控制和通信连接。为了满足普通移动设备严格的功率和空间约束，这些芯片将CPU(Central Processing Unit，中央处理单元)与其他元件组合为单个紧凑的物理封装。
一些计算系统在他们的主存储器中使用DRAM(Dynamic Random Access Memory，动态随机存取存储器)IC(Integrated Circuit，集成电路)。如本领域所知，DRAM通过在每个记忆单元中的电容上存储一定数量的电荷来存储逻辑“1”或者逻辑“0”，从而维持信息。
近来，高密度的LPDDR4(The 4th Generation of Low Power Double Data Rate，第4代低功耗双倍数据速率)DRAM已引入到移动平台上。为了保证系统性能，存储控制器的IP(Intellectual Property，知识产权)提供者通常定义了封装和PCB设计约束以降低产品风险。这些设计约束可能会增加封装尺寸和LPDDR4PCB的面积，从而提高整个系统成本。
为了得到更高密度的存储器，可将更多的DRAM芯片堆叠在PoP SoC中，但是由于更多的DRAM芯片堆叠在PoP SoC中，因此不可避免地增加了PoP SoC的整体高度。在不久的将来，由于高端产品将变得越来越薄，因此PoP SoC可能不符合这些高端产品的严格空间约束。对于MCP(多芯片封装)产品，当前的主流产品为2通道/32位MCP。使用字节方式(byte-mode)/更小的晶粒可能是得到更高密度的解决方案。但是，字节方式操作也将限制DRAM重加载CA(Command/Address，指令/地址)信号的运行速度。
发明内容
有鉴于此，本发明实施例提供了一种混合系统，可以确保存储密度的同时，不用受PoP的高度限制或者遭受MCP字节方式的速度衰减。
本发明实施例提供了一种混合系统，包括：电路板，具有主表面；封装上封装，含有底部封装，安装于该电路板的该主表面上，以及顶部封装，堆叠在该底部封装上，其中，该底部封装包括：片上系统，以及该顶部封装包括至少一个能够被该片上系统存取的封装上动态随机存取存储器晶粒；以及多芯片封装，直接安装在该电路板的该主表面上，其中该多芯片封装包括至少一个板上动态随机存取存储器晶粒，能够被该片上系统经由电路板走线来存取。
其中，该片上系统在该底部封装中整合了至少一个中央处理单元和图像处理单元。
其中，该片上系统包括：存储控制器，用于从该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒读取数据，和将数据写入该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒。
其中，该电路板走线为存储器总线。
其中，该多芯片封装整合了该板上动态随机存取存储器晶粒和闪存。
其中，该闪存包括：内嵌式多媒体卡或者通用闪存。
其中，该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒均为易失性存储器晶粒及均具有双倍数据速率架构。
其中，该封装上动态随机存取存储器晶粒为第四代低功耗双倍数据速率存储器晶粒，并且该板上动态随机存取存储器晶粒为第四代双倍数据速率存储器晶粒。
其中，该封装上动态随机存取存储器晶粒没有延迟锁相环，并且该板上动态随机存取存储器晶粒具有至少一个延迟锁相环。
其中，该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒分别电性连接至的用于指令和地址的信号引脚的数量不同。
其中，该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒具有不同的用于输入和输出的电源电压。
本发明实施例的有益效果是：
本发明实施例的混合系统，整合了PoP和MCP，因此在确保存储密度的同时，能够不用受PoP的高度限制或者遭受MCP字节方式的速度衰减。
附图说明
包含附图以提供对本发明的进一步理解，并且该附图纳入并构成本说明书的一部分。该附图示意了本发明的实施例，并且连同以下描述一起来解释本发明的原理。在附图中：
图1是根据本发明一个实施例的混合系统的横截面的示意图；
图2是根据本发明一个实施例的混合系统的布局示意图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本申请说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式，而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
可以理解的是，当将诸如“层”、“区域”或“基底”等元件称为“在另一元件上”或者“延伸至另一元件上”时，那么该元件可以是直接在其他元件上或者直接延伸至其他元件上或者也可以存在中间元件。相反地，当将元件称为“直接在”或者“直接延伸至”另一元件上时，则没有中间元件存在。也可以理解的是，当将元件称为“连接”或“耦接”到另一元件时，那么该元件可以直接连接或者直接耦接至另一元件或者可以存在中间元件。相反地，当将元件称为“直接连接”或者“直接耦接”至另一元件，则没有中间元件存在。
可以在此中使用诸如“以下”、“以上”、“上面”、“下面”、“水平”、“横向”或者“垂直”等相对术语，以描述附图中示意的一个元件、层或者区域相对另一元件、层或者区域的关系。可以理解的是，这些术语旨在涵盖除了附图中描述的方位以外的其他方位。
本发明提供了一种混合系统，可以将PoP SoC与eMCP(embedded multi-chippackage，内嵌式多芯片封装)整合至一个用于移动应用的主电路板或者PCB(PrintedCircuit Board，印刷电路板)。
本发明关于一种混合系统，具有安装于相同的PCB或者主电路板上的封装上(on-package)DRAM晶粒和板上(on-board)DRAM晶粒。该板上DRAM晶粒可以由SoC中的存储控制器或者处理器经由PCB走线或者PCB上的存储器总线来存取。
图1是根据本发明一个实施例的混合系统的横截面示意图。图2是图1所示的混合系统的布局示意图。如图1和2所示，混合系统1包括：PCB或者主电路板(可统称为电路板)10。该PCB10机械地支撑电子元件以及使用导电轨道(track)、走线(trace)、接垫和其他的由层压在非导电基底上的铜片蚀刻成的结构来电性连接电子元件。根据设计要求，PCB10可以为单侧(一个铜层)，双侧(两个铜层)或者多层(外层和内层)。多层PCB允许高得多的元件密度。不同层上的导体使用金属化孔(plated-through hole)或者通孔(vias)来连接。
根据本实施例，PCB10可以包含诸如电容、电阻或者主动元件等嵌入于基底中的元件。电路板基底一般由介电复合材料构成。该复合材料包括：基质(一般为环氧树脂)、强化材料(一般为织物，有时非织物，玻璃纤维)，以及在一些情形中，将填充物添加至树脂中，诸如陶瓷。可以理解的是，为了简单起见，没有示出PCB10的详细结构。
根据本实施例，PoP(封装上封装)20直接安装于该PCB10的主表面上。根据本实施例，PoP20垂直地组合离散的SoC和存储器封装。根据本实施例，PoP20在3D(三维)结构中堆叠多个芯片，该3D结构允许密集的封装并且用于将处理器顶上的存储器形成PoP SoC配置。两个或者更多的封装使用标准接口来安装(即垂直堆叠)于彼此的顶上，以在他们之间路由信号。
根据本实施例，PoP20包括：含有SoC211的底部封装21，该SoC211整合了一个或更多的CPU、GPU(Graphics Processing Unit，图像处理单元)、高速缓冲存储器(cachememory)、和/或其他需要在单个物理封装中提供计算功能的电子元件。根据本实施例，SoC211可以进一步包括：存储控制器，用于从存储器读取数据和写入数据至存储器。根据本实施例，SoC211可以采取BGA(Ball Grid Array，球栅阵列)的方式来封装，但是不限制于此，例如SoC211也可能采用WLP(Wafer Level Package，晶圆级封装)或者扇出式WLP的方式来封装。
根据本实施例，SoC211可以密封在模塑料216内。底部封装21可以通过PoP20的连接元件(也可称为“导电结构”)250直接附着到PCB10的主表面上。连接元件250可以为焊料球，但是不限制于此，例如连接元件250也有可能是焊料凸块或者铜柱凸块。根据本实施例，SoC211的基底210设置在导电结构250和SoC211之间，并且可以为RDL(RedistributionLayer，重分布层)。
根据本实施例，顶部封装22直接安装在底部封装21上。顶部封装22具有至少一个DRAM晶粒(封装上DRAM存储器晶粒)。例如，在本实施例中示出了两个DRAM晶粒221和222。根据本实施例，DRAM晶粒221和222为DDR(Double Data Rate，双倍数据速率)DRAM晶粒，例如为32位LPDDR4-3200Mbps DRAM晶粒，但是不限制于此。可以理解的是，可以使用其他类型的DDR DRAM，例如双通道DDR DRAM或者四通道DDR DRAM，但是不限制于此。DRAM晶粒221和222作为主存储器，以处理SoC211中的处理器的数据。
根据本实施例，DRAM晶粒221和222使用插入在他们之间的垫片(spacer)242来垂直地堆叠在封装基底220上。根据本实施例，DRAM晶粒221和222可以分别通过接合线231和232电性连接至封装基底220。可以理解的是，DRAM晶粒221和222与封装基底220之间的电性连接仅是出于说明目的。在其他实施例中可以使用其他合适的电性连接方案，诸如TSV。根据本实施例，DRAM晶粒221和222，接合线231和232，以及封装基底220的上表面由模塑料226密封和覆盖。
根据本实施例，顶部封装22通过多个连接元件260附着至底部封装21的顶部，诸如焊球、凸块或者柱。这些连接元件260可以通过各自的TMV(Through Mold Vias，穿模通孔)218电性耦接至基底210。SoC211可以通过基底210、TMV218、连接元件260、封装基底220和接合线231和232构成的路径来存取DRAM晶粒221和222。
根据本实施例，诸如eMCP(内嵌式MCP)等MCP30以接近PoP20的方式安装在PCB10的主表面上，例如通过一个或更多的导电结构350安装在PCB10的主表面上。MCP30包括：至少一个DRAM晶粒(板上DRAM存储器晶粒)。例如，本实施例示出了两个DRAM晶粒301和302。根据实施例，DRAM晶粒301和302为DDR DRAM晶粒，例如32位LPDDR4-3200Mbps DRAM晶粒，但是不限制于此。可以理解的是，可以使用其他类型的DDR DRAM，例如双通道DDR DRAM或者四通道DDR DRAM，但是不限制于此。类似于DRAM晶粒221和222，DRAM晶粒301和302也作为主存储器，以处理SoC211中的处理器的数据。在PCB10中可以提供存储器总线(PCB走线)102，使得数据或信号可以在PoP20和MCP30之间传达。
根据本实施例，DRAM晶粒301和302与插入在他们之间的垫片342垂直地堆叠在封装基底320上。根据本实施例，DRAM晶粒301和302可以分别通过接合线331和332电性连接至封装基底320。可以理解的是，DRAM晶粒301和302与封装基底320之间的电性连接仅是出于说明目的。在其他实施例中可以使用其他合适的电性连接方案，诸如TSV。根据本实施例，DRAM晶粒301和302，接合线331和332，以及封装基底320的上表面由模塑料326密封。
根据另一实施例，MCP30可以为用于移动存储器的封装型的eMCP，该eMCP将移动DRAM和闪存整合至一个芯片封装中，其中该闪存包括：内嵌式多媒体卡(embedded Multi-Media-Card，eMMC)、或者通用闪存(Universal Flash Storage，UFS)。例如，MCP可以包括：移动DDR和eMMC。在此情形中，图1所示的DRAM晶粒301和302之一可以由闪存替换。闪存可以为NOR(非或)闪存或者NAND(与非)闪存，在NOR闪存中，单元阵列具有NOR结构，而在NAND闪存中，单元阵列具有NAND结构。提供NOR闪存或者NAND闪存以便于存储既使掉电也不会被移除的数据，诸如移动设备的启动代码(boot code)，程序，通信数据，或者存储数据。闪存在各式设备中使用，包括移动电话、数字照相机和便携式计算器。SoC211可以包括：存储控制器，用于从闪存中读取数据和写入数据至闪存中。
通过提供图1和图2所示的配置，SoC211可以通过不同的存取路径(PoP20内的路径和PoP20外的路径)来存取DRAM芯片或者晶粒221，222，301和302。SoC211可以通过由基底210，连接元件260，封装基底220和接合线231与232构成的路径来存取DRAM芯片或者晶粒221和222。SoC211可以通过PCB10中的存储器总线(PCB走线)102存取DRAM芯片或晶粒301和302。SoC211中的处理器可以经由存储器总线102耦接至一个或更多的存储器通道中的DRAM芯片或晶粒301和302。
当相比于仅PoP的传统平台或者仅MCP的传统平台，由PoP20和MCP30构成的混合平台(也可称为混合系统)1确保了更大的密度。例如，8GB DRAM的仅PoP的传统平台现在可划分为以上描述的使用先进的工艺技术的混合系统1的4GB-PoP和4GB-MCP，而不用受PoP的高度限制或者遭受MCP字节方式的速度衰减。
在一些实施例中，顶部封装22中的DRAM和MCP30中的DRAM之间的差别包括但不限于：存取延迟，存储器设备在DRAM中是否包括DLL(Delay-Locked Loop，延迟锁相环)，指令和地址引脚的数量，每封包的数据大小，拓扑结构，最大频率，突发长度(burst length)，RAS(Row Adress Strobe，列地址控制器)，VDDQ(即，至输入和输出的电源电压)。
例如，在顶部封装22中的DRAM为LPDDR4(第4代LPDDR)存储器且MCP30中的DRAM为DDR4存储器的实施例中，差别可以包括但不限于下述：LPDDR4在DRAM中不具有DLL，但是DDR4具有至少一个DLL；LPDDR4具有6个信号引脚用于指令和地址，而DDR4具有22个此类引脚；LPDDR4每封包的数据大小为x16/x32/x64(“x”表示“倍”并且“/”表示“或”)，而DDR4每封包的数据大小为x4/x8；LPDDR4的拓扑结构为点至点(point-to-point)，而DDR4为DIMM(Dual-Inline Memory Module，双列直插式存储器模块)；LPDDR4的最大频率为4266MT/s，而DDR4为3200MT/s(其中MT/s表示百万次每秒)；LPDDR4的突发长度为16或32，而DDR4为8；LPDDR4没有RAS支持，而DDR4具有数据CRC(Cyclic Redundancy Check，循环冗余检查)和指令/地址奇耦性；LPDDR4操作在1.1v的VDDQ，而DDR4操作在1.2v的VDDQ。另外，对于存取延迟，LPDDR4在大数据转移方面胜过DDR4；例如当数据转移大小大于阈值时，例如大约570字节。如此，LPDDR4更适合于I/O密集型工作负载数据，而DDR4更适合于计算密集型工作负载数据。
在一些实施例中，顶部封装22中的DRAM和MCP30中的DRAM尽管具有上述的不同，但是具有许多相似性。这些相似性可以包括但不限制于：字节可寻址性，易失性存储器，用于存取存储器的指令和地址协议，双倍数据速率架构(即，每频率转移两个数据)，差分频率输入和数据选通。诸如顶部封装22的DRAM和MCP30中的DRAM分别为LPDDR4和DDR4的示例。尽管使用LPDDR4和DDR4来作为示例，但是可以理解的是，顶部封装22中的DRAM和MCP30中的DRAM可以为任意合适的具有上述的一个或更多的差别以及上述的一个或更多相似性的存储器设备。
在一个实施例中，顶部封装22中的DRAM可以为LPDDR存储器设备，诸如LPDDR4或另一代的LPDDR存储器设备。在一个实施例中，MCP30中的DRAM可以为DDR存储器设备，诸如DDR4或者另一代的DDR存储器设备。
LPDDR是一类操作在低电源电压以降低功耗的SDRAM(Synchronous DRAM，同步DRAM)。移动设备已广泛地采用LPDDR，其中功率消耗是移动设备的主要问题。如前述，LPDDR和DDR均为字节可寻址，并且均为需要每隔几微秒刷新一次以保持内容的易失性存储器设备。LPDDR的一个优势在于比对应代的DDR消耗更少的电量。例如，最新代的LPDDR4操作在1.1v，低于具有1.2v标准电压的DDR4。LPDDR4也支持改进的节电低频模式，当执行单个后台任务时，该改进的节电低频模式能够促使时钟速率下降以进一步节约电量。经验结果显示：在各式使用模式(诸如主动预充电、主动待机、突发读、突发写等)下，LPDDR4比DDR4可以节约33％～87％的电量。LPDDR4和DDR4之间的额外的相似性和不同已在前面描述。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种混合系统，其特征在于，包括：
电路板，具有主表面；
封装上封装，含有底部封装，安装于该电路板的该主表面上，以及顶部封装，堆叠在该底部封装上，其中，该底部封装包括：片上系统，以及该顶部封装包括至少一个能够被该片上系统存取的封装上动态随机存取存储器晶粒；以及
多芯片封装，直接安装在该电路板的该主表面上，其中该多芯片封装包括至少一个板上动态随机存取存储器晶粒，能够被该片上系统经由电路板走线来存取。
2.如权利要求1所述的混合系统，其特征在于，该片上系统在该底部封装中整合了至少一个中央处理单元和图像处理单元。
3.如权利要求1所述的混合系统，其特征在于，该片上系统包括：存储控制器，用于从该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒读取数据，和将数据写入该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒。
4.如权利要求1所述的混合系统，其特征在于，该电路板走线为存储器总线。
5.如权利要求1所述的混合系统，其特征在于，该多芯片封装整合了该板上动态随机存取存储器晶粒和闪存。
6.如权利要求5所述的混合系统，其特征在于，该闪存包括：内嵌式多媒体卡或者通用闪存。
7.如权利要求1所述的混合系统，其特征在于，该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒均为易失性存储器晶粒及均具有双倍数据速率架构。
8.如权利要求1所述的混合系统，其特征在于，该封装上动态随机存取存储器晶粒为第四代低功耗双倍数据速率存储器晶粒，并且该板上动态随机存取存储器晶粒为第四代双倍数据速率存储器晶粒。
9.如权利要求1所述的混合系统，其特征在于，该封装上动态随机存取存储器晶粒没有延迟锁相环，并且该板上动态随机存取存储器晶粒具有至少一个延迟锁相环。
10.如权利要求1所述的混合系统，其特征在于，该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒分别电性连接至的用于指令和地址的信号引脚的数量不同；
和/或者，该封装上动态随机存取存储器晶粒和该板上动态随机存取存储器晶粒具有不同的用于输入和输出的电源电压。
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