CN101510543A - 集成半导体器件 - Google Patents

集成半导体器件 Download PDF

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CN101510543A
CN101510543A CNA200910007167XA CN200910007167A CN101510543A CN 101510543 A CN101510543 A CN 101510543A CN A200910007167X A CNA200910007167X A CN A200910007167XA CN 200910007167 A CN200910007167 A CN 200910007167A CN 101510543 A CN101510543 A CN 101510543A
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chip
integrated
electrode
semiconductor device
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CN101510543B (zh
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山田浩
板谷和彦
小野塚丰
舟木英之
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Abstract

本发明涉及一种集成半导体器件，其包括：多个半导体元件，具有不同的集成元件电路或不同的尺寸；绝缘材料，设置在所述半导体元件之间；有机绝缘膜，完全设置在所述半导体元件和所述绝缘材料上；细薄层布线，设置在所述有机绝缘膜上，且连接所述半导体元件；第一输入/输出电极，设置在所述绝缘材料的区域上；以及第一凸起电极，形成在所述第一输入/输出电极上。

Description

集成半导体器件
相关申请的交叉引用
本申请基于并要求于2008年2月14日提交的在先日本专利申请No.2008-32594的优先权，在此引入其全部内容以作参考。
技术领域
本发明涉及一种在其上安装多个半导体芯片的集成半导体器件。
背景技术
在近来的集成半导体器件工艺中，已发展了高密度集成技术，且相应地对于组成集成半导体器件的半导体元件要求高集成度。尤其在用于集成半导体器件的新近技术中，对于微机电系统(MEMS)以及大规模集成(LSI)电路都要求高集成度。
MEMS包括具有通过硅微制造工艺制造的微结构的机电部件。期望MEMS广泛应用于诸如压力传感器、加速传感器以及RF滤波器的电子部件领域中。为了将MEMS和LSI集成在一起，已经研发了高密度三维封装技术来作为MEMS-LSI集成技术中的一种，其中利用MEMS-LSI集成技术将LSI与MEMS一个叠置在另一个上。然而，在这种封装中，必须在LSI与MEMS中形成垂直通孔，这使器件制造成本上升。因此，需要将它们集成在同一平面上的技术，该技术不必形成垂直通孔。
在单个平面上的集成技术包括两种主要的方法：芯片上系统(SOC)和封装内系统(SIP)。SOC是一种通过在单个芯片上形成多个元件的封装方法。SOC方法可以提高元件的密度，但对被集成的元件有限制。例如，由于器件制造工艺不兼容，Si器件不能集成诸如GaAS的不同器件类型的元件。此外，SOC为设计和实现新元件需要长的时间，这增加器件研发成本。
另一方面，利用SIP方法，单独地(individually)制备多个LSI芯片和MEMS芯片，且然后将它们集成在插入式电路板上。在SIP中，由于单独地制备元件，因此对并入的元件没有限制。此外，在研发新系统的情况下，可以使用常规芯片，从而可以缩短设计所需要的时间周期且因此可以减少器件研发成本。然而，封装密度依赖于在其上安装LSI芯片和MEMS芯片的插入式电路板，且因此很难提高器件封装密度。
为了解决上述问题，例如，JP-A 2007-260866(KOKAI)提出在检查和筛选之后将通过单独的制造技术制备的LSI和MEMS晶片切成芯片，然后将芯片并排地重新排列并重新布置成MEMS集成晶片。通过允许由不同制造工艺制备的各种类型的元件的集成以及在大的面积上仅重新排列已通过检查的操作元件，该重新布置的MEMS晶片使得制造成本降低。另外，通过细布线层使在重新布置的MEMS晶片上的LSI和MEMS互相电连接。伪SOC技术可以提供常规SIP无法实现的高封装密度和常规SOC无法实现的不同类型元件的集成，其中利用该伪SOC技术，LSI和MEMS以芯片级(at chip level)重新排列，且被重新布置为MEMS集成晶片。
然而，利用伪SOC技术，当通过倒装芯片技术将伪SOC芯片安装在电路布线板上时，由于电路布线板与伪SOC芯片的热膨胀系数之间的差异，伪SOC芯片会变形。于是，绝缘和支撑不同类型元件的有机树脂会破裂。更具体地，由于通过使用设置在伪SOC芯片周边上的凸起电极而倒装安装的伪SOC芯片的热膨胀系数与安装伪SOC芯片的电路布线板的热膨胀系数之间的差异，出现位移差。这种位移差导致伪SOC芯片中的翘曲(warp)，并且设置在伪SOC芯片的不同类型器件之间的有机树脂通过应力而最终使破裂。破裂的主要原因在于，为了通过不在半导体元件上设置凸起电极而减小寄生电容且为了减轻凸起电极高跨比(pitch)，在伪SOC芯片周边上设置了I/O电极。
发明内容
根据本发明的一方面，一种集成半导体器件包括：多个半导体元件，具有不同的集成元件电路或不同的尺寸；绝缘材料，设置在所述半导体元件之间；有机绝缘膜，完全设置在所述半导体元件和所述绝缘材料上；细薄层布线，设置在所述有机绝缘膜上，且连接所述半导体元件；第一输入/输出电极，设置在所述绝缘材料的区域上；以及第一凸起电极，形成在所述第一输入/输出电极上。
附图说明
图1是根据本发明实施例的集成半导体器件的顶视图；
图2是沿着A-A截取的图1的器件的截面图；
图3是常规的集成半导体器件的顶视图；
图4是沿着A-A截取的图3的器件的截面图；
图5是倒装芯片安装在电路布线板上的常规半导体器件的截面图；
图6是倒装芯片安装在电路布线板上的根据本实施例的集成半导体器件的截面图；
图7A到7M是根据本实施例的集成半导体器件在制造工艺中的截面图；以及
图8是根据本实施例的修改例的集成半导体器件的截面图。
具体实施方式
下面参考附图详细说明本发明的示例性实施例。为了方便，可以按照不同的比例来描绘附图中的部件。还应当注意，在图1中，为了方便，以实线形式示例出包含于集成半导体器件1中的LSI芯片2、MEMS芯片3和绝缘材料4以及在集成半导体器件1的表面上的凸起电极5。
如图1和2中所示，通过以芯片级重新排列LSI芯片2和MEMS芯片3并通过使用伪SOC技术将它们重新布置为MEMS集成晶片，来制备集成半导体器件(伪SOC芯片)1。在这种结构中不设置使LSI芯片2、MEMS芯片3等互相电互连的布线板(插入式基底)。实际上，通过将作为MEMS集成晶片的伪SOC晶片切割成单独的芯片来形成集成半导体器件(伪SOC芯片)1。集成半导体器件(伪SOC芯片)1包括LSI芯片2、MEMS芯片3、绝缘材料4、凸起电极5、接触部分(接触过孔)6、有机绝缘膜7、细薄层布线(总体层，global layer)8、有机绝缘膜9、I/O电极10、MEMS封装材料11、以及MEMS腔12。
通过对在其上形成有LSI半导体元件的晶片进行测试和筛选并将该晶片切割成芯片，获得LSI芯片2。通过对在其上形成有MEMS机电元件的晶片进行测试和筛选并将该晶片切割成芯片，获得MEMS芯片3。在图1和2的实例中，集成半导体器件(伪SOC芯片)1承载五个LSI芯片2(两个CPU、两个驱动器、以及一个存储器)和一个MEMS芯片3。LSI芯片2是与MEMS芯片3类型不同的元件。这里为了便于说明，采用上述结构，但是安装在集成半导体器件(伪SOC芯片)1上的LSI芯片2和MEMS芯片3的数量不限于该实例。
在LSI芯片2和MEMS芯片3的每一个之间，且如果必需，在LSI芯片2和MEMS芯片3下方以及集成半导体器件(伪SOC芯片)1的周边中，设置绝缘材料4。绝缘材料4由此使LSI芯片2和MEMS芯片3互相绝缘且使这些芯片互相固定。绝缘材料4由有机树脂形成。更具体地，其优选包括含有硅石填充物的环氧树脂、聚酰亚胺树脂、以及苯并环丁烯(BCB)的至少一种。
凸起电极5将集成半导体器件(伪SOC芯片)1电气且机械地连接到稍后将描述的电路布线板200。凸起电极5设置在集成半导体器件(伪SOC芯片)1的LSI芯片2和MEMS芯片3之间的绝缘材料4的顶表面上，或更具体地，设置于形成在绝缘材料4的区域中的I/O电极10的顶表面上。根据该设计，可以将有机绝缘膜7、细薄层布线8、以及有机绝缘膜9形成在凸起电极5(I/O电极10)和绝缘材料4之间。无论是何设计，根据本发明，凸起电极5(I/O电极10)应总是设置在绝缘材料4之上。优选地，这些凸起电极5由包含Ti、Ni、Al、Cu、Au、Ag、Pb、Sn、Pd和W中的至少一种的金属形成，或由这些金属的任意合金形成。
在LSI芯片2和MEMS芯片3的顶表面上设置接触部分6，以在LSI芯片2和细薄层布线8之间以及在MEMS芯片3和细薄层布线8之间建立电连接。
有机绝缘膜7使LSI芯片2和MEMS芯片3与细薄层布线8电绝缘。将有机绝缘膜7设置在除了其接触部分6之外的LSI芯片2上以及除了其接触部分6之外的MEMS芯片3上。有机绝缘膜7可以由聚酰亚胺树脂形成。
将细薄层布线8设置在接触部分6和有机绝缘膜7的顶表面上，以在LSI芯片2和MEMS芯片3之间建立电连接。特别地，优选地，细薄层布线8由包含Ti、Ni、Al、Cu、Au、Pb、Sn、Pd和W中的至少一种的金属形成，或由这些金属的任意合金形成。
将有机绝缘膜9设置在除了其中形成I/O电极10的区域之外的细薄层布线8的顶表面上，以保护细薄层布线8。有机绝缘膜9可以由聚酰亚胺树脂形成。值得注意的是，根据该设计，可以将细薄层布线8和有机绝缘膜9的多个层沉积为有机绝缘膜7上的多层布线，来取代各用于细薄层布线8和有机绝缘膜9的一层。
将I/O电极10设置在细薄层布线8的顶表面上，以在其上形成凸起电极5且由此将凸起电极5电连接到细薄层布线8。更具体地，将I/O电极10设置在集成半导体器件(伪SOC芯片)1的LSI芯片2和MEMS芯片3之间的绝缘材料4的区域上。可以将I/O电极10不完全沉积在绝缘材料4的区域上且可以部分设置在细薄层布线8和有机绝缘膜7上。然而，总是将I/O电极10沉积在LSI芯片2和MEMS芯片3之间的绝缘材料4的区域上方。对于形成在I/O电极10上的凸起电极5，可以使用Cu/Ni/Ti或Cu/Ti作为阻挡金属。
MEMS封装材料11密封MEMS芯片3的MEMS可移动部分，且MEMS腔12是被MEMS芯片3和MEMS封装材料11包围的开口，MEMS可移动部分被设置于其中。
下面与常规集成半导体器件的设置相比较来说明集成半导体器件(伪SOC芯片)1的上述设置。在图3中，为了方便，以实线形式示例出设置在常规集成半导体器件(伪SOC芯片)100中的LSI芯片2、MEMS芯片3和绝缘材料4以及在集成半导体器件(伪SOC芯片)100上的凸起电极5。
与根据本实施例的集成半导体器件(伪SOC芯片)1相类似，常规集成半导体器件(伪SOC芯片)100包括LSI芯片2、MEMS芯片3、绝缘材料4、凸起电极5、接触部分6、有机绝缘膜7、细薄层布线8、有机绝缘膜9、I/O电极10、MEMS封装材料11、以及MEMS腔12，如图3和4中所示。
该常规集成半导体器件(伪SOC芯片)100与集成半导体器件(伪SOC芯片)1之间的差别在于I/O电极10(凸起电极5)的位置。如上所述，集成半导体器件(伪SOC芯片)1具有在集成半导体器件(伪SOC芯片)1的LSI芯片2和MEMS芯片3之间的绝缘材料4的区域上方的I/O电极10(凸起电极5)。比较而言，集成半导体器件(伪SOC芯片)100具有仅在半导体器件(伪SOC芯片)100周边上的绝缘材料4的区域上方的I/O电极10(凸起电极5)。换句话说，在LSI芯片2和MEMS芯片3之间的绝缘材料4的区域上方没有设置I/O电极10(凸起电极5)。
现在说明在电路布线板200上对常规集成半导体器件(伪SOC芯片)100的倒装芯片装配。在该装配中，由于集成半导体器件和电路布线板的热膨胀系数之间的差异，在图5中所示例的常规集成半导体器件(伪SOC芯片)100和电路布线板200之间产生位移差。特别地，由于与电路布线板200接触的I/O电极10(凸起电极5)设置在集成半导体器件(伪SOC芯片)100周边上的绝缘材料4的顶表面上，因此在集成半导体器件(伪SOC芯片)100中发生翘曲(应力变形)300。这导致集成半导体器件(伪SOC芯片)100的LSI芯片2和MEMS芯片3之间的那部分绝缘材料4的破裂。
接着，说明根据本实施例在电路布线板200上对集成半导体器件(伪SOC芯片)1的倒装芯片装配。在图6中所示例的集成半导体器件(伪SOC芯片)1和电路布线板200的热膨胀系数之间存在差异，这在集成半导体器件与电路布线板之间引起位移差。然而，连接到电路布线板200的I/O电极10(凸起电极5)被设置在集成半导体器件(伪SOC芯片)1的LSI芯片2和MEMS芯片3之间的那部分绝缘材料4的顶表面上。因此，有效地抑制集成半导体器件(伪SOC芯片)1中的翘曲(应力变形)300。由此可以解决与集成半导体器件(伪SOC芯片)1的LSI芯片2和MEMS芯片3之间的区域相对应的绝缘材料4的破裂的问题。因此，根据本实施例的集成半导体器件(伪SOC芯片)1提高了与在其上倒装芯片装配集成半导体器件的电路布线板200的连接的可靠性。
对于电路布线板200，可以采用在美国专利No.4811082中描述的基底，或者采用具有构建在常规玻璃环氧树脂基底上的绝缘层和导电层的印刷表面分层电路(surface laminar circuit，SLC)板。此外，还可以采用其上具有铜布线的主要由聚酰亚胺树脂形成的公知的柔性板。不具体限制电子电路器件的电路布线板200。
现在说明根据本实施例的集成半导体器件的制造方法。图7A到7M是在制造工艺中根据本实施例的集成半导体器件(伪SOC芯片)1的截面图。这些附图对应于沿着A-A截取的图1中的器件。
首先，如图7A中所示例的，制备LSI芯片2、MEMS芯片3、以及玻璃掩模(集成转移板)13。将具有不同的胶粘强度的有机绝缘膜7沉积在其上安装LSI芯片2和MEMS芯片3的玻璃掩模13的表面上。在玻璃掩模13的另一侧上形成细布线图形14。为了说明，使用感光聚酰亚胺树脂(Toray UR3140)作为该实例中的有机绝缘膜7。
接着，在图7B中，以这样的方式将LSI芯片2和MEMS芯片3安装在玻璃掩模13上，以使LSI芯片2的表面(附图中的底侧)与MEMS芯片3的表面齐平。实际上，大量的LSI芯片2和MEMS芯片3被设置在玻璃掩模13上，一起构成伪SOC晶片。
在图7C中，利用绝缘材料4涂敷LSI芯片2和MEMS芯片3的背面(附图中的顶侧)。在该实例中，为了说明，采用包含硅石填充物的环氧树脂用于绝缘材料4。由于应该将绝缘材料4沉积在半导体元件之间的微小区域中而没有任何孔隙，所以优选在绝缘材料4的涂敷中采用真空印刷技术。
其后，如图7D中所示例的，使LSI芯片2和MEMS芯片3在玻璃掩模13上对准，且在其上形成有玻璃掩模13的细布线图形14的表面上将上面具有这些芯片的结构暴露于曝光能量15。根据用于有机绝缘膜7的感光树脂的灵敏度来调整曝光量。在该实例中利用聚酰亚胺树脂(Toray UR3140)，曝光量优选为100mJ/cm2。
接着，在图7E中，在去除玻璃掩模13之后，执行显影工艺，以便在接触部分6的表面(附图中的底侧)上所沉积的有机绝缘膜7中选择性地制造开口以形成接触过孔16。在显影工艺中使用显影溶液(TorayDV-505)。在制造工艺中使该实例的有机绝缘膜7的表面(附图中的底侧)平坦化。
在图7F中，通过诸如电子束(EB)蒸发或溅射的任意公知技术，在有机绝缘膜7的表面(附图中的顶侧)上沉积细薄层布线8。从而通过接触过孔16将细薄层布线8电连接到接触部分6，或者换句话说，连接到LSI芯片2和MEMS芯片3。在该实例中，将Al/Ti用于细薄层布线8。由于使有机绝缘膜7的表面(附图中的顶侧)平坦化，不发生细薄层布线8不规则地破裂的问题。此外，由于也会使得在随后的工艺中沉积的层平坦化，因此I/O电极10形成为平坦的。因此，以高精度在I/O电极10上形成凸起电极5。
在图7G中，利用有机绝缘膜9涂敷细薄层布线8的表面(附图中的顶侧)，以便叠置细薄层布线8和有机绝缘膜9。结果，细薄层布线8和有机绝缘膜9这两层都形成在有机绝缘膜7上。此外，在有机绝缘膜9的最外表面(附图中的最顶层)中形成开口17，用于设置I/O电极10。每个开口17的直径为50微米，且从开口17暴露出的细薄层布线8用作I/O电极10的一部分。在该实例中，由感光聚酰亚胺树脂(Toray UR3140)形成有机绝缘膜9。
在图7H中，通过电子束(EB)蒸发来利用Cu/Ti多级金属层18涂敷有机绝缘膜9的表面(附图中的顶侧)。多级金属层18具有多层结构，其中Cu层沉积于Ti层的表面(附图中的顶侧)上。形成在开口17中的多级金属层18的部分最终成为I/O电极10的一部分，且用作对凸起电极5的阻挡金属。
在图7I中，在多级金属层18的表面(附图中的顶侧)上旋转涂敷50微米厚的抗蚀剂膜19，且通过曝光和显影在抗蚀剂膜19中形成具有80微米直径的开口20，该80微米直径大于开口17的直径。以足够用于抗蚀剂膜19的厚度的能量的量来执行曝光，并在该实例中通过使用显影溶液(Hoechst Japan，AZ400K显影液)来执行显影。对于抗蚀剂膜19，使用厚膜抗蚀剂(Hoechst Japan，AZ4903)。
接着，如图7J中所示，现在，所产生的伪SOC晶片在与I/O电极10(开口17)相对应的位置处的抗蚀剂膜19中具有开口20。在该实例中，在下述组分的Pb/Sn镀敷溶液(磺酸焊接/镀敷溶液)中浸没且电镀将该伪SOC晶片。利用Cu/Ti层作为阴极且利用高纯度共晶焊料板作为阳极来进行电镀。电流密度在1与4A/dm2之间，且浴池温度为25℃。轻轻地搅拌溶液，以便在开口20中的多级金属层18上沉积50微米的PbSn焊料合金21。这里，焊料成分(Pb/Sn)大体上与共晶焊料相同或朝向Pb或Sn略微偏移。在工艺结束时PbSn焊料合金21成为凸起电极5。
磺酸焊接/镀敷溶液的成分
锡离子(Sn2+)         12体积百分比
铅离子(Pb2+)         30体积百分比
脂肪族磺酸           41体积百分比
非离子表面活性剂     5体积百分比
阳离子表面活性剂     5体积百分比
异丙醇               7体积百分比
在图7K中，利用丙酮去除由AZ4903形成以在电镀工艺中用作抗蚀剂的抗蚀剂膜19。
在图7L中，为了去除多级金属层18，通过浸入柠檬酸/过氧化氢的溶液中来蚀刻掉Cu层，且然后通过浸入乙二胺四乙酸/氨水/过氧化氢/净化水的混合溶液中来蚀刻掉Ti层。结果，除了PbSn焊料合金21的背面(附图中的底侧)上的部分之外，完全去除多级金属层18。
在图7M中，通过对伪SOC晶片进行回流，使PbSn焊料合金21成形为环形(round)凸起电极5。
最后，将通过上述处理步骤获得的伪SOC晶片切割成单独的芯片，完成集成半导体器件(伪SOC芯片)1。
现在说明将由参考图7A到7M所述的制造工艺获得的集成半导体器件(伪SOC芯片)1倒装芯片安装到电路布线板200的方法。特别地，通过利用具有用于对准的单向透视玻璃(half mirror)的公知技术的倒装芯片接合器，对准电路布线板200的电极端子和集成半导体器件(伪SOC芯片)1的凸起电极5。通过具有加热机构的夹头(collet)夹持集成半导体器件(伪SOC芯片)1，并将其在350℃的氮气气氛中预热。
接着，随着使得集成半导体器件(伪SOC芯片)1的凸起电极5与电路布线板200的电极端子接触，降低夹头以施加30kg/mm2的压力。然后将温度提升到370℃以熔化焊料，以便将集成半导体器件(伪SOC芯片)1附着到电路布线板200的电极端子。通过上述处理步骤，如图6中所示例的，在电路布线板200上倒装芯片安装集成半导体器件(伪SOC芯片)1。
如果必要的话，根据公知技术，可以在集成半导体器件(伪SOC芯片)1和电路布线板200之间的间隙中设置封装树脂。可以使用包含双酚型环氧树脂、咪唑固化催化剂、酸酐固化剂、以及45wt％的球状石英填充物的环氧树脂作为封装树脂。
此外，可以使用熔融的环氧树脂，通过研磨、混合、以及熔化100重量份的甲酚酚醛型环氧树脂(Sumitomo Chemical Co.，Ltd.，ECON-195XL)、54重量份的作为固化剂的苯酚树脂、100重量份的作为填充物的熔融硅石、0.5重量份的作为催化剂的苄基二甲胺、3重量份的作为另一添加剂的碳黑、以及3重量份的硅烷耦合剂，来准备该环氧树脂。材料不具体限制为上述材料。
下面与在电路布线板200上常规集成半导体器件(伪SOC芯片)100的上述倒装芯片装配的连接可靠性相比较，来讨论在电路布线板200上通过参考图7A至7M说明的制造方法而获得的集成半导体器件(伪SOC芯片)1的上述倒装芯片装配的连接可靠性。
更具体地，比较两种类型的样品以进行有关它们的连接可靠性的评估。通过将在20毫米×5毫米的区域中包括256个凸起电极5的常规集成半导体器件(伪SOC芯片)100倒装芯片安装到电路布线板200上来制备一种类型的样品，而通过将在20毫米×5毫米的区域中包括256个凸起电极5的集成半导体器件(伪SOC芯片)1倒装芯片安装到电路布线板200上来准备另一种类型的样品。对于每一类型，在-55℃(30分钟)到25℃(5分钟)到125℃(30分钟)到25℃(5分钟)的温度循环条件下测试一千个样品。如果256个管脚中的任意一个变为断开的，则确定该器件为不合格的。
作为测试的结果，在1500次循环之后，在100％的常规集成半导体器件(伪SOC芯片)100中，发现设置在LSI芯片2和MEMS芯片3之间的绝缘材料4在应力下破裂。
另一方面，在根据本实施例的集成半导体器件(伪SOC芯片)1中，在3000次循环之后，在设置于LSI芯片2和MEMS芯片3之间的绝缘材料4中没有观察到破裂。这表明在连接可靠性方面的显著提高。
下面给出本实施例的修改例。如图8中所示例的，集成半导体器件(伪SOC芯片)31与集成半导体器件(伪SOC芯片)1的不同之处在于：凸起电极5和I/O电极10不仅设置在集成半导体器件(伪SOC芯片)31的LSI芯片2和MEMS芯片3之间的绝缘材料4的部分(的紧接上方)的顶表面，而且还设置在该部分(的紧接下方)的背表面上。通过设置在其间的通孔布线32，将顶表面上的I/O电极10连接到背表面上的I/O电极10。
由于这个原因，在绝缘材料4中线性地形成将在绝缘材料4的顶表面和背表面上的I/O电极10相互连接的通孔布线32。这意味着不必以迂回的方式在LSI芯片2和MEMS芯片3中制造垂直通孔。因此，当与在LSI芯片2和MEMS芯片3的半导体基底中具有通孔的器件相比较，可以以较低成本制造在其两个表面(顶表面和底表面)上具有I/O电极10的集成半导体器件(伪SOC芯片)31。另外，由于设置在I/O电极10上的凸起电极，可以容易地以三维的方式将集成半导体器件(伪SOC芯片)31与其它集成半导体器件(伪SOC芯片)或其它电子器件叠置在一起。
根据本实施例，集成半导体器件的I/O电极设置在绝缘材料的顶表面上，利用该绝缘材料将不同类型的元件相互固定，其中该集成半导体器件为伪SOC芯片。此外，通过设置在I/O电极10上的凸起电极，将集成半导体器件固定到电路布线板上。由于这种结构，可以避免由集成半导体器件和电路布线板的热膨胀系数之间的差异所导致的集成半导体器件的应力变形。因此，在不同类型元件之间的绝缘材料的部分中没有发生破裂，且可以容易地改善连接可靠性。
根据本发明，集成半导体器件的I/O电极设置在绝缘材料的顶表面上，利用该绝缘材料将不同类型的元件相互固定，其中该集成半导体器件为伪SOC芯片。此外，通过设置在I/O电极上的凸起电极，将集成半导体器件固定到电路布线板上。由于这种结构，保护集成半导体器件不受由集成半导体器件和电路布线板的热膨胀系数之间的差异所导致的应力变形影响。因此本发明的优点在于：在不同类型元件之间的有机树脂绝缘材料的部分中没有发生破裂，且可以改善连接可靠性。
对于本领域技术人员来说，很容易想到其它的优点和修改例。因此，本发明在其更宽方面不限于在此所示出和描述的具体细节和代表性实施例。因此，在不脱离由所附权利要求书及其等同物限定的总发明构思的精神或范围下，可以进行各种修改。

Claims (7)

1.一种集成半导体器件，包括：
多个半导体元件，具有不同的集成元件电路或不同的尺寸；
绝缘材料，设置在所述半导体元件之间；
有机绝缘膜，完全设置在所述半导体元件和所述绝缘材料上；
细薄层布线，设置在所述有机绝缘膜上，且连接所述半导体元件；
第一输入/输出电极，设置在所述绝缘材料的区域上；以及
第一凸起电极，形成在所述第一输入/输出电极上。
2.根据权利要求1的器件，其中
所述绝缘材料包括：第一表面，在其上形成所述细薄层布线；第二表面，在所述集成半导体器件的背表面上与所述第一表面相对；以及连接所述第一表面和所述第二表面的通孔，
在所述第一表面上设置所述第一输入/输出电极，以及
在所述第二表面上设置第二输入/输出电极。
3.根据权利要求1的器件，其中所述半导体元件中的至少一个为机电元件。
4.根据权利要求1的器件，其中通过使用所述第一凸起电极在电路布线板上倒转芯片安装所述器件。
5.根据权利要求2的器件，其中在所述第二输入/输出电极上形成第二凸起电极。
6.根据权利要求1的器件，其中所述绝缘材料由包含至少硅石填充物的选自环氧树脂、聚酰亚胺树脂以及苯并环丁烯(BCB)中的至少一种形成。
7.根据权利要求1的器件，其中所述第一凸起电极由包含Ti、Ni、Al、Cu、Au、Ag、Pb、Sn、Pd和W中的至少一种的金属或其合金形成。
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