TWI760518B - 包括絕熱壁的半導體封裝 - Google Patents

包括絕熱壁的半導體封裝 Download PDF

Info

Publication number
TWI760518B
TWI760518B TW107122325A TW107122325A TWI760518B TW I760518 B TWI760518 B TW I760518B TW 107122325 A TW107122325 A TW 107122325A TW 107122325 A TW107122325 A TW 107122325A TW I760518 B TWI760518 B TW I760518B
Authority
TW
Taiwan
Prior art keywords
semiconductor
package
die
insulating wall
semiconductor die
Prior art date
Application number
TW107122325A
Other languages
English (en)
Other versions
TW201917840A (zh
Inventor
姜敃圭
孫在現
申志爀
Original Assignee
南韓商愛思開海力士有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商愛思開海力士有限公司 filed Critical 南韓商愛思開海力士有限公司
Publication of TW201917840A publication Critical patent/TW201917840A/zh
Application granted granted Critical
Publication of TWI760518B publication Critical patent/TWI760518B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

包括絕熱壁的半導體封裝。一種半導體封裝包括並排設置在封裝基板的表面上的第一半導體晶片和第二半導體晶片。絕熱壁被設置在第一半導體晶片與第二半導體晶片之間。絕熱壁將第一半導體晶片與第二半導體晶片熱隔離。

Description

包括絕熱壁的半導體封裝
本公開涉及半導體封裝技術，更具體地講，涉及包括將一個半導體晶片與另一半導體晶片熱隔離的絕熱壁的半導體封裝。
相關申請的交叉引用
本申請主張2017年10月27日提交的韓國申請No.10-2017-0141341的優先權，其整體通過引用併入本文。
可在單個半導體封裝中採用各種類型的半導體晶片。單個半導體封裝中所採用的半導體晶片可具有不同的功能。即，單個半導體封裝中所採用的半導體晶片可能不同地消耗電力。因此，由單個半導體封裝中的半導體晶片產生的熱的量也可能彼此不同。
與消耗相對低的電力的低功率半導體晶片相比，消耗相對高的電力的高功率半導體晶片可產生相對大量的熱。由高功率半導體晶片產生的熱可被傳導到與高功率半導體晶片相鄰的低功率半導體晶片。在這種情況下，低功率半導體晶片的性能可能由於高功率半導體晶片所產生的熱而下降。因此，在至少兩種不同類型的半導體晶片被嵌入在單個半導體封裝中的情況下，可能有必要開發用於控制或處理單個半導體封裝中的熱分佈和熱傳導的技術。
根據實施方式，提供了一種半導體封裝。該半導體封裝包括：第一封裝基板；內建封裝，其被設置在第一封裝基板上並被配置為包括第一半導體晶片以及用於將第一半導體晶片熱隔離的絕熱壁；以及第二半導體晶片，其被設置在第一封裝基板上以與內建封裝間隔開。
根據另一實施方式，提供了一種半導體封裝。該半導體封裝包括：第一半導體晶片和第二半導體晶片，它們被並排設置在封裝基板的表面上以彼此間隔開；第一模製層，其覆蓋第一半導體晶片；第二模製層，其覆蓋第二半導體晶片；以及絕熱壁，其被設置在第一模製層與第二模製層之間以將第一半導體晶片熱隔離。
10‧‧‧半導體封裝
10R‧‧‧半導體封裝
100‧‧‧內建封裝
110‧‧‧半導體晶片
110R‧‧‧第一半導體晶片
111‧‧‧頂表面
112‧‧‧底表面
113‧‧‧側表面
130‧‧‧熱導體
131‧‧‧頂表面
132‧‧‧底表面
133‧‧‧側表面
150‧‧‧第二封裝基板
153‧‧‧側表面
161‧‧‧第一球連接器
165‧‧‧第二球連接器
190‧‧‧絕熱壁
191‧‧‧內側表面
193‧‧‧外側表面
195‧‧‧上端
196‧‧‧下端
199‧‧‧絕熱層的部分
200‧‧‧半導體晶片
200R‧‧‧第二半導體晶片
300‧‧‧半導體晶片
300R‧‧‧第三半導體晶片
301‧‧‧第一層疊物
302‧‧‧第二層疊物
310‧‧‧第三半導體晶片
320‧‧‧接合線
400‧‧‧半導體晶片
400R‧‧‧第四半導體晶片
500‧‧‧第一封裝基板
500R‧‧‧封裝基板
501‧‧‧頂表面
502‧‧‧底表面
600‧‧‧第三球連接器
710‧‧‧第一模製層
711‧‧‧頂表面
713‧‧‧側表面
720‧‧‧第二模製層
721‧‧‧頂表面
723‧‧‧側表面
802R‧‧‧第一熱傳導路徑
803R‧‧‧第二熱傳導路徑
805‧‧‧第三熱傳導路徑
7800‧‧‧記憶卡
7830‧‧‧主機
8710‧‧‧電子系統
8711‧‧‧控制器
8712‧‧‧輸入/輸出單元
8713‧‧‧記憶體
8714‧‧‧介面
8715‧‧‧匯流排
鑒於附圖和所附詳細描述，本公開的各種實施方式將變得更顯而易見，附圖中：圖1是示出根據實施方式的半導體封裝的平面圖；圖2是沿著圖1的線A-A’截取的橫截面圖；圖3是沿著圖1的線B-B’截取的橫截面圖；圖4是示出嵌入在圖1的半導體封裝中的內建封裝的橫截面圖；圖5是示出沒有絕熱壁的一般半導體封裝作為比較例的平面圖；圖6是示出採用包括根據實施方式的半導體封裝的記憶卡的電子系統的框圖；以及圖7是示出包括根據實施方式的半導體封裝的另一電子系統的框圖。
本文所使用的術語可對應於考慮其在實施方式中的功能而選擇的詞語，術語的含義可被解釋為根據實施方式所屬領域的普通技術人員而不同。如果詳細定義，則可根據定義來解釋術語。除非另外定義，否則本文所使用的術語(包括技術術語和科學術語)可具有實施方式所屬領域的普通技術人員通常理解的相同含義。
將理解，儘管本文中可使用術語“第一”、“第二”、“第三”等來描述各種元件，但是這些元件不應受這些術語限制。這些術語僅用於將一個元件與另一元件相區分，而非用於僅限定元件本身或者意指特定順序。
還將理解，當元件或層被稱為在另一元件或層“上”、“上方”、“下麵”、“下方”或“外側”時，該元件或層可與另一元件或層直接接觸，或者可存在中間元件或層。用於描述元件或層之間的關係的其它詞語應該以類似的方式解釋(例如，“在...之間”與“直接在...之間”或者“相鄰”與“直接相鄰”之間)。
諸如“在...之下”、“在...下面”、“下”、“上面”、“上”、“頂部”、“底部”等的空間相對術語可用於描述元件和/或特徵與另一元件和/或特徵的關係(例如，如圖中所示)。將理解，除了附圖中所描繪的取向之外，空間相對術語旨在涵蓋裝置在使用和/或操作中的不同取向。例如，當附圖中的裝置翻轉時，被描述為在其它元件或特徵下面和/或之下的元件將被取向為在其它元件或特徵上面。裝置可按照其它方式取向(旋轉90度或處於其它取向)並且相應地解釋本文中所使用的空間相對描述符。
半導體封裝可包括諸如半導體晶片或半導體晶粒的電子裝置。半導體晶片或半導體晶粒可藉由使用晶粒切割製程將諸如晶圓的半導體基板分離成多片來獲得。半導體晶片可對應於記憶體晶片、邏輯晶片(包括特殊應用積體電路(ASIC)晶片)或系統上晶片(SoC)。記憶體晶片可包括集成在半 導體基板上的動態隨機存取記憶體(DRAM)電路、靜態隨機存取記憶體(SRAM)電路、NAND型快閃記憶體電路、NOR型快閃記憶體電路、磁隨機存取記憶體(MRAM)電路、電阻式隨機存取記憶體(ReRAM)電路、鐵電隨機存取記憶體(FeRAM)電路或相變隨機存取記憶體(PcRAM)電路。邏輯晶片可包括集成在半導體基板上的邏輯電路。半導體封裝可用在諸如行動電話的通信系統、與生物技術或保健關聯的電子系統或可穿戴電子系統中。
以下將參照附圖描述本公開的各種實施方式。貫穿說明書，相同的標號表示相同的元件。即使標號未參照一幅圖提及或描述，該標號也可參照另一幅圖提及或描述。另外，即使標號未在一幅圖中示出，其也可參照另一幅圖提及或描述。
圖1示出根據實施方式的半導體封裝10的平面圖。圖2是沿著圖1的線A-A’截取的橫截面圖，圖3是沿著圖1的線B-B’截取的橫截面圖。圖4示出嵌入在圖1的半導體封裝10中的內建封裝100的橫截面圖。圖5是示出沒有絕熱壁的一般半導體封裝10R作為比較例的平面圖。
參照圖1，半導體封裝10可被配置為具有多晶片封裝(MCP)形狀或球柵陣列固態驅動器(BGA SSD)封裝形狀。半導體封裝10可被配置為包括多個半導體晶片110、200、300和400。半導體晶片110、200、300和400可具有不同的功能。
如果半導體封裝10被配置為具有BGA SSD封裝形狀，則第一半導體晶片110可對應於控制器晶片。在這種情況下，第二半導體晶片200可包括緩衝記憶體，第三半導體晶片300可包括構成SSD的非揮發性記憶體。與控制器晶片對應的第一半導體晶片110可被配置為控制具有BGA SSD封裝形狀的半導體封裝10的總體操作。控制器晶片(即，第一半導體晶片110)可以是系統晶片。控制器晶片110可包括邏輯裝置，該邏輯裝置控制緩衝記憶體(即，第二 半導體晶片200)和非揮發性記憶體(即，第三半導體晶片300)的操作。
第四半導體晶片400可包括電源管理積體電路(PMIC)裝置。第二半導體晶片200可包括揮發性記憶體(例如，DRAM裝置)，其充當緩衝記憶體。緩衝記憶體可暫時地儲存要寫到非揮發性記憶體(即，第三半導體晶片300)中的資料。即，資料可基本上儲存在非揮發性記憶體(即，第三半導體晶片300)中。非揮發性記憶體(即，第三半導體晶片300)可使用MAND型記憶體裝置來實現。第三半導體晶片300可包括多個層疊物(例如，第一層疊物301和第二層疊物302)以增加第三半導體晶片300的資料儲存容量。
第一至第四半導體晶片110、200、300和400可被安裝在第一封裝基板500上。第一至第四半導體晶片110、200、300和400可被設置在第一封裝基板500的頂表面501上。第一至第四半導體晶片110、200、300和400可被設置在第一封裝基板500的頂表面501上，其中第一至第四半導體晶片110、200、300和400可彼此間隔開。此外，第二至第四半導體晶片200、300和400可與內建封裝100間隔開。此外，至少第一半導體晶片110和第二半導體晶片200可並排設置在封裝基板500的表面上。
充當控制器晶片的第一半導體晶片110可利用相對高的驅動電壓來操作，並且在操作期間可產生相對大量的熱。即，第一半導體晶片110可以是高功率半導體晶片。相比之下，第二半導體晶片200或第三半導體晶片300可以是產生相對少量的熱的低功率半導體晶片。例如，充當控制器晶片的第一半導體晶片110可消耗大約1.5瓦的電力，而包括DRAM裝置的第二半導體晶片200可消耗大約0.15瓦的電力。此外，第一半導體晶片110可產生比第二半導體晶片200和第三半導體晶片300更大量的熱。
參照圖1和圖2，絕熱壁190可被設置在第一半導體晶片110與第二半導體晶片200之間。絕熱壁190可被引入到半導體封裝10中以將第二半導體 晶片200與第一半導體晶片110熱隔離。如圖3所示，絕熱壁190可延伸以將第三半導體晶片300與第一半導體晶片110熱隔離。
參照圖5，一般半導體封裝10R可被圖示作為比較範例並且可被配置為沒有絕熱壁190。第一半導體晶片110R可設置在封裝基板500R上。第二半導體晶片200R、第三半導體晶片300R和第四半導體晶片400R可設置在第一半導體晶片110R的周邊區域處。第一半導體晶片110R可以是在操作期間產生相對大量的熱的高功率裝置。
第一半導體晶片110R所產生的熱可沿著第一熱傳導路徑802R和第二熱傳導路徑803R被傳導到設置在第一半導體晶片110R的周邊區域處的第二半導體晶片200R和第三半導體晶片300R。因此，由於第一半導體晶片110R所產生的熱，第二半導體晶片200R和第三半導體晶片300R的溫度可能不期望地升高。
傳導到第二半導體晶片200R的熱可使第二半導體晶片200R的特性劣化。即，構成第二半導體晶片200R的DRAM裝置的特性可能由於傳導到第二半導體晶片200R的熱而劣化。例如，構成第二半導體晶片200R的DRAM裝置中的電晶體可能被從第一半導體晶片110R產生的熱加熱，從而使DRAM裝置的刷新特性、操作速度和可靠性劣化。如果DRAM裝置的溫度升高，則用於防止DRAM裝置的單元資料丟失的刷新操作的迴圈時間可能減小，從而導致刷新操作的執行次數增加。
另外，傳導到第三半導體晶片300R的熱可使構成第三半導體晶片300R的NAND型記憶體件的特性劣化。例如，如果NAND型裝置的溫度升高，則NAND型裝置的資料保持特性和可靠性可能會劣化。
再參照圖1和圖2，絕熱壁190可延伸以環繞第一半導體晶片110的周邊，如圖1所示。當從平面圖看時，絕熱壁190可具有矩形閉環形狀以環繞 第一半導體晶片110。因此，絕熱壁190可對從第一半導體晶片110的操作產生的熱通過與圖5所示的第一熱傳導路徑802R和第二熱傳導路徑803R對應的熱傳導路徑傳導到第二半導體晶片200和第三半導體晶片300進行阻斷。即，絕熱壁190可被設置為阻擋從第一半導體晶片110朝著第一半導體晶片110的周邊區域的熱傳導。
由於從第一半導體晶片110朝著第一半導體晶片110的周邊區域的熱傳導被絕熱壁190抑制，所以絕熱壁190可防止第二半導體晶片200和第三半導體晶片300的特性由於第二半導體晶片200和第三半導體晶片300的溫度增加而劣化。
參照圖2，絕熱壁190可被設置為使得絕熱壁190的內側表面191面向第一半導體晶片110的側表面113。絕熱壁190的內側表面191可與覆蓋第一半導體晶片110的側表面113的第一模製層710的側表面713接觸。絕熱壁190與第一半導體晶片110的側表面113之間的間隙區域可利用第一模製層710的部分填充。絕熱壁190的多個外側表面193中的一個可面向第二半導體晶片200。絕熱壁190的外側表面193可與第二模製層720接觸。絕熱壁190的多個外側表面193中的另一個可面向第三半導體晶片300，如圖3所示。
絕熱壁190可被設置在第一封裝基板500的頂表面501上方，並且可向上延伸，使得絕熱壁190的上端195位於與第一模製層710的頂表面711相同的水平處。絕熱壁190可向上延伸以到達第二模製層720的頂表面721。第一模製層710的頂表面711可位於與第二模製層720的頂表面721基本上相同的水平處。絕熱壁190可延伸以具有高度T2，該高度T2大於第一半導體晶片110的厚度T1，其中絕熱壁190可在與第一封裝基板500的頂表面501正交的法線相同的方向上延伸。例如，絕熱壁190的上端195可在第一模製層710的頂表面711和第二模製層720的頂表面721之間的介面處暴露。絕熱壁190的與上端195相對的下端 196可位於比第一半導體晶片110的底表面112低的水平處。
絕熱壁190可垂直延伸，使得絕熱壁190的下端196位於比第一半導體晶片110的底表面112低的水平處，並且絕熱壁190的上端195位於比第一半導體晶片110的頂表面111高的水平處。由於絕熱壁190的內側表面191的總面積大於第一半導體晶片110的側表面113的總面積，所以絕熱壁190可有效地阻擋從第一半導體晶片110朝著第二半導體晶片200和第三半導體晶片300傳導的熱。
第二模製層720可被設置在第一封裝基板500的頂表面501上以覆蓋第二半導體晶片200、第三半導體晶片300和第四半導體晶片400。第一模製層710可被設置為覆蓋第一半導體晶片110的至少一部分。第一模製層710和第二模製層720中的每一個可包括保護材料(例如，環氧模塑化合物(EMC)材料)以保護第一至第四半導體晶片110、200、300和400免受外部環境影響。絕熱壁190的下端196可與第一封裝基板500的頂表面501間隔開。第二模製層720可延伸以填充絕熱壁190的下端196與第一封裝基板500的頂表面501之間的間隙。
絕熱壁190可包括熱導率低於第一模製層710和第二模製層720的熱導率的絕熱材料。例如，絕熱壁190可包括具有大約0.02W/mK至大約0.60W/mK的熱導率的絕熱材料。絕熱壁190可包括具有至多0.4W/mK的熱導率的絕熱材料。在一些實施方式中，絕熱壁190可包括無機絕熱材料或有機絕熱材料。無機絕熱材料可包括粉狀碳酸鎂、粉狀氧化鎂、矽酸鈣等，有機絕熱材料可包括聚氨酯(polyurethane)泡沫、聚苯乙烯(polystyrene)泡沫等。另選地，絕熱壁190可包括矽氣凝膠(silica aerogel)材料。
再參照圖1和圖2，絕熱壁190可被設置為環繞第一半導體晶片110的側表面113。因此，通過第一半導體晶片110的操作產生的熱可被基本上保 持在由絕熱壁190環繞的空間中。因此，充當散熱器的熱導體130可被設置在第一半導體晶片110上以提供將第一半導體晶片110所產生的熱傳導到半導體封裝10的外部區域的熱傳導路徑。
熱導體130可附接到第一半導體晶片110，使得熱導體130的底表面132與第一半導體晶片110的頂表面111接觸。熱導體130的與第一半導體晶片110相對的頂表面131可暴露於半導體封裝10的外部區域。因此，熱導體130可構成將第一半導體晶片110所產生的熱傳遞到半導體封裝10的外部區域的第三熱傳導路徑805。結果，第一半導體晶片110所產生的熱可通過第三熱傳導路徑805有效地發射到半導體封裝10的外部區域。
參照圖3，構成第三半導體晶片300的第一層疊物301和第二層疊物302中的每一個可包括垂直地層疊的多個第三半導體晶片310以增加第三半導體晶片300的資料儲存容量。第三半導體晶片310可垂直地層疊以提供具有階梯結構的第一層疊物301或第二層疊物302。第一層疊物301和第二層疊物302中的每一個中的第三半導體晶片310可通過接合線320電連接到第一封裝基板500。
熱導體130可基本上穿透第一模製層710以充當從第一半導體晶片110的頂表面111延伸到第一模製層710的頂表面711的第三熱傳導路徑805。熱導體130可被形成為包括熱導率高於第一模製層710的熱導率的材料。熱導體130可被形成為包括各種導熱材料中的至少一種。
熱導體130可通過將虛設晶片附接到第一半導體晶片110來形成。與熱導體130對應的虛設晶片可以是沒有任何積體電路的半導體虛設晶片(例如，矽虛設晶片)。熱導體130的半導體材料(例如，矽材料)的熱導率可高於第一模製層710的EMC材料的熱導率。因此，第一半導體晶片110所產生的熱可通過熱導體130有效地發射。用作熱導體130的矽虛設晶片可具有大約149W/mK的相對高的熱導率。相比之下，第一模製層710的EMC材料可具有大 約3W/mK的熱導率，其低於熱導體130的熱導率。如果熱導體130是矽虛設晶片並且第一半導體晶片110是矽晶片，則熱導體130和第一半導體晶片110可具有基本上相同的熱膨脹係數。在這種情況下，即使第一半導體晶片110由於操作而變熱，在熱導體130與第一半導體晶片110之間的介面處也不形成熱應力。結果，第一半導體晶片110不會遭受諸如裂縫的缺陷。
儘管圖中未示出，熱介面材料層可被設置在熱導體130與第一半導體晶片110之間以改進熱導體130與第一半導體晶片110之間的熱傳導效率。
再參照圖2，第一半導體晶片110可被設置在第一封裝基板500上並且可被嵌入在內建封裝100中。內建封裝100可被配置為包括設置在第一封裝基板500上方的第二封裝基板150、安裝在第二封裝基板150的表面上的第一半導體晶片110以及覆蓋並保護第一半導體晶片110的第一模製層710，如圖2和圖4所示。第一模製層710和第二模製層720可被形成為包括基本上相同的材料。即使第一模製層710和第二模製層720分別在兩個不同的模製步驟形成，第一模製層710和第二模製層720可構成半導體封裝10的模製層。
參照圖2和圖4，第二封裝基板150可包括互連構件以將第一半導體晶片110電連接到第一封裝基板500。第二封裝基板150可以是印刷電路板(PCB)。第一半導體晶片110和第二封裝基板150可通過第一球連接器161彼此電連接。第一封裝基板500和第二封裝基板150可通過第二球連接器165彼此電連接。
參照圖4，可通過在第一模製層710的側表面713(與內建封裝100的側表面對應)和第一模製層710的頂表面711(與內建封裝100的頂表面對應)上沉積絕熱膜或絕熱層並藉由去除絕熱膜或絕熱層的一部分199以暴露第一模製層710的頂表面711來形成絕熱壁190。絕熱壁190可覆蓋第一模製層710的側表面713(與內建封裝100的側表面對應)並且可延伸以覆蓋第二封裝基板 150的側表面153。因此，絕熱壁190可延伸以環繞內建封裝100的所有側表面。作為去除絕熱膜或絕熱層的部分199的結果，絕熱壁190可被形成為使第一模製層710的頂表面711(與內建封裝100的側表面對應)暴露。
再參照圖2，絕熱壁190可被設置在第二模製層720與第一模製層710的側表面713之間。換言之，第二模製層720可使第一模製層710的頂表面711暴露。熱導體130的頂表面131也可在第一模製層710的頂表面711處暴露。熱導體130可被設置為基本上穿透第一模製層710的一部分以接觸第一半導體晶片110的頂表面111。
內建封裝100的第二封裝基板150可抑制從第一半導體晶片110到第一封裝基板500的熱傳導。第二封裝基板150可包括具有相對低的熱導率的有機材料。因此，第二封裝基板150可更有效地抑制從第一半導體晶片110到第二半導體晶片200和第三半導體晶片300的熱傳導。
此外，第二球連接器165可附接到第一封裝基板500的頂表面501，第三球連接器600可附接到第一封裝基板500的與第二球連接器165相對的底表面502。第三球連接器600可充當將半導體封裝10電連接到外部裝置或外部系統的連接構件。
根據上述實施方式，絕熱壁可被設置在半導體封裝中以將包括在半導體封裝中的高功率半導體晶片與包括在半導體封裝中的至少一個低功率半導體裝置熱隔離。
圖6是示出包括採用根據實施方式的多個半導體封裝中的至少一個的記憶卡7800的電子系統的框圖。記憶卡7800可包括諸如非揮發性記憶體裝置的記憶體7810以及記憶體控制器7820。記憶體7810和記憶體控制器7820可儲存資料或者讀出所儲存的資料。記憶體7810和記憶體控制器7820中的至少一個可包括根據實施方式的多個半導體封裝中的至少一個。
記憶體7810可包括應用了本公開的實施方式的技術的非揮發性記憶體裝置。記憶體控制器7820可控制記憶體7810，使得回應於來自主機7830的讀/寫請求，讀出所儲存的資料或者儲存資料。
圖7是示出包括根據實施方式的多個半導體封裝中的至少一個的電子系統8710的框圖。電子系統8710可包括控制器8711、輸入/輸出單元8712和記憶體8713。控制器8711、輸入/輸出單元8712和記憶體8713可通過提供資料移動的路徑的匯流排8715彼此聯接。
在實施方式中，控制器8711可包括微處理器、數位訊號處理器、微控制器和/或能夠執行與這些元件相同的功能的邏輯裝置中的一個或更多個。控制器8711或記憶體8713可包括根據本公開的實施方式的多個半導體封裝中的至少一個。輸入/輸出單元8712可包括選自鍵區、鍵盤、顯示裝置、觸控式螢幕等中的至少一個。記憶體8713是用於儲存資料的裝置。記憶體8713可儲存要由控制器8711執行的資料和/或命令等。
記憶體8713可包括諸如DRAM的揮發性記憶體裝置和/或諸如快閃記憶體的非揮發性記憶體裝置。例如，快閃記憶體可被安裝到諸如移動終端或桌上型電腦的資訊處理系統。快閃記憶體可構成固態硬碟(SSD)。在這種情況下，電子系統8710可在快閃記憶體系統中穩定地儲存大量資料。
電子系統8710還可包括被配置為向通信網路發送資料以及從通信網路接收資料的介面8714。介面8714可為有線或無線型。例如，介面8714可包括天線或者有線或無線收發器。
電子系統8710可被實現為移動系統、個人電腦、工業電腦或者執行各種功能的邏輯系統。例如，移動系統可以是個人數位助理(PDA)、可擕式電腦、平板電腦、行動電話、智慧型電話、無線電話、膝上型電腦、記憶卡、數位音樂系統和資訊發送/接收系統中的任一個。
如果電子系統8710是能夠執行無線通訊的設備，則電子系統8710可用在使用諸如CDMA(碼分多址)、GSM(全球移動通信系統)、NADC(北美數位蜂窩)、E-TDMA(增強時分多址)、WCDAM(寬頻碼分多址)、CDMA2000、LTE(長期演進)或Wibro(無線寬頻互聯網)的技術的通信系統中。
出於例示性目的公開了本公開的實施方式。本領域技術人員將理解，在不脫離本公開和所附申請專利範圍的範疇和精神的情況下，可進行各種修改、添加和替換。
10‧‧‧半導體封裝
100‧‧‧內建封裝
110‧‧‧半導體晶片
111‧‧‧頂表面
112‧‧‧底表面
113‧‧‧側表面
130‧‧‧熱導體
131‧‧‧頂表面
132‧‧‧底表面
133‧‧‧側表面
150‧‧‧第二封裝基板
161‧‧‧第一球連接器
165‧‧‧第二球連接器
190‧‧‧絕熱壁
191‧‧‧內側表面
193‧‧‧外側表面
195‧‧‧上端
196‧‧‧下端
200‧‧‧半導體晶片
400‧‧‧半導體晶片
500‧‧‧第一封裝基板
501‧‧‧頂表面
502‧‧‧底表面
600‧‧‧第三球連接器
710‧‧‧第一模製層
711‧‧‧頂表面
713‧‧‧側表面
720‧‧‧第二模製層
721‧‧‧頂表面

Claims (19)

  1. 一種半導體封裝，該半導體封裝包括：第一封裝基板；內建封裝，該內建封裝被設置在所述第一封裝基板上並被配置為包括第一半導體晶片以及用於將所述第一半導體晶片熱隔離的絕熱壁；第二半導體晶片，該第二半導體晶片被設置在所述第一封裝基板上以與所述內建封裝間隔開；以及被設置為與所述第二半導體晶片間隔開的第三半導體晶片，其中，所述第二半導體晶片包括構成緩衝記憶體的揮發性記憶體；其中，所述第三半導體晶片包括構成固態驅動器(SSD)的非揮發性記憶體；並且其中，所述第一半導體晶片包括控制所述緩衝記憶體和所述固態驅動器的操作的控制器晶片。
  2. 根據請求項1所述的半導體封裝，其中，所述內建封裝還包括填充所述第一半導體晶片與所述絕熱壁之間的間隙的第一模製層。
  3. 根據請求項2所述的半導體封裝，其中，所述內建封裝還包括設置在所述第一封裝基板上方的第二封裝基板；並且其中，所述第一半導體晶片被安裝在所述第二封裝基板上並由所述第一模製層覆蓋。
  4. 根據請求項2所述的半導體封裝，其中，所述絕熱壁包括絕熱材料，該絕熱材料的熱導率低於所述第一模製層的熱導率。
  5. 根據請求項4所述的半導體封裝，其中，所述絕熱壁具有0.4W/mK或更小的熱導率。
  6. 根據請求項2所述的半導體封裝，其中，所述內建封裝還包括熱導體，該熱導體穿透所述第一模製層以與所述第一半導體晶片接觸。
  7. 根據請求項6所述的半導體封裝，其中，所述熱導體包括熱導率高於所述第一模製層的熱導率的材料。
  8. 根據請求項7所述的半導體封裝，其中，所述熱導體包括矽虛設晶片。
  9. 根據請求項2所述的半導體封裝，該半導體封裝還包括第二模製層，該第二模製層覆蓋所述第一封裝基板和所述第二半導體晶片並且使所述第一模製層的頂表面暴露。
  10. 根據請求項9所述的半導體封裝，其中，所述絕熱壁延伸，使得所述絕熱壁的上端在所述第二模製層的頂表面處暴露。
  11. 根據請求項9所述的半導體封裝，其中，所述絕熱壁被設置在所述第二模製層與所述內建封裝的至少一個側表面之間。
  12. 根據請求項1所述的半導體封裝，其中，所述絕熱壁延伸，使得所述絕熱壁的下端位於比所述第一半導體晶片的底表面低的水平處。
  13. 根據請求項1所述的半導體封裝，其中，所述絕熱壁延伸以環繞所述內建封裝的所有側表面。
  14. 根據請求項1所述的半導體封裝，其中，所述第一半導體晶片是比所述第二半導體晶片產生更大量的熱的高功率晶片，其中，所述第二半導體晶片是低功率晶片。
  15. 一種半導體封裝，該半導體封裝包括：並排設置在封裝基板的表面上而彼此間隔開的第一半導體晶片和第二半導體晶片；覆蓋所述第一半導體晶片的第一模製層； 覆蓋所述第二半導體晶片的第二模製層；設置在所述第一模製層與所述第二模製層之間以將所述第一半導體晶片熱隔離的絕熱壁；以及被設置為與所述第二半導體晶片間隔開的第三半導體晶片，其中，所述第二半導體晶片包括構成緩衝記憶體的揮發性記憶體；其中，所述第三半導體晶片包括構成固態驅動器(SSD)的非揮發性記憶體；並且其中，所述第一半導體晶片包括控制所述緩衝記憶體和所述固態驅動器的操作的控制器晶片。
  16. 根據請求項15所述的半導體封裝，其中，所述絕熱壁延伸，使得所述絕熱壁的上端在所述第一模製層和所述第二模製層的頂表面處暴露。
  17. 根據請求項15所述的半導體封裝，其中，所述絕熱壁延伸，使得所述絕熱壁的下端位於比所述第一半導體晶片的底表面低的水平處。
  18. 根據請求項15所述的半導體封裝，其中，所述絕熱壁延伸以環繞所述第一半導體晶片。
  19. 根據請求項15所述的半導體封裝，該半導體封裝還包括熱導體，該熱導體穿透所述第一模製層以與所述第一半導體晶片接觸。
TW107122325A 2017-10-27 2018-06-28 包括絕熱壁的半導體封裝 TWI760518B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020170141341A KR20190047444A (ko) 2017-10-27 2017-10-27 단열벽을 포함하는 반도체 패키지
??10-2017-0141341 2017-10-27
KR10-2017-0141341 2017-10-27

Publications (2)

Publication Number Publication Date
TW201917840A TW201917840A (zh) 2019-05-01
TWI760518B true TWI760518B (zh) 2022-04-11

Family

ID=66243446

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107122325A TWI760518B (zh) 2017-10-27 2018-06-28 包括絕熱壁的半導體封裝

Country Status (4)

Country Link
US (2) US10600713B2 (zh)
KR (1) KR20190047444A (zh)
CN (1) CN109727922B (zh)
TW (1) TWI760518B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190047444A (ko) * 2017-10-27 2019-05-08 에스케이하이닉스 주식회사 단열벽을 포함하는 반도체 패키지
US11152330B2 (en) * 2019-04-16 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure and method for forming the same
KR20210034784A (ko) * 2019-09-23 2021-03-31 삼성전자주식회사 솔리드 스테이트 드라이브 장치 및 그 제조 방법
JP2021077698A (ja) * 2019-11-06 2021-05-20 キオクシア株式会社 半導体パッケージ
KR20210066387A (ko) * 2019-11-28 2021-06-07 삼성전자주식회사 반도체 패키지
US20230137512A1 (en) * 2021-11-03 2023-05-04 Western Digital Technologies, Inc. Stacked ssd semiconductor device
JP2023183142A (ja) * 2022-06-15 2023-12-27 キオクシア株式会社 半導体装置および半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020180023A1 (en) * 2000-07-18 2002-12-05 Tzong-Dar Her Structure of a multi chip module having stacked chips
US20090057874A1 (en) * 2005-03-29 2009-03-05 Infineon Technologies Ag Semiconductor module including semiconductor chips in a plastic housing in separate regions
US20170206937A1 (en) * 2016-01-19 2017-07-20 Mediatek Inc. Hybrid system integrating package-on-package soc and embedded multi-chip package on one main circuit board

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2816244B2 (ja) * 1990-07-11 1998-10-27 株式会社日立製作所 積層型マルチチップ半導体装置およびこれに用いる半導体装置
JP4504434B2 (ja) * 2008-02-14 2010-07-14 株式会社東芝 集積半導体装置
KR20110004119A (ko) 2009-07-07 2011-01-13 주식회사 하이닉스반도체 시스템 인 패키지
US8816494B2 (en) 2012-07-12 2014-08-26 Micron Technology, Inc. Semiconductor device packages including thermally insulating materials and methods of making and using such semiconductor packages
US10269676B2 (en) 2012-10-04 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced package-on-package (PoP)
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure
KR20140106038A (ko) 2013-02-25 2014-09-03 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8987876B2 (en) * 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
KR20150123420A (ko) * 2014-04-24 2015-11-04 에스케이하이닉스 주식회사 반도체 패키지 및 그 제조 방법
KR20190047444A (ko) * 2017-10-27 2019-05-08 에스케이하이닉스 주식회사 단열벽을 포함하는 반도체 패키지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020180023A1 (en) * 2000-07-18 2002-12-05 Tzong-Dar Her Structure of a multi chip module having stacked chips
US20090057874A1 (en) * 2005-03-29 2009-03-05 Infineon Technologies Ag Semiconductor module including semiconductor chips in a plastic housing in separate regions
US20170206937A1 (en) * 2016-01-19 2017-07-20 Mediatek Inc. Hybrid system integrating package-on-package soc and embedded multi-chip package on one main circuit board

Also Published As

Publication number Publication date
KR20190047444A (ko) 2019-05-08
US10600713B2 (en) 2020-03-24
CN109727922B (zh) 2023-04-18
TW201917840A (zh) 2019-05-01
US20190131203A1 (en) 2019-05-02
US20200185298A1 (en) 2020-06-11
CN109727922A (zh) 2019-05-07
US11270923B2 (en) 2022-03-08

Similar Documents

Publication Publication Date Title
TWI760518B (zh) 包括絕熱壁的半導體封裝
US10170456B2 (en) Semiconductor packages including heat transferring blocks and methods of manufacturing the same
US9153557B2 (en) Chip stack embedded packages
TWI718313B (zh) 具有不對稱晶片堆疊結構的半導體封裝
US9985002B2 (en) Thin stack packages
US9158081B2 (en) Semiconductor package with an optical signal path, memory card including the same, and electronic system including the same
TWI810380B (zh) 包括橋接晶粒的系統級封裝件
TWI778197B (zh) 包括橋接晶粒的堆疊封裝
US20150311182A1 (en) Semiconductor package and method for manufacturing the same
TW202029423A (zh) 包括橋接晶粒的半導體封裝
US9391009B2 (en) Semiconductor packages including heat exhaust part
TW202032731A (zh) 包含橋接晶粒的系統級封裝件
KR20160049616A (ko) 반도체 패키지
US9508699B2 (en) Semiconductor package and method for manufacturing the same
US10361141B2 (en) Semiconductor packages relating to thermal transfer plate and methods of manufacturing the same
US9209161B2 (en) Stacked package and method for manufacturing the same
US10714405B2 (en) Semiconductor packages relating to thermal redistribution patterns