CN109690787A - 具有减小的串联总电阻的FinFET - Google Patents

具有减小的串联总电阻的FinFET Download PDF

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CN109690787A
CN109690787A CN201780055712.5A CN201780055712A CN109690787A CN 109690787 A CN109690787 A CN 109690787A CN 201780055712 A CN201780055712 A CN 201780055712A CN 109690787 A CN109690787 A CN 109690787A
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U·卢
S·埃克博特
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Qualcomm Inc
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Abstract

使用选择性外延生长来形成异质结构的源极/漏极区域，以填充n型FinFET器件的硅鳍中的蚀刻的凹槽。

Description

具有减小的串联总电阻的FinFET
相关申请的引用
本申请要求2016年09月13日提交的美国专利申请号15/264,519的优先权，其全部内容通过引用并入本文。
技术领域
本申请一般涉及晶体管，更具体地涉及具有减小的串联总电阻的鳍形场效应晶体管。
背景技术
在鳍形场效应(FinFET)晶体管中形成源极接触和漏极接触必须克服几个障碍。用户需要低导通电阻，这可以通过接触的重掺杂来满足。但是如此重的掺杂会使沟道缩短太多，以至于漏电成为问题。为了提供低导通电阻，通常使用选择性外延生长(SEG)在蚀刻到鳍中的凹槽中形成每个源极/漏极(S/D)接触，以便通过在鳍凹槽内产生的SEG沉积来将鳍加宽。
SEG沉积偏爱某些晶面，使得SEG沉积不在凹槽内呈现平面形状的鳍，而是呈现菱形轮廓，其中轮廓的具有角度的侧面被称为琢面。琢面从鳍横向延伸，使得SEG沉积可以使相邻的鳍融合或合并。因此，对于具有小扩散长度(LOD)的设计，必须减少SEG沉积，以防止相邻FinFET之间的鳍合并，这限制了所需的导通电阻的减小。另外，不稳定的接触着陆会使最小LOD器件的琢面区域中的电阻恶化。而且，对于n型FinFET，鳍侧壁表面通常具有<110>晶向。这不是获得驱动能力的优选方向。因此，n型FinFET的导通电阻和驱动能力问题尚未解决。
因此，本领域需要具有减小的导通电阻的改进的FinFET。
发明内容
通过选择性外延生长(SEG)工艺在n型FinFET的鳍内提供异质结构的源极/漏极区域，以减小源极/漏极总串联电阻和接触电阻率。SEG沉积发生在邻近栅极间隔器的鳍中的蚀刻的凹槽内，并且包括对该凹槽加衬的硅缓冲层。硅锗外延层覆盖缓冲层。最后，在硅锗层之上SEG沉积原位n型掺杂的硅帽层，以完成异质结构的沉积。与帽层相反，硅锗层和缓冲层可以以未掺杂的状态沉积。
在沉积外延层之后，离子注入步骤利用第一浓度的n型掺杂剂(诸如磷)掺杂硅锗层，并利用第二浓度的n型掺杂剂(诸如砷)注入帽层，其中第二浓度大于第一浓度。得到的FinFET具有减小的总串联电阻和接触电阻率，同时将短沟道效应和漏电最小化。
通过以下详细描述可以更好地理解这些和其他优点。
附图说明
图1A是FinFET器件的透视图，示出了将被移除以形成凹槽的鳍区域。
图1B是在形成各向异性凹槽之后图1A的FinFET器件的侧视图。
图1C是在各向同性凹槽形成之后的SOI FinFET器件的侧视图。
图2是在通过根据本公开的方面的选择性外延生长工艺在凹槽中沉积异质结构的源极/漏极区域之后的图1B的FinFET器件的侧视图。
图3是在对源极/漏极区域进行注入掺杂之后的图2的FinFET器件的侧视图。
图4是在对源极/漏极区域进行退火之后的图3的FinFET器件的侧视图。
图5是根据本公开的方面的制造具有异质结构的源极/漏极区域的FinFET的方法的流程图。
图6是包含图4的FinFET器件的示例设备的框图。
通过参考下面的详细描述，可以最好地理解本发明的实施例及其优点。应当理解，相同的附图标记用于标识一个或多个附图中所图示的相同元件。
具体实施方式
提供一种n型FinFET器件的异质结构的源极/漏极区域，其减小了总串联电阻并提供改善的电流驱动能力。使用选择性外延生长(SEG)工艺沉积异质结构的源极/漏极区域，以利用至少3个外延层来填充硅鳍内的与栅极间隔器相邻的凹槽。异质结构的源极/漏极区域的未掺杂硅的第一外延缓冲层对该凹槽加衬。利用磷(Ph)注入掺杂首先覆盖缓冲层的未掺杂硅锗(SiGe)的第二外延层。第三(帽)外延层覆盖SiGE层并且利用磷进行原位掺杂并且也利用砷(As)进行注入掺杂。
控制SiGe外延层的注入掺杂的能量，以便磷掺杂的预期范围(Rp)位于邻近SiGe外延层与帽外延层的界面处的SiGe外延层内。类似地，控制帽外延层中砷注入的能量，以便砷掺杂的预期范围位于帽外延层内，并且不会渗透到SiGe外延层中。与SiGe外延层中的n型掺杂剂浓度相比，所得到的帽外延层的掺杂导致帽外延层中更高的n型掺杂剂浓度。用于FinFET器件的异质结构的源极/漏极区域非常有利，因为SiGE外延层提供低的源极-漏极电阻，而帽外延层减小了接触电阻率。另外，异质结构的源极/漏极区域的掺杂提供浅的结深度以最小化短沟道效应。通过以下示例实施例可以更好地理解这些有利特性。
体FinFET和绝缘体上硅(SOI)FinFET架构均受益于本文公开的异质结构的源极/漏极区域。图1A中示出了在蚀刻硅鳍110中的源极/漏极凹槽115之前的体FinFET 100。硅鳍110从体硅衬底105蚀刻并由浅沟槽隔离区域140隔离。栅极电极120(例如，多晶硅、金属碳化物、金属氮化物、金属硅化物或FinFET领域中已知的其他合适材料)和间隔器(例如，氮化硅、氧化硅或其他合适的介电材料)130和125形成在鳍110上。鳍110的侧壁可以具有<110>晶向，这对于n型FinFET是常规的。在备选的实施例中可以使用其他定向。在形成鳍和栅极的情况下，蚀刻凹槽115，如在图1B中所示。可以使用湿法蚀刻或干法蚀刻。诸如反应离子蚀刻(RIE)工艺的干法蚀刻形成各向异性蚀刻，使得凹槽115的侧边缘与间隔器130(或125)的侧边界齐平或对齐。备选地，如图1C中所示，对于包括将鳍110与衬底105分离的掩埋氧化物层160的绝缘体上硅(SOI)架构，可以对凹槽115进行湿法蚀刻，使得凹槽115各向同性地底切间隔器130。如图1C中所示，蚀刻通常发生在一对栅极电极120和它们对应的间隔器130之间。为了清楚地图示，图1B仅示出了一个栅极电极120和间隔器130。
不管是使用各向同性蚀刻工艺还是各向异性蚀刻工艺来形成凹槽115，然后都使用选择性外延生长工艺利用第一外延未掺杂硅缓冲层200对凹槽115加衬，如图2中所示。凹槽115的深度和缓冲层200的厚度取决于特定的工艺节点。对于14nm技术节点，在一个实施例中，从鳍110的上表面开始的凹槽115的深度为45nm。类似地，在14nm技术节点中，缓冲层200的深度可以为大约8nm。缓冲层200用于最小化结漏电并控制到沟道和体的扩散率。另外，缓冲层200使所得到的n型FinFET器件的冶金结中的缺陷最小化。
然后，在凹槽115中的缓冲层200之上SEG沉积未掺杂的外延SiGe层205。在n型FinFET的异质结构的源极/漏极中使用SiGe是反直觉的，因为其通常用于p型FinFET的应变工程，但是这里已发现，其在n型FinFET中的使用可以最小化所得到的鳍110中源极/漏极区域的本征体电阻率。在这方面，无论退火温度如何，硅锗的本征体电阻都明显低于硅。例如，在700℃的退火温度下，磷掺杂的SiGe的方块电阻(欧姆/平方厘米)约为30欧姆/cm2，而多晶硅的方块电阻约为300欧姆/cm2。SiGE层205的厚度取决于技术节点，但在14nm技术节点实施例中可以大于15nm或甚至大于20nm。这种厚度提供残余应变弛豫。最后，在SiGe层205之上SEG沉积外延硅帽层210，以完成具有凹槽115的异质结构的源极/漏极沉积。帽层210的厚度也取决于技术工艺节点，并且对于14nm技术工艺节点实施例，厚度可以小于17nm。与其他层不同，在SEG沉积期间，利用诸如磷的n型掺杂剂对帽层210进行原位掺杂。凹槽115内的SEG沉积将自然地形成琢面，因为选择性外延生长在某些晶体取向中优选。因此，必须控制SEG沉积，使得来自一个鳍110的琢面不会与相邻鳍110上的琢面短接。本文公开的异质结构的SEG沉积提供减小的串联总电阻和接触电阻率，尽管SEG沉积受到限制以防止这种琢面的过度生长。
然后，使用离子注入工艺来掺杂硅锗层205和帽层210，如图3中所示。注意，硅锗中的砷和磷掺杂剂的扩散率比硅中的更快。因此，与硅帽层210中的扩散率相比，这种掺杂剂在硅锗层205中的扩散率将更大。无论扩散是发生在硅锗中还是硅中，还要注意，与砷的扩散相比，磷的扩散发生得更快，因为磷具有相当低的摩尔质量。因此，与磷离子注入相比，砷离子注入将在更小的距离上扩散。因此，砷是被注入到帽层210中以最小化由于过度扩散到沟道中的短沟道效应的n型掺杂剂。例如，可以使用大约3K电子伏的能量来注入砷，以确保砷预期范围300保留在帽层210内并且不会延伸到硅锗层205中。所得到的砷注入降低了帽层210的肖特基势垒高度(SBH)，使得对FinFET器件的接触电阻减小。在这方面，鳍110的宽度应当小于栅极电极120的长度，以实现减少的漏致势垒降低(DIBL)。鳍110的这种相对窄的宽度使得实现降低的接触电阻率成为问题。但凹槽115内的异质结构的SEG沉积解决了困扰现有技术的接触电阻率的问题。
与砷注入相比，磷的注入能量应当足够稳健以确保磷预期范围305位于硅锗层205内和帽层210下方。以这种方式，防止了相对较快扩散的磷以任何显著的浓度注入到帽层210内，使得它不会扩散到沟道中并加重所得到的n型FinFET器件的短沟道效应。例如，可以使用大约6K电子伏的注入能量进行磷注入来确保磷预期范围305的合适深度。
离子注入对鳍110内的晶格造成相当大的损坏，甚至可以使其呈现非晶晶向。因此，在离子注入之后对源极/漏极区域进行退火，以便晶格可以通过例如固相或液相再生而重结晶。离子注入本身可以与退火工艺(诸如在热离子注入工艺中)结合。图4中示出了在离子注入和退火之后的n型FinFET器件400。砷离子和磷离子的横向扩散导致缓冲层200的侧向闭塞，缓冲层200现在仅位于凹槽115的下部。硅锗层205已经横向扩散并且是n+掺杂的，而帽层210是n++掺杂的。在一个实施例中，可以认为在凹槽115内所得到的缓冲层200、n+掺杂的硅锗层205和n++掺杂的硅帽层210的组合在凹槽内形成了用于减小n型FinFET器件的总串联电阻和接触电阻的异质结构的装置，该异质结构的装置包括n型掺杂的硅锗层。
现在将关于图5的流程图讨论诸如FinFET 400中的FinFET源极/漏极区域的制造方法。方法开始于在n型FinFET器件的硅鳍内蚀刻与栅极间隔器相邻的凹槽的步骤500。方法还包括外延沉积硅缓冲层200以对该凹槽加衬的动作505。方法还包括在该凹槽内的硅缓冲层之上外延沉积硅锗层的动作510。最后，方法包括在硅锗层之上外延沉积硅帽层的动作515。
本文公开的减小的总串联电阻和接触电阻率可以有利地用于如图6中所示的设备600中的片上系统(SoC)605内的n型FinFET。设备600可以包括蜂窝电话、智能电话、个人数字助理、平板计算机、膝上型计算机、数码相机、手持式游戏设备或其他合适的设备。SoC605在系统总线615上与诸如传感器的多个外围设备610通信，系统总线615还耦合到诸如DRAM 620的存储器和显示控制器625。显示控制器625又耦合到驱动显示器635的视频处理器630。
如本领域技术人员现在将理解并且取决于当前的特定应用，在不脱离本公开的范围的情况下，可以对本公开的器件的材料、装置、配置和使用方法进行许多修改、替换和变化。鉴于此，本公开的范围不应当限于本文所图示和所描述的特定实施例的范围(因为它们仅仅是本公开的一些实例的方式)，而是应当与以下所附权利要求及其功能等同完全相称。

Claims (27)

1.一种n型FinFET器件，包括：
具有间隔器的栅极；
具有与所述间隔器相邻的凹槽的硅鳍；
在所述凹槽内的n型掺杂硅锗层；和
覆盖所述n型掺杂硅锗层的n型掺杂硅帽层。
2.根据权利要求1所述的n型FinFET器件，其中所述凹槽具有与所述间隔器的侧边缘对齐的侧边缘。
3.根据权利要求1所述的n型FinFET器件，其中所述凹槽具有底切所述间隔器的侧边缘的侧边缘。
4.根据权利要求1所述的n型FinFET器件，还包括与所述硅鳍相邻的浅沟槽隔离区域。
5.根据权利要求1所述的n型FinFET器件，还包括在所述硅鳍下方的掩埋氧化物区域。
6.根据权利要求1所述的n型FinFET器件，还包括：
对所述凹槽加衬的硅缓冲层，其中所述n型掺杂硅锗层位于所述硅缓冲层和所述n型掺杂硅帽层之间。
7.根据权利要求6所述的n型FinFET器件，其中所述硅缓冲层、所述n型掺杂硅锗层和所述n型掺杂硅帽层都是选择性外延生长层。
8.根据权利要求6所述的n型FinFET器件，其中所述n型掺杂硅帽层掺杂有砷和磷，并且其中所述n型掺杂硅锗层掺杂有磷。
9.根据权利要求8所述的n型FinFET器件，其中所述n型掺杂硅锗层中的所述磷掺杂是离子注入，所述离子注入具有在所述n型掺杂的掺杂硅锗层内达到峰值的预期范围，所述峰值与所述n型掺杂硅锗层和所述n型掺杂硅帽层之间的界面相邻。
10.根据权利要求8所述的n型FinFET晶体管，其中所述n型掺杂硅帽层中的所述砷掺杂是离子注入，所述离子注入具有在所述n n型掺杂硅帽层内达到峰值的预期范围。
11.根据权利要求8所述的n型FinFET器件，其中所述n型掺杂硅帽层中的所述磷掺杂是原位磷掺杂。
12.根据权利要求1所述的n型FinFET器件，其中所述凹槽具有圆形的底部。
13.根据权利要求1所述的n型FinFET器件，其中所述n型掺杂硅帽层的n型掺杂剂浓度大于所述n型掺杂硅锗层的n型掺杂剂的浓度。
14.根据权利要求1所述的n型FinFET器件，其中所述n型FinFET器件被包括在选自由蜂窝电话、智能电话、个人数字助理、平板计算机、膝上型计算机、数码相机和手持式游戏设备组成的组的设备中。
15.一种制造FinFET器件的方法，包括：
在n型FinFET器件的硅鳍内蚀刻与栅极间隔器相邻的凹槽；
外延沉积硅缓冲层以对所述凹槽加衬；
在所述凹槽内的所述硅缓冲层之上外延沉积硅锗层；以及
在所述硅锗层上外延沉积硅帽层。
16.根据权利要求15所述的方法，其中外延沉积所述硅帽层还包括利用n型掺杂剂原位掺杂所述硅帽层。
17.根据权利要求16所述的方法，其中所述n型掺杂剂是磷。
18.根据权利要求15所述的方法，其中外延沉积所述硅锗层不包括对所述硅锗层进行原位掺杂。
19.根据权利要求15所述的方法，其中蚀刻所述凹槽是反应离子蚀刻，所述反应离子蚀刻各向异性地蚀刻所述凹槽，以便具有与所述栅极间隔器的侧边缘对齐的侧边缘。
20.根据权利要求15所述的方法，其中蚀刻所述凹槽是湿法蚀刻，所述湿法蚀刻各向同性地蚀刻所述凹槽，以便具有底切所述栅极间隔器的侧边缘的侧边缘。
21.根据权利要求15所述的方法，还包括：
利用砷对所述硅帽层进行离子注入；以及
利用磷对所述硅锗层进行离子注入。
22.根据权利要求21所述的方法，还包括在所述离子注入之后对所述硅帽层和所述硅锗层进行退火。
23.一种n型FinFET器件，包括：
具有间隔器的栅极；
具有与所述间隔器相邻的凹槽的硅鳍；和
填充所述凹槽的异质结构的装置，用于减小所述n型FinFET器件的总串联电阻和接触电阻，所述异质结构的装置包括n型掺杂硅锗层。
24.根据权利要求23所述的n型FinFET器件，其中所述凹槽具有与所述间隔器的侧边缘对齐的侧边缘。
25.根据权利要求23所述的n型FinFET器件，其中所述凹槽具有底切所述间隔器的侧边缘的侧边缘。
26.根据权利要求23所述的n型FinFET器件，还包括与所述硅鳍相邻的浅沟槽隔离区域。
27.根据权利要求23所述的n型FinFET器件，还包括在所述硅鳍下方的掩埋氧化物区域。
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