CN109585554A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN109585554A
CN109585554A CN201810688284.6A CN201810688284A CN109585554A CN 109585554 A CN109585554 A CN 109585554A CN 201810688284 A CN201810688284 A CN 201810688284A CN 109585554 A CN109585554 A CN 109585554A
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CN109585554B (zh
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高琬贻
柯忠祁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了包括具有多个间隔件层的间隔件部件的半导体器件结构。在一个实例中，半导体器件包括：衬底上的有源区，有源区包括源极/漏极区域；位于有源区上方的栅极结构，源极/漏极区域靠近栅极结构；间隔件部件，该间隔件部件具有沿着栅极结构的侧壁的第一部分并且具有沿着源极/漏极区域的第二部分，其中，间隔件部件的第一部分包括沿着栅极结构的侧壁的块状间隔件层，其中，间隔件部件的第二部分包括块状间隔件层和处理的密封间隔件层，处理的密封间隔件层沿着源极/漏极区域设置并且位于块状间隔件层和源极/漏极区域之间；以及位于间隔件部件上的接触蚀刻停止层。本发明的实施例还涉及半导体器件及其形成方法。

Description

半导体器件及其形成方法
技术领域
本发明的实施例涉及半导体器件及其形成方法。
背景技术
在追求更高的器件密度、更高的性能和更低的成本的过程中，随着半导体工业已经进入纳米技术工艺节点，来自制造和设计问题的挑战已经引起了诸如鳍式场效应晶体管(FinFET)的三维设计的发展。典型的FinFET制造有从衬底延伸的鳍结构，例如通过蚀刻至衬底的硅层中。在垂直鳍中形成FinFET的沟道。在鳍结构上方(例如，上面以包裹)提供栅极结构。在沟道上具有栅极结构允许栅极结构周围的沟道的栅极控制是有益的。FinFET器件具有许多优势，包括减少短沟道效应和增加电流。
随着器件尺寸持续按比例缩小，可以通过使用金属栅电极而不是典型的多晶硅栅电极来改进FinFET器件的性能。形成金属栅极堆叠件的一个工艺是形成替换栅极的工艺(也称为“后栅极”工艺)，其中“后”制造最终的栅极堆叠件。然而，在先进的工艺节点中实现这种IC制造工艺存在挑战。在栅极制造期间对沉积和图案化工艺的不准确和不适当的控制可能严重恶化器件结构的电性能。
发明内容
本发明的实施例提供了一种半导体器件，包括：衬底上的有源区，所述有源区包括源极/漏极区域；栅极结构，位于所述有源区上方，所述源极/漏极区域靠近所述栅极结构；间隔件部件，具有沿着所述栅极结构的侧壁的第一部分并且具有沿着所述源极/漏极区域的第二部分，其中，所述间隔件部件的第一部分包括沿着所述栅极结构的侧壁的块状间隔件层，其中，所述间隔件部件的第二部分包括所述块状间隔件层和处理的密封间隔件层，所述处理的密封间隔件层沿着所述源极/漏极区域设置并且位于所述块状间隔件层和所述源极/漏极区域之间；以及接触蚀刻停止层，位于所述间隔件部件上。
本发明的另一实施例提供了一种用于形成半导体器件的方法，包括：通过使用第一工艺气体的第一原子层沉积工艺在衬底上形成密封间隔件层；通过第二工艺气体等离子体处理所述密封间隔件层以形成处理的密封间隔件层，其中，所述第一工艺气体与所述第二工艺气体不同；通过使用所述第一工艺气体的第二原子层沉积工艺在所述处理的密封间隔件层上形成块状间隔件层；以及沿着栅极结构的侧壁将所述处理的密封间隔件层和所述块状间隔件层图案化成栅极间隔件部件。
本发明的又一实施例提供了一种用于形成半导体器件的方法，包括：沿着衬底上的栅极结构的侧壁形成间隔件部件，所述间隔件部件包括处理的密封间隔件层和块状间隔件层，其中，所述栅极结构形成在有源区上方，所述有源区包括所述衬底上的源极/漏极区域，所述源极/漏极区域靠近所述栅极结构；以及沿着所述栅极结构的侧壁去除所述栅极结构和所述处理的密封间隔件层的至少部分，其中，去除所述栅极结构的同时保持沿着所述源极/漏极区域的所述处理的密封间隔件层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的用于在衬底上制造器件结构的示例性工艺的流程图；
图2示出了根据一些实施例的半导体器件结构的立体图；以及
图3A至图3B、图4A至图4B、图5A至图5B、图6A至图6B、图7A至图7B、图8A至图8B、图9A至图9B、图10A至图10B、图11A至图11B、图12A至图12B、图13A至图13B、图14A至图14B、图15A至图15B和图16A至图16B示出了根据一些实施例的处于图1的不同制造阶段的半导体器件结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明通常涉及半导体器件，并且更具体地涉及形成在半导体器件中的替换栅极。本发明提供了用于制造具有良好耐等离子体性的间隔件结构的方法，使得在完成替换栅极制造工艺之后，间隔件结构可以保持期望的完整轮廓。在一个实施例中，间隔件结构可以包括具有不同膜特性的多个间隔件层。可以在其它工艺中、在其它器件中和/或对其它层使用本发明的一些方面的实施方式。例如，其它示例器件可以包括平面FET、水平全环栅(HGAA)FET、垂直全环栅(VGAA)FET和其它器件。描述了示例方法和结构的一些变型。本领域普通技术人员将容易理解，可以作出的其它修改预期在其它实施例的范围内。虽然以特定顺序讨论了方法实施例，但是各个其它方法实施例可以以任何逻辑顺序实施并且可以包括本文中描述的更少或更多的步骤。
在用于形成晶体管的金属栅极的替换栅极工艺中，在衬底上方形成伪栅极堆叠件作为用于之后在衬底上形成的实际栅极堆叠件的预留位置。围绕伪栅极堆叠件形成间隔件结构。在形成源极/漏极部件之后，邻近间隔件结构形成接触蚀刻停止层(CESL)和层间介电(ILD)层，去除伪栅极堆叠件，留下由间隔件结构、CESL和ILD层围绕的开口。之后，在由间隔件结构、CESL和ILD限定的开口中形成金属栅极。
金属栅极结构包括栅极介电层，诸如高k介电层、可选阻挡层、功函调整层和金属栅电极。可以使用多个沉积和图案化工艺来形成功函调整层，例如以微调晶体管的阈值电压(Vt)。在一些实施例中，针对诸如p型FinFET或n型FinFET的不同类型的晶体管，功函调整层可以利用不同的材料，以根据需要增强器件电性能。阻挡层可选地用于在图案化工艺期间保护栅极介电层。
图1示出了实施为用于形成半导体器件结构(诸如图2中示出的简化的FINFET器件结构201)的工艺100的示例性流程图。未在图2中示出或描述的其它方面可以从以下附图和描述中变得明显。图2中的结构可以以例如一个晶体管或更多个晶体管的方式电连接或耦合。图3A至16B是根据一些实施例的对应工艺100的各个阶段的衬底的部分的示意性截面图。应该注意，工艺100可以用于形成任何合适的结构，包括图2至图16B中示出的半导体器件结构201或本文未呈现的其它半导体结构。
在衬底70上形成图2中示出的简化的FINFET器件结构201。衬底70可以是或包括块状半导体衬底、绝缘体上半导体(SOI)衬底或其它衬底。衬底70的半导体材料可以包括或是选自硅(例如，像Si<100>或Si<111>的晶体硅)、硅锗、锗、砷化镓或其它半导体材料的至少一种的材料。半导体材料可以是掺杂或未掺杂的，诸如用p型或n型掺杂剂。在SOI结构用于衬底70的一些实施例中，衬底70可以包括设置在绝缘层上的半导体材料，该绝缘层可以是设置在半导体衬底中的掩埋绝缘体，或可以是玻璃或蓝宝石衬底。在本文示出的实施例中，衬底70是含硅材料，诸如晶体硅衬底。此外，衬底70不限于任何特定的尺寸、形状或材料。衬底70可以是具有200mm直径、300mm直径或其它直径(诸如450mm)等的圆化/圆形衬底。衬底70也可以是任何多边形、正方形、矩形、弯曲或其它非圆形工件，诸如根据需要的多边形衬底。
每个鳍结构74均提供形成一个或多个器件的有源区域。使用包括掩模、光刻和/或蚀刻工艺的合适工艺来制造鳍结构74。在实例中，在衬底70上面形成掩模层。光刻工艺包括在掩模层上面形成光刻胶层(抗蚀剂)，将光刻胶层曝光成图案，实施曝光后烘烤工艺以及显影光刻胶以图案化光刻胶层。使用合适的蚀刻工艺将光刻胶层的图案转移至掩模层以形成掩模元件。之后，掩模元件可以用于保护衬底70的区域，同时蚀刻工艺在衬底内形成凹槽76，留下延伸的鳍，诸如鳍结构74。可以使用反应离子蚀刻(RIE)和/或其它合适的工艺来蚀刻凹槽76。可以利用在衬底上形成鳍结构的方法的许多其它实施例。
在实施例中，鳍结构74的宽度为约10纳米(nm)并且高度在从约10nm至60nm的范围内，诸如约50nm高。然而，应该理解，其它尺寸可以用于鳍结构74。在一个实例中，鳍结构74包括硅材料或诸如锗的另一元素半导体或包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体。鳍结构74也可以是包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或它们的组合的合金半导体。此外，鳍结构74可以根据需要使用n型和/或p型掺杂剂掺杂。
如所描述的，在实例中，可以通过蚀刻掉衬底70的部分以在衬底70中形成凹槽76来形成多个鳍结构74。之后，可以用隔离材料填充凹槽76，凹进或回蚀刻隔离材料以形成隔离结构78。用于隔离结构78和/或鳍结构74的其它制造技术是可能的。隔离结构78可以隔离衬底70的一些区域，例如，鳍结构74中的有源区。在实例中，隔离结构78可以是浅沟槽隔离(STI)结构和/或其它合适的隔离结构。STI结构可以由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其它合适的绝缘材料形成。STI结构可以包括例如具有一个或多个衬垫层的多层结构。
在鳍结构74上方形成伪栅极结构212。在图2所示的实例中，伪栅极结构212包括栅极介电层80、栅电极层82和硬掩模84。应该注意，伪栅极结构212还可以包括覆盖层和/或其它合适的层。伪栅极结构212中的各个层可以通过合适的沉积技术形成并且通过合适的光刻和蚀刻技术图案化。伪栅极结构212在鳍结构74的两侧或三侧接合鳍结构74。源极/漏极区域52a和52b设置在鳍结构74的相对于伪栅极结构212的相对区域中。如图所示，例如，可以在各个晶体管之间共享一些源极/漏极区域，并且未示出为共享的其它源极/漏极区域可以与未示出的相邻晶体管共享。在一些实例中，各个源极/漏极区域可以连接或耦合在一起，从而使得FinFET实现为两个功能晶体管。例如，如果相邻(例如，与相对相反)的源极/漏极区域52a、52b电连接，诸如通过外延生长合并该区域(例如，相邻的源极/漏极区域，与伪栅极结构212的相对侧相反，被合并)，则可以实现两个功能晶体管。其它实例中的其它配置可以实现其它数量的功能晶体管。
如此处描述的术语“伪”是指牺牲结构，其将在后期阶段中被去除并且将在替换栅极工艺中用诸如高k电介质和金属栅极结构的另一结构替换。替换栅极工艺是指在整个栅极制造工艺的后期阶段制造栅极结构。栅极介电层80可以是介电氧化物层。例如，可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其它合适的方法形成介电氧化物层。栅电极层82可以是多晶硅层或其它合适的层。例如，可以通过诸如低压化学汽相沉积(LPCVD)和等离子体增强CVD(PECVD)的合适沉积工艺来形成栅电极层82。硬掩模84可以是适合于将衬底上的栅电极层82图案化为具有期望的部件/尺寸的任何合适的材料。
在实施例中，将伪栅极结构212的各个层首先沉积为毯式层。之后，通过包括光刻和蚀刻工艺的工艺来图案化毯式层，去除毯式层的部分并且保留隔离结构78和鳍结构74上方的剩余部分以形成伪栅极结构212。
在实例中，半导体器件结构201包括p型器件区域250a和n型器件区域250b。可以在p型器件区域250a中形成诸如p型FinFET的一个或多个p型器件，并且可以在n型器件区域250b中形成诸如n型FinFET的一个或多个n型器件。半导体器件结构201可以包括在诸如微处理器、存储器器件的IC和/或其它IC中。
图2进一步示出了在之后的附图中使用的参考截面。截面A-A是沿着例如相对的源极/漏极区域52a、52b之间的鳍结构74中的沟道的平面。截面B-B是垂直于截面A-A的平面并且横跨鳍结构74中的源极/漏极区域52a。为了清楚起见，随后的附图涉及这些参考截面。以下以“A”符号结尾的附图示出了对应于截面A-A的各个工艺阶段的截面图，以及以下以“B”符号结尾的附图示出了对应于截面B-B的各个工艺阶段的截面图。在一些附图中，可以省略其中示出的组件或部件的一些参考标号以避免模糊其它组件或部件；这是为了便于描述附图。
回参照图1中示出的工艺100，工艺100从操作102开始，通过提供衬底70(如图3A至图3B所示的)准备用于制造将在衬底70上形成的诸如半导体器件201的半导体器件。
在操作104中，如图4A至图4B所示，实施蚀刻工艺以在衬底70中形成限定衬底70中的鳍结构74的凹槽76。掩模72(例如，硬掩模)用于促进在衬底70中形成鳍结构74。例如，在半导体衬底70上方沉积一个或多个掩模层，并且之后将一个或多个掩模层图案化成掩模72。在一些实例中，一个或多个掩模层可以包括氮化硅、氮氧化硅、碳化硅、碳氮化硅等或它们的组合，并且可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)或其它沉积技术来沉积。可以使用光刻图案化一个或多个掩模层。例如，可以在一个或多个掩模层上形成光刻胶(诸如通过使用旋涂)，并且通过使用适当的光掩模将光刻胶暴露于光来图案化光刻胶。之后，取决于使用的是正性光刻胶还是负性光刻胶来去除光刻胶的曝光部分或未曝光部分。之后，可以诸如通过使用合适的蚀刻工艺将光刻胶的图案转移至一个或多个掩模层，这形成掩模72。蚀刻工艺可以包括反应离子蚀刻(RIE)、中性束蚀刻(NBE)、电感耦合等离子体(ICP)蚀刻等或它们的组合。蚀刻可以是各向异性的。随后，例如，在灰化或湿剥离工艺中去除光刻胶。
在操作106中，如图5A至图5B所示，在对应的凹槽76中的每个凹槽76中形成隔离结构78。隔离结构78可以包括或可以是诸如氧化物(诸如氧化硅)、氮化物等或它们的组合的绝缘材料，并且绝缘材料可以通过高密度等离子体CVD(HDP-CVD)、可流动CVD(FCVD)(例如，远程等离子体系统中的CVD基材料沉积以及后固化以使其转化成诸如氧化物的另一材料)等或它们的组合形成。可以使用通过任何可接受的工艺形成的其它绝缘材料。在示出的实施例中，隔离结构78包括由FCVD工艺形成的氧化硅。诸如化学机械抛光(CMP)的平坦化工艺可以去除任何过量的绝缘材料和任何剩余的掩模(例如，用于蚀刻凹槽76并且形成鳍结构74)以使绝缘材料的顶面和鳍结构74的顶面形成为基本共面。之后，可以使绝缘材料凹进以形成隔离结构78。使绝缘材料凹进，从而使得鳍结构74从相邻的隔离结构78之间突出，这可以至少部分地将鳍结构74划定为半导体衬底70上的有源区。可以使用可接受的蚀刻工艺(诸如对绝缘材料的材料有选择性的工艺)使绝缘材料凹进。
例如，可以使用采用蚀刻或应用材料公司的SICONI工具或稀释的氢氟酸(dHF)的化学氧化物去除。此外，隔离结构78的顶面可以具有如图所示的平坦表面，可以由蚀刻工艺产生的凸表面、凹表面(诸如凹陷)或它们的组合。
在操作108中，如图6A至图6B所示，在衬底上形成伪栅极结构212。伪栅极结构212位于鳍结构74上方并且垂直于鳍结构74横向延伸。每个伪栅极结构212均包括栅极介电层80、栅电极层82和硬掩模84。在替换栅极工艺中，栅极介电层80可以是界面电介质。可以通过依次形成各个层，并且之后将这些层图案化成伪栅极结构212来形成用于伪栅极结构212的栅极介电层80、栅电极层82和硬掩模84。例如，用于界面电介质的层可以包括或可以是氧化硅、氮化硅等或它们的多层，并且可以在鳍结构74上热和/或化学生长，或诸如通过PECVD、ALD或其它沉积技术共形沉积。用于栅电极层82的层可以包括或可以是通过CVD、PVD或其它沉积技术沉积的硅(例如，多晶硅)或另一材料。用于硬掩模84的层可以包括或可以是通过CVD、PVD、ALD或其它沉积技术沉积的氮化硅、氮氧化硅、碳氮化硅等或它们的组合。之后，可以例如使用如以上描述的光刻和一个或多个蚀刻工艺来图案化用于硬掩模84、栅电极层82和栅极介电层80的层，以形成用于每个伪栅极结构212的硬掩模84、栅电极层82和栅极介电层80。
在一些实施例中，在形成伪栅极结构212之后，可以在有源区中形成轻掺杂漏极(LDD)区域(未具体示出)。例如，可以使用伪栅极结构212作为掩模将掺杂剂注入至有源区(例如，鳍结构74)中。示例性掺杂剂可以包括或可以是例如用于p型器件的硼和用于n型器件的磷或砷，但是可以使用其它掺杂剂。LDD区域可以具有在从约1015cm-3至约1017cm-3的范围内的掺杂剂浓度。
在操作110中，如图7A至图7B所示，在伪栅极结构212的侧壁上形成密封间隔件层86。密封间隔件层86共形地形成在衬底70上。在一个实例中，密封间隔件层86由介电常数小于4的材料(诸如低k介电材料)形成。例如，密封间隔件层86可以由包含碳氧化硅(SiOC)材料的材料制造。在一个具体实例中，密封间隔件层86由不含氮的碳氧化硅(SiOC)材料制造。
在一个实例中，可以通过任何合适的沉积工艺形成密封间隔件层86。在一个具体实例中，可以通过原子层沉积(ALD)工艺形成密封间隔件层86。在一个实例中，在ALD工艺中使用的工艺气体可以包括包含硅(Si)和碳(C)源的含硅和碳前体以及包含氧源的含氧前体。硅(Si)和碳(C)源以及含氧前体可以在原子层沉积工艺期间交替供应。在一个具体实例中，含硅和碳前体是不含氮的含硅和碳前体。在一些实例中，含硅和碳前体可以具有作为其特定化学/功能结构的主要Si-C-Si(硅-碳-硅)线性键合结构。应当认为，硅键之间结合的碳的数量可以影响所得到的膜层的密度，从而可以通过控制硅键之间形成的碳的数量来调整或改变膜介电常数。应当认为，碳原子的数量越多，可以获得的所得到的膜层的介电常数就越低。
此外，主要由Si-C-Si线性键合结构形成的膜层也认为具有比主要由Si-O-Si、Si-OH或其它含硅键合形成的膜层更低的密度。因此，通过选择具有作为其特定化学/功能结构的Si-C-Si(硅-碳-硅)线性键合结构的前体，可以获得具有相对较低的介电常数(例如，小于4，诸如约3.0-3.5)的密封间隔件层86。含硅和碳前体的合适的实例包括SiCl3-CH2-SiCl3、SiCl2-(CH2)2-SiCl2、SiCl-(CH2)3-SiCl、SiCl2＝C＝SiCl2等。应该注意，附接至键合结构末端的氯元素可以认为是在化学反应期间将经历热解过程的离去基团，从前体的主要Si-C-Si键合结构离开以触发反应。因此，根据需要也可以利用包含诸如Br、F等的其它元素的其它合适的离去基团。含氧前体的合适的实例包括水蒸汽(H2O)、O2、O3、CO、CO2等。
在操作110中的密封间隔件层ALD沉积工艺期间，可以可选地供应包括硅和碳源前体和含氧前体的不同气体以用于反应。ALD工艺的循环包括交替流动(或脉冲)和清除操作，其中，每个前体均在循环期间流动(或脉冲)并且随后清除至少一次。例如，硅和碳源前体流入ALD工具室中，其中衬底(例如，在其上形成器件结构，例如，如图7A至图7B示出的)转移至ALD工具室内，并且随后，从ALD工具室清除硅和碳源前体。在一些实例中，硅和碳源前体可以在清除之前与衬底上可用的反应位点反应。在一些实例中，反应可以使反应位点饱和，或硅和碳源前体可能不与衬底上可用的一些反应位点反应。在清除硅和碳源前体之后，之后氧源前体流入ALD工具室中，并且随后，从ALD工具室清除氧源前体。类似地，在一些实例中，氧源前体可以在清除之前与衬底上可用的反应位点反应。在一些实例中，反应可以使反应位点饱和，或氧源前体可能不与衬底上可用的一些反应位点反应。
交替的硅和碳源前体和氧源前体之间的脉冲和清除的循环可以实施任意次数，直至形成密封间隔件层86的所需厚度。总沉积时间可以在从300秒至900秒的范围内，诸如约600秒。交替的硅和碳源前体和氧源前体之间的总循环可以在从约15次循环至20次循环的范围内，诸如约18次循环。
在一个实例中，密封间隔件层86可以具有在从约3.2至约3.7(诸如约3.5)的介电常数。
应该注意，此处描述的密封间隔件层86可以形成为牺牲层和/或表面保护层以提供界面保护层，该界面保护层可以防止随后形成在其上的膜堆叠件免受随后的蚀刻/图案化工艺的损坏。因此，密封间隔件层86的厚度可以控制在足以提供界面保护的范围内。在一个实例中，密封间隔件层86可以具有在从至的范围内(诸如从至)的厚度。
在操作112中，如图8A至图8B所示，对密封间隔件层86实施等离子体处理工艺。如图8A至图8B示出的，等离子体处理工艺通过等离子体83处理密封间隔件层86以改变衬底表面性质，形成处理的密封间隔件层87。等离子体表面处理工艺可以有效地包含与密封间隔件层86中的不饱和键反应的某些元素，以改进键合能量并且使膜结构致密以形成具有相对较高的膜密度的处理的密封间隔件层87。来自处理的密封间隔件层87的更高的膜密度可以在伪栅极去除工艺期间使界面和随后形成在其上的膜堆叠件免受等离子体的损坏。此外，也可以实施处理工艺以修改密封间隔件层86的表面的形貌和/或表面粗糙度，以改进处理的密封间隔件层87的粘附性和鲁棒性。在一个实施例中，表面处理工艺可以产生表面粗糙度在从约至约的范围内的粗糙表面。
在一个实施例中，可以通过将包含含氢气体或惰性气体的工艺气体供应至等离子体工艺室中来实施表面处理工艺。含氢气体可以选自H2、H2O、H2O2、它们的组合等。在一个示例性实施例中，用于实施衬底处理工艺的含氢气体包括H2气。此外，在某些实施例中，工艺气体可以包括实施表面处理工艺的惰性气体。惰性气体的实例包括Ar、He等。应该注意，用于通过使用含氢气体实施表面处理工艺的工艺参数可以被配置为与使用惰性气体的工艺参数类似。
在一个实例中，等离子体处理工艺包括由包括在等离子体工艺室中的微波发生器产生的微波等离子体。在操作112中，对于等离子体处理工艺，微波发生器可以产生在从约0.3GHz至约300GHz的频率范围内的从约10瓦至约3000瓦的范围内的微波功率。等离子体工艺时间可以控制在从约100秒至约1000秒的范围内，诸如约600秒。
如上所述，此处使用的密封间隔件层86用作界面保护层以及牺牲层，以保护随后形成在其上的膜结构免受随后的蚀刻/图案化工艺的损坏。对密封间隔件层86实施等离子处理工艺将密封间隔件层86转化为处理的密封间隔件层87。处理的间隔件层87具有致密和增强的膜结构，其为器件结构提供稳健的耐等离子性和强大的界面保护。通过这样做，随后形成在处理的密封间隔件层87上的层可以在蚀刻/图案化工艺中接收良好的等离子体保护。
在等离子体处理工艺之后，由于较高的膜密度，处理的密封间隔件层87可具有比密封间隔件层86略大的介电常数。在一个实例中，处理的密封间隔件层87具有在从3.5和3.9的范围内(诸如约3.7)的介电常数。由于等离子体处理工艺的致密化，处理的密封间隔件层87的膜密度也大于密封间隔件层86的膜密度。相反地，处理的密封间隔件层87的厚度可以缩小密封间隔件层86的厚度的在从约10％至20％的范围内。在一个实例中，处理的密封间隔件层87具有在从约至约的范围内的厚度。处理之后，对于处理的密封间隔件层87，密封间隔件层86的膜密度从1.7变为2.5。
在操作114中，如图9A至图9B所示，之后在处理的密封间隔件层87上形成块状间隔件层88。块状间隔件层88与没有对其实施等离子体处理工艺的密封间隔件层86(如图7A至图7B所示)的材料基本相同。块状间隔件层88用作半导体器件的间隔件部件89的主要结构。因此，实现块状间隔件层88的足够厚度以实现半导体器件的操作。因此，块状间隔件层88的厚度大于处理的密封间隔件层87的厚度。在一个实例中，块状间隔件层88可以具有在从约至约的厚度。
如上所述，块状间隔件层88也由介电常数小于4的材料(诸如低k介电材料)形成。例如，如上所述，块状间隔件层88可以由包含碳氧化硅(SiOC)的材料制造，与用于形成密封间隔件层86的材料相同。在一个实例中，块状间隔件层88由不含氮的碳氧化硅(SiOC)材料制造。
类似地，可以通过诸如ALD工艺的任何合适的沉积工艺形成块状间隔件层88。在一个具体实例中，可以通过原子层沉积(ALD)工艺形成块状间隔件层88，ALD工艺使用包括包含硅(Si)和碳(C)源的含硅和碳前体以及包含氧源的含氧前体。在一个实例中，含硅和碳前体是不含氮的含硅和碳前体。含硅和碳前体可以具有作为其特定化学结构的主要Si-C-Si(硅-碳-硅)线性键合结构。含硅和碳前体的合适的实例包括SiCl3-CH2-SiCl3、SiCl2-(CH2)2-SiCl2、SiCl-(CH2)3-SiCl、SiCl2＝C＝SiCl2等。含氧前体的合适的实例包括水蒸汽(H2O)、O2、O3、CO、CO2等。
在一个实例中，块状间隔件层88可以具有在从约3.2至约3.7(诸如约3.5)的介电常数。块状间隔件层88的膜密度为从约1.5至约2.0，诸如约1.7。
如上所述，由于块状间隔件层88和密封间隔件层86由相同的材料形成，因此应该理解，由于更高的膜密度，处理的密封间隔件层87可以具有比块状间隔件层88略大的介电常数。由于等离子体处理工艺的致密化，处理的密封间隔件层87的膜密度也大于块状间隔件层88的膜密度。
在操作116中，之后，图案化和各向异性地蚀刻处理的密封间隔件层87和块状间隔件层88以形成期望的轮廓，从而形成如图10A至图10B所示的间隔件部件89。间隔件部件89包括处理的间隔件层87和块状间隔件层88。应该注意，之后可以牺牲并且去除处理的间隔件层87，仅留下部分块状间隔件层88作为衬底上的间隔件部件89。蚀刻工艺可以包括RIE、NBE或其它蚀刻工艺。在实施例中，间隔件部件89包括诸如氮化硅或氮氧化硅的介电材料。
在操作118中，如图11A至图11B所示，在衬底70中形成用于源极/漏极区域的凹槽90。如图所示，凹槽90形成在伪栅极结构212的相对侧上的鳍结构74中。可以通过蚀刻工艺凹进。蚀刻工艺可以是各向同性的或各向异性的，或者可以相对于半导体衬底70的一个或多个晶面是选择性的。因此，基于实施的蚀刻工艺，凹槽90可以具有各种截面轮廓。蚀刻工艺可以是诸如RIE、NBE等的干蚀刻或诸如使用四甲基氢氧化铵(TMAH)、氢氧化铵(NH4OH)或其它蚀刻剂的湿蚀刻。
应该注意，蚀刻工艺选择性地蚀刻衬底70上的鳍结构74，同时对间隔件部件89的损坏最小。因此，当在衬底70中形成凹槽90(如图11A所示)时，去除隔离结构78之间的鳍结构74的至少部分(如图11B所示)，以及如图11B所示的间隔件部件89可以保留在衬底70上，同时具有最小的高度/宽度损失。
在操作120中，在在衬底70中形成凹槽90之后，可以实施外延沉积工艺以生长源极/漏极区域92，如图12A和图12B所示。外延源极/漏极区域92可以包括或可以是硅锗(SixGe1-x，其中，x可以介于约0和1之间)、碳化硅、硅磷、纯或基本上纯的锗、III-V族化合物半导体、II-VI族化合物半导体等。例如，用于形成III-V族化合物半导体的材料包括InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP等。可以诸如通过金属有机CVD(MOCVD)、分子束外延(MBE)、液相外延(LPE)、汽相外延(VPE)、选择性外延生长(SEG)等或它们的组合在凹槽90中外延生长材料来在凹槽90中形成外延源极/漏极区域92。如图12A至图12B示出的，由于隔离结构78和间隔件部件89的阻挡，首先在凹槽90中垂直生长外延源极/漏极区域92，在此期间外延源极/漏极区域92不水平生长。在完全填充凹槽90并且从间隔件部件89垂直向外之后，可以垂直和水平生长外延源极/漏极区域92以形成小平面，小平面可以对应于半导体衬底70的晶面。在一些实例中，对p型器件和n型器件的外延源极/漏极区域使用不同的材料。在凹进或外延生长期间适当的掩模可以允许在不同的器件中使用不同的材料。
本领域普通技术人员也将容易理解，可以省略图11A至图11B以及图12A至图12B的凹进和外延生长，并且可以通过使用伪栅极结构212和间隔件部件89作为掩模将掺杂剂注入至鳍结构74来形成源极/漏极区域。在采用外延源极/漏极区域92的一些实例中，外延源极/漏极区域92也可以诸如通过外延生长期间的原位掺杂而掺杂和/或通过在外延生长之后将掺杂剂注入至外延源极/漏极区域92而掺杂。示例性掺杂剂可以包括或可以是例如用于p型器件的硼或用于n型器件的磷或砷，但是可以使用其它掺杂剂。外延源极/漏极区域92(或其它源极/漏极区域)可以具有在从约1019cm-3至约1021cm-3的范围内的掺杂剂浓度。因此，可以通过掺杂(例如，通过注入和/或外延生长期间的原位掺杂，如果合适的话)和/或通过外延生长来划定源极/漏极区域，如果合适的话，通过掺杂或外延生长可以进一步划定其中划定源极/漏极区域的有源区。
在操作122中，如图13A至图13B所示，形成覆盖伪栅极结构212的接触蚀刻停止层(CESL)96。CESL 96可以提供在形成例如接触件或通孔时停止蚀刻工艺的机制。接触蚀刻停止层96可以由与邻近的层或组件具有不同蚀刻选择性的介电材料形成。CESL 96形成在外延源极/漏极区域92的表面、间隔件部件89的侧壁和顶面、硬掩模84的顶面以及隔离结构78的顶面上。CESL 96可以包括或可以是含氮材料、含硅材料和/或含碳材料。此外，CESL 96可以包括或可以是氮化硅、碳氮化硅、氮化碳、氮氧化硅、碳氧化硅等或它们的组合。可以通过诸如等离子体增强ALD(PEALD)、CVD或其它沉积技术的沉积工艺来沉积CESL 96。
在操作124中，如图14A至图14B所示，在CESL 96上方形成ILD层99。ILD层99可以包括诸如正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG)、SiOxCy、旋涂玻璃)、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物和/或其它合适的介电材料的材料。可以通过旋涂、CVD、FCVD、PECVD、PVD或其它合适的沉积技术来沉积ILD层99。在实施例中，通过可流动CVD(FCVD)工艺形成ILD层99以填充在相邻的伪栅极结构212之间。应该注意，在热退火工艺之后，可以诸如通过CMP平坦化ILD层99，根据需要提供平坦表面。
在操作126中，随后，从衬底70去除伪栅极结构212以限定ILD层99中的开口50(如图15A至图15B所示)，这之后可以允许在开口50中形成诸如金属栅极结构的替换栅极结构56以继续制造半导体器件结构201，如图16A至图16B所示。回参照图15A至图15B，在伪栅极结构212的去除工艺期间，实施一系列等离子体蚀刻/图案化工艺。在一些实例中，可以实施灰化工艺和/或清除浮渣工艺以从衬底70去除蚀刻残留物。因此，衬底70上的结构(包括间隔件部件89、CESL 96和ILD层99)可能在等离子体工艺期间经历等离子体攻击，这可能导致对膜结构的不期望的损坏，特别是与伪栅极结构212直接接触的间隔件部件89。因此，通过利用包括处理的密封间隔件层87和块状间隔件层88的间隔件部件89(例如，多间隔件层结构)，处理的密封间隔件层87用作界面保护层，以在伪栅极结构移去除工艺期间直接暴露于等离子体，从而防止块状间隔件层88暴露于等离子体。此外，由于处理的密封间隔件层87具有相对致密的膜结构并且相对耐等离子体，处理的密封间隔件层87能够保持通过侵蚀性等离子体暴露并且甚至通过清除浮渣氧暴露。在清除浮渣工艺期间的氧暴露通常认为是可能不期望地影响间隔件部件89的介电常数的显著因素，因为由其产生的氧元素通常提高间隔件部件89的介电常数的值。因此，处理的密封间隔件层87的逐渐消耗使得块状间隔件层88在侵蚀性等离子体暴露期间和甚至在清除浮渣氧暴露期间受到攻击。因此，控制并且确定处理的密封间隔件层87的厚度在的适当范围内，以允许伪栅极结构去除工艺期间的侵蚀性等离子体暴露和清除浮渣氧暴露期间逐渐消耗，而不会过早耗尽，过早耗尽可能不期望地将附近的块状间隔件层89暴露于等离子体。因此，在图15A所示的处理的间隔件层87与伪栅极结构212直接接触的位置中，处理的间隔件层87被消耗并且在去除伪栅极结构212之后基本从衬底70去除，但是在其它实例中，在伪栅极结构212的去除之后，处理的间隔件层87的至少一些部分可以沿着块状间隔件层89保留在处理的间隔件层87与伪栅极结构212直接接触的位置中。相反地，在图15B所示的在没有等离子体暴露的情况下将间隔件部件89(特别地处理的密封间隔件层87)覆盖在CESL96和ILD层99下方的位置处，包括处理的密封间隔件层87和块状间隔件层88的间隔件部件89可以保留在衬底70上，靠着源极/漏极区域92的侧壁内衬。
在操作128中，在去除伪栅极结构212之后，之后，可以在开口填充并且形成替换栅极结构56。替换栅极结构56可以是金属栅极结构，包括形成在其中的界面层(未示出)、高介电常数介电层53、功函调整层54和金属电极结构55以形成金属栅极结构，如图16A至图16B所示。
虽然不旨在限制，但是本发明的一个或多个实施例提供了半导体器件及其形成的许多益处。例如，本发明的实施例可以提供在形成CESL之前用于形成具有多个膜层的间隔件部件的方法。间隔件部件可以包括密封间隔件层和块状间隔件层。等离子体处理密封间隔件层以形成处理的密封间隔件，该处理的密封间隔件层是耐等离子体的，以在随后的伪栅极去除工艺中经历等离子体暴露而不会过早消耗或耗尽。因此，在从衬底去除伪栅极结构之后，在一些位置中，处理的密封间隔件以及块状间隔件层可以保留在衬底上，而在一些位置中，仅保留块状间隔件层。
在一个实施例中，半导体器件包括衬底上的有源区(有源区包括源极/漏极区域)、位于有源区上方的栅极结构(源极/漏极区域靠近栅极结构)、间隔件部件，该间隔件部件具有沿着栅极结构的侧壁的第一部分并且具有沿着源极/漏极区域的第二部分，其中，间隔件部件的第一部分包括沿着栅极结构的侧壁的块状间隔件层，其中，间隔件部件的第二部分包括块状间隔件层和处理的密封间隔件层，处理的密封间隔件层沿着源极/漏极区域设置并且位于块状间隔件层和源极/漏极区域之间，以及位于间隔件部件上的接触蚀刻停止层。在实施例中，层间介电层位于接触蚀刻停止层上。在实施例中，块状间隔件层具有小于4的介电常数。在实施例中，块状间隔件层是不含氮的碳氧化硅材料。在实施例中，处理的密封间隔件层具有大于块状间隔件层的介电常数。在实施例中，处理的密封间隔件层具有比块状间隔件层更大的膜密度。在实施例中，栅极结构包括设置在高介电常数层上的金属栅电极。在实施例中，接触蚀刻停止层是含氮化硅的材料。在实施例中，块状间隔件层具有大于处理的密封间隔件层的厚度。
在另一实施例中，用于形成半导体器件的方法包括：通过使用第一工艺气体的第一原子层沉积工艺在衬底上形成密封间隔件层，通过第二工艺气体等离子体处理密封间隔件层以形成处理的密封间隔件层，其中，第一工艺气体与第二工艺气体不同，以及通过使用第一工艺气体的第二原子层沉积工艺在处理的密封间隔件层上形成块状间隔件层，并且沿着栅极结构的侧壁将处理的密封间隔件层和块状间隔件层图案化成栅极间隔件部件。在实施例中，等离子体处理密封间隔件层还包括通过将微波功率施加至放置衬底的等离子体工艺室来形成第二工艺气体的等离子体。在实施例中，第一工艺气体包括含硅和碳前体和含氧前体。在实施例中，含硅和碳前体是不含氮的含硅和碳前体。在实施例中，含氧前体包括水蒸汽。在实施例中，含硅和碳前体具有线性Si-C-Si键合结构。在实施例中，块状间隔件层具有大于处理的间隔件层的厚度。在实施例中，第二工艺气体包括含氢气体、惰性气体或它们的组合。
在另一实施例中，用于形成半导体器件的方法包括：沿着衬底上的栅极结构的侧壁形成间隔件部件，该间隔件部件包括处理的密封间隔件层和块状间隔件层，其中，栅极结构形成在有源区上方，有源区包括衬底上的源极/漏极区域，源极/漏极区域靠近栅极结构，并且沿着栅极结构的侧壁去除栅极结构和处理的密封间隔件层的至少部分，其中，去除栅极结构的同时保持沿着源极/漏极区域的处理的密封间隔件层。在实施例中，沿着栅极结构的侧壁去除栅极结构和处理的密封间隔件层的至少部分还包括：保持沿着栅极结构的侧壁并且沿着源极/漏极区域的块状间隔件层。在实施例中，栅极结构是伪栅极结构。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
衬底上的有源区，所述有源区包括源极/漏极区域；
栅极结构，位于所述有源区上方，所述源极/漏极区域靠近所述栅极结构；
间隔件部件，具有沿着所述栅极结构的侧壁的第一部分并且具有沿着所述源极/漏极区域的第二部分，其中，所述间隔件部件的第一部分包括沿着所述栅极结构的侧壁的块状间隔件层，其中，所述间隔件部件的第二部分包括所述块状间隔件层和处理的密封间隔件层，所述处理的密封间隔件层沿着所述源极/漏极区域设置并且位于所述块状间隔件层和所述源极/漏极区域之间；以及
接触蚀刻停止层，位于所述间隔件部件上。
2.根据权利要求1所述的半导体器件，还包括：
层间介电层，位于所述接触蚀刻停止层上。
3.根据权利要求1所述的半导体器件，其中，所述块状间隔件层具有小于4的介电常数。
4.根据权利要求1所述的半导体器件，其中，所述块状间隔件层是不含氮的碳氧化硅材料。
5.根据权利要求1所述的半导体器件，其中，所述处理的密封间隔件层具有大于所述块状间隔件层的介电常数。
6.根据权利要求1所述的半导体器件，其中，所述处理的密封间隔件层具有比所述块状间隔件层更大的膜密度。
7.根据权利要求1所述的半导体器件，其中，所述栅极结构包括设置在高介电常数层上的金属栅电极。
8.根据权利要求1所述的半导体器件，其中，所述接触蚀刻停止层是含氮化硅的材料。
9.一种用于形成半导体器件的方法，包括：
通过使用第一工艺气体的第一原子层沉积工艺在衬底上形成密封间隔件层；
通过第二工艺气体等离子体处理所述密封间隔件层以形成处理的密封间隔件层，其中，所述第一工艺气体与所述第二工艺气体不同；
通过使用所述第一工艺气体的第二原子层沉积工艺在所述处理的密封间隔件层上形成块状间隔件层；以及
沿着栅极结构的侧壁将所述处理的密封间隔件层和所述块状间隔件层图案化成栅极间隔件部件。
10.一种用于形成半导体器件的方法，包括：
沿着衬底上的栅极结构的侧壁形成间隔件部件，所述间隔件部件包括处理的密封间隔件层和块状间隔件层，其中，所述栅极结构形成在有源区上方，所述有源区包括所述衬底上的源极/漏极区域，所述源极/漏极区域靠近所述栅极结构；以及
沿着所述栅极结构的侧壁去除所述栅极结构和所述处理的密封间隔件层的至少部分，其中，去除所述栅极结构的同时保持沿着所述源极/漏极区域的所述处理的密封间隔件层。
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