TW201916360A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TW201916360A
TW201916360A TW107121124A TW107121124A TW201916360A TW 201916360 A TW201916360 A TW 201916360A TW 107121124 A TW107121124 A TW 107121124A TW 107121124 A TW107121124 A TW 107121124A TW 201916360 A TW201916360 A TW 201916360A
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semiconductor device
gate structure
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TW107121124A
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TWI666768B (zh
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高琬貽
柯忠祁
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台灣積體電路製造股份有限公司
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    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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Abstract

提供包括具有複數間隔層之間隔部件的半導體裝置結構。在一範例中，半導體裝置包括主動區，位於基板上，上述主動區包括源極/汲極區；閘極結構，位於上述主動區之上，上述源極/汲極區靠近上述閘極結構；間隔部件，沿著上述閘極結構之側壁具有第一部分且沿著上述源極/汲極區具有第二部分，其中上述間隔部件的第一部分沿著閘極結構之側壁包括主體間隔層，其中上述間隔部件的第二部分包括主體間隔層及經處理的密封間隔層，經處理的密封間隔層係沿著源極/汲極區設置且位於主體間隔層及源極/汲極區之間、以及接觸蝕刻終止層，位於間隔部件上。

Description

半導體裝置及其形成方法
本揭露係關於一種半導體裝置的製造方法，且特別是關於具有高電漿阻抗的間隔結構的製造方法。
隨著半導體工業進入奈米技術製程節點以追求更高的裝置密度、更高的性能、以及更低的成本，來自製造及設計雙方的挑戰導致了三維設計的發展，例如鰭式場效電晶體(fin field effect transistors,FinFETs)。典型的鰭式場效電晶體，舉例來說，藉由蝕刻至基板的矽層中以製造成具有自基板延伸的鰭片結構。鰭式場效電晶體的通道形成在垂直鰭片中。提供閘極結構於上述鰭片結構之上(例如，位於其上以封裹鰭片結構)。在通道上具有閘極結構對允許閘極結構周圍的通道的閘極控制是有益的。鰭式場效電晶體裝置提供許多優點，包括減少短通道效應及增加電流。
隨著裝置尺寸持續微縮化，可藉由使用金屬閘極電極取代典型多晶矽閘極電極以提升鰭式場效電晶體裝置性能。形成金屬閘極堆疊的一個製程是形成置換閘極製程(亦稱為”閘極後製”(gate-last)製程)，其中所述之最終閘極堆疊為”最後”製造。然而，在先進的製程節點中實施此類積體電路製 程存在著挑戰。在閘極製造期間的對沉積及圖案化製程的不精確和不適當控制可能不利地惡化裝置結構的電性表現。
本揭露實施例提供一種半導體裝置，上述半導體裝置包括主動區，位於基板上，上述主動區包括源極/汲極區；閘極結構，位於上述主動區之上，上述源極/汲極區靠近上述閘極結構；間隔部件，沿著上述閘極結構之側壁具有第一部分且沿著上述源極/汲極區具有第二部分，其中上述間隔部件的上述第一部分沿著上述閘極結構之側壁包括主體間隔層，其中上述間隔部件的上述第二部分包括上述主體間隔層及經處理的密封間隔層，上述經處理的密封間隔層係沿著上述源極/汲極區設置且位於上述主體間隔層及上述源極/汲極區之間、以及接觸蝕刻終止層，位於上述間隔部件上。
本揭露實施例提供一種半導體裝置的形成方法，在此方法中，包括藉由使用第一製程氣體的第一原子層沉積製程在基板上形成密封間隔層、藉由第二製程氣體電漿處理上述密封間隔層以形成經處理的密封間隔層，其中上述第一製程氣體與上述第二製程氣體不同，藉由使用上述第一製程氣體的第二原子層沉積製程在上述密封間隔層上形成主體間隔層、以及沿著閘極結構的側壁將上述經處理的密封間隔層及上述主體間隔層圖案化至閘極間隔部件中。
本揭露實施例提供另一種半導體裝置的形成方法，在此方法中，包括形成間隔部件，上述間隔部件沿著位於基板上的閘極結構的側壁包括經處理的密封間隔層及主體間 隔層，其中上述閘極結構係形成在主動區之上，上述主動區在上述基板上包括源極/汲極區，上述源極/汲極區接近上述閘極結構，以及自沿著上述閘極結構的側壁去除上述閘極結構及至少一部份的上述經處理的密封間隔層，其中去除上述閘極結構而沿著上述源極/汲極區保持經處理的密封間隔層不被去除。
50‧‧‧開口
52a、52b‧‧‧源極/汲極區
53‧‧‧高介電常數介電層
54‧‧‧功函數調整層
55‧‧‧金屬電極結構
56‧‧‧置換閘極結構
70‧‧‧基板
72‧‧‧遮罩
74‧‧‧鰭片結構
76‧‧‧凹槽
78‧‧‧隔離結構
80‧‧‧閘極介電層
82‧‧‧閘極電極層
83‧‧‧電漿
84‧‧‧硬遮罩
86‧‧‧密封間隔層
87‧‧‧經處理密封間隔層
88‧‧‧主體間隔層
89‧‧‧間隔部件
90‧‧‧凹槽
92‧‧‧源極/汲極區
96‧‧‧接觸蝕刻終止層
99‧‧‧層間介電層
100‧‧‧製程
102、104、106、108、110、112、114、116、118、120、122、124、126、128‧‧‧操作
201‧‧‧鰭式場效電晶體裝置結構
212‧‧‧虛置閘極結構
250a‧‧‧p型裝置區
250b‧‧‧n型裝置區
A-A、B-B‧‧‧剖面
以下將配合所附圖式詳述本揭露之實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。
第1圖係根據一些實施例繪示出在基板上製造裝置結構之示例製程的流程圖。
第2圖係根據一些實施例繪示出半導體裝置結構的透視圖。
第3A-3B、4A-4B、5A-5B、6A-6B、7A-7B、8A-8B、9A-9B、10A-10B、11A-11B、12A-12B、13A-13B、14A-14B、15A-15B及16A-16B係根據一些實施例繪示出半導體裝置結構在第1圖之不同製造階段下的剖面圖。
以下的揭示內容提供許多不同的實施例或範例，以展示本揭露的不同部件。以下將揭示本說明書各部件及其排列方式之特定範例，用以簡化本揭露敘述。當然，這些特定範例並非用於限定本揭露。例如，若是本說明書以下的發明內容敘述了將形成第一部件於第二部件之上或上方，即表示其包括 了所形成之第一及第二部件是直接接觸的實施例，亦包括了尚可將附加的部件形成於上述第一及第二部件之間，則第一及第二部件為未直接接觸的實施例。此外，本揭露說明中的各式範例可能使用重複的參照符號及/或用字。這些重複符號或用字的目的在於簡化與清晰，並非用以限定各式實施例及/或所述配置之間的關係。
再者，為了方便描述圖示中一元件或部件與另一(些)元件或部件的關係，可使用空間相對用語，例如「在...之下」、「下方」、「下部」、「上方」、「上部」及諸如此類用語。除了圖示所繪示之方位外，空間相對用語亦涵蓋使用或操作中之裝置的不同方位。當裝置被轉向不同方位時(例如，旋轉90度或者其他方位)，則其中所使用的空間相對形容詞亦將依轉向後的方位來解釋。
本揭露總體上是關於半導體裝置，且特別是關於在半導體裝置中形成置換閘極。本揭露提供用於製造具有良好電漿阻抗的間隔結構的方法，以使間隔結構在置換閘極製程完成之後，可保持完整並具有期望的輪廓。在一範例中，上述間隔結構可包括具有不同薄膜特性的複數間隔層。本揭露的一些面向的實施可被使用於其他製程中、其他裝置中、及/或用於其他膜層。舉例來說，其他範例裝置可包括平面式場效電晶體(planar FET)、水平全繞式閘極場效電晶體(horizontal gate all around FETs,HGAA FET)、垂直全繞式閘極場效電晶體(vertical gate all around FETs,VGAA FET)、及其他裝置。此處描述範例方法及結構的一些變化。本領域具有通常知識者將 可容易理解在其他實施例的範圍內可做其他的修改。雖然討論的一些方法實施例以特定順序進行，各式其他方法實施例可以另一合乎邏輯的順序進行，且可包括少於或多於此處討論的步驟。
在用於形成用於電晶體的金屬閘極的置換閘極製程中，在基板之上形成虛置閘極堆疊以作為其後形成的實際閘極堆疊的預留位置(placeholder)。形成間隔結構圍繞上述虛置閘極堆疊。在形成源極/汲極部件之後，形成接觸蝕刻終止層(contact etch stop layer,CESL)及層間介電(interlayer dielectric,ILD)層鄰接至上述間隔結構，去除上述虛置閘極堆疊，留下被上述間隔結構、接觸蝕刻終止層及層間介電層圍繞的開口。接著，在藉由上述間隔結構、接觸蝕刻終止層及層間介電層所定義的開口中形成金屬閘極。
上述金屬閘極結構包括閘極介電層，例如高介電常數介電層、選擇性阻障層(barrier layer)、功函數調整層(work-function tuning layer)、及閘極金屬電極。可使用複數沉積及圖案化製程以形成上述功函數調整層，舉例來說，用以微調電晶體的臨界電壓(threshold voltage,Vt)。在一些實施例中，此功函數調整層可針對不同類型的電晶體使用不同的材料，例如p-型鰭式場效電晶體或n-型鰭式場效電晶體，以根據所需提升裝置電性表現。選擇性使用上述阻障層以在圖案化製程期間保護閘極介電層。
第1圖繪示出形成半導體裝置結構的製程100的示例性流程圖，例如第2圖中所繪示的簡化鰭式場效電晶體裝置 結構201。第2圖中未說明或描述的其他觀點可於以下圖示及描述中得到。第2圖中的結構可以例如一或多個電晶體的方式電性連接或耦合(couple)。第3A-16B圖係根據一些實施例，對應於製程100之各階段的基板的一部份的剖面示意圖。應注意的是，可使用製程100以形成任意合適結構，包括第2-16B圖中所繪示的半導體裝置結構201或其他未於此處揭露的半導體結構。
在基板70上形成第2圖中繪示的簡化鰭式場效電晶體裝置結構201。此基板70可為或包括主體(bulk)半導體基板、絕緣層上半導體(semiconductor-on-insulator,SOI)基板、或其他基板。此基板70的半導體材料可包括或為擇自矽(例如，像是矽<100>或矽<111>的結晶矽)、矽鍺(silicon germanium)、鍺(germanium)、砷化鎵(gallium arsenide)、或其他半導體材料的至少其中一者的材料。此半導體材料可為摻雜或未摻雜的，例如使用p-型或n-型摻質。在一些其中使用絕緣層上半導體作為基板70的實施例中，基板70可包括設置於絕緣層上的半導體材料，其可以是設置在半導體基板中的埋置絕緣體(buried insulator)，或其可以是玻璃或藍寶石(sapphire)基板。在此描述的實施例中，基板70為含矽材料，例如結晶矽基板。此外，基板70不限於任何特定的尺寸、形狀、或材料。基板70可以是200毫米直徑、300毫米直徑、或其他直徑，例如450毫米等的圓形(round/circular)基板。基板70亦可以是任何多邊形(polygonal)、方形(square)、矩形(rectangular)、曲形(curved)、或其他非圓形工件(workpiece)，例如根據需要的多邊形基板。
每個鰭片結構74提供形成一個或多個裝置的主動區。使用包括遮罩、光微影、及/或蝕刻製程的合適製程形成鰭片結構74。在一範例中，形成遮罩層覆蓋基板70。光微影製程包括形成光阻層(阻劑)覆蓋上述遮罩層、曝光上述光阻層成為圖案、進行曝光後烘烤製程(post-exposure bake process)、及顯影上述光阻層以圖案化此光阻層。使用合適蝕刻製程將光阻層的圖案轉移至遮罩層以形成遮罩元件。可接著使用上述遮罩元件以在蝕刻製程形成凹槽76至基板中時保護基板70的區域，留下延伸的鰭片，例如鰭片結構74。可使用反應離子蝕刻(reactive ion etch,RIE)及/或其他合適製程蝕刻上述凹槽76。可使用方法的許多其他實施例以在基板上形成鰭片結構。
在一實施例中，鰭片結構74為大約10奈米寬且高度範圍在大約10奈米至60奈米，例如約50奈米高。然而，應理解的是，鰭片結構74亦可使用其他尺寸。在一範例中，鰭片結構74包括矽材料或其他元素半導體，例如鍺，或包括碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)的化合物半導體。此鰭片結構74亦可以是包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、或GaInAsP的合金半導體，或上述之組合。此外，此鰭片結構74可以根據所需使用n-型及/或p-型摻質摻雜。
如所述，在一範例中，可藉由蝕刻掉一部分的基板70以在基板70中形成凹槽76來形成多個鰭片結構74。可接著使用經凹蝕或回蝕刻的隔離材料填充凹槽76以形成隔離結構 78。用於隔離結構78及/或鰭片結構74的其他製造技術是可行的。隔離結構78可隔離基板70的一些區域，例如鰭片結構74中的主動區。在一範例中，上述隔離結構78可以是淺溝槽隔離(shallow trench isolation,STI)結構及/或其他合適隔離結構。上述淺溝槽隔離結構可由氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃(fluoride-doped silicate glass,FSG)、低介電常數介電材料、及/或其他合適絕緣材料形成。上述淺溝槽隔離結構可包括多層膜結構，舉例來說，具有一或多個襯層。
形成虛置閘極結構212於鰭片結構74之上。在第2圖所描述的範例中，虛置閘極結構212包括閘極介電層80、閘極電極層82、及硬遮罩84。應注意的是，虛置閘極結構212可更包括封蓋層及/或其他合適膜層。可藉由合適沉積技術形成虛置閘極結構212中的各式膜層，以及藉由合適光微影及蝕刻技術以圖案化虛置閘極結構212中的各式膜層。虛置閘極結構212在鰭片結構74的兩側或三側上接合(engage)鰭片結構74。設置源極/汲極區52a及52b於相對於虛置閘極結構212的鰭片結構74的兩側區域中。舉例來說，如所標示的，在各電晶體之間可共享一些源極/汲極區，且一些未繪示為共享的其他源極/汲極區可與未繪示的相鄰電晶體共享。在一些範例中，各式源極/汲極區中的各個源極/汲極區可被連接或耦合在一起，以使鰭式場效電晶體作為兩個功能(functional)電晶體實施。舉例來說，如果相鄰(例如，而非相對)源極/汲極區52a、52b電性連接，例如藉由磊晶成長合併(coalesce)此些區域(例如，合併相鄰而非虛置閘極結構212的兩側上的源極/汲極區)，可實現兩個功能 電晶體。其他範例中的其他配置可實現其他數量的功能電晶體。
於此處描述的用語”虛置”是指犧牲結構，其將在後續階段中被去除且將被置換成其他結構，例如置換閘極製程中的高介電常數介電質及金屬閘極結構。置換閘極製程是指在整個閘極製造製程中的後期階段製造閘極結構。上述閘極介電層80可以是介電氧化層。舉例來說，可藉由化學氧化法(chemical oxidation)、熱氧化法(thermal oxidation)、原子層沉積(atomic layer deposition,ALD)、化學氣相沉積(chemical vapor deposition,CVD)、及/或其他合適方法形成上述介電氧化層。上述閘極電極層82可以是多晶矽層或其他合適膜層。舉例來說，可藉由合適沉積製程例如低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)及電漿增強化學氣相沉積(plasma-enhanced CVD,PECVD)形成此閘極電極層82。上述遮罩層84可以是合適於在基板上以期望的部件/尺寸圖案化閘極電極層82的任何材料。
在一實施例中，首先沉積虛置閘極結構212的各式膜層為毯覆層(blanket layers)。接著，藉由包括光微影及蝕刻製程的製程來圖案化此些毯覆層，去除部分毯覆層且保持隔離結構78及鰭片結構74之上的剩餘部分以形成虛置閘極結構212。
在一實施例中，半導體裝置結構201包括p型裝置區250a及n型裝置區250b。可在p型裝置區250a中形成一或多個p型裝置，例如p型鰭式場效電晶體，且可在n型裝置區250b形 成一或多個n型裝置，例如n型鰭式場效電晶體。上述半導體裝置結構201可被包括在積體電路中，例如微處理器、記憶裝置、及/其他積體電路。
第2圖更進一步繪示出用於後續圖示中的參考剖面。剖面A-A為例如沿著相對源極/汲極區52a、52b之間的鰭片結構74中的通道的平面。剖面B-B為垂直於剖面A-A的平面且橫跨鰭片結構74中的源極/汲極區52a。為了清楚起見，後續圖示將參考此些參考剖面。在後續圖示中以”A”符號結尾的圖示繪示出對應於剖面A-A在各式製程情況下的剖面圖，且在後續圖示中以”B”符號結尾的圖示繪示出對應於剖面B-B在各式製程情況下的剖面圖。在一些圖示中，其中所示的一些組件(component)或部件的附圖標記可被省略以避免模糊其他組件或部件；此係為了便於描繪此些圖示。
回頭參考第1圖中繪示的製程100，如第3A-3B圖所示，製程100在操作102處透過提供基板70開始，準備用於製造形成於基板70上的半導體裝置，例如半導體裝置201。
如第4A-4B圖所示，在操作104，進行蝕刻製程以在基板70中形成在基板70中定義鰭片結構74的凹槽76。使用遮罩72(例如，硬遮罩)以便於在基板70中形成鰭片結構74。舉例來說，設置一或多個遮罩層於半導體基板70之上，且接著圖案化上述一或多個遮罩層至遮罩72中。在一些範例中，上述一或多個遮罩層可包括或為氮化矽、氮氧化矽、碳化矽、氮碳化矽、相似材料、或上述之組合，且可藉由化學氣相沉積(chemical vapor deposition,CVD)、物理氣相沉積(physical vapor deposition,PVD)、原子層沉積(atomic layer deposition,ALD)、或其他沉積技術沉積。可使用光微影技術圖案化上述一或多個遮罩層。舉例來說，例如藉由旋轉塗佈(spin-on coating)可於上述一或多個遮罩層上形成光阻，且藉由使用適當光遮罩將光阻曝露至光中以圖案化光阻。可接著去除光阻的曝露或未曝露部分，其取決於使用的是正光阻或是負光阻。光阻的圖案可接著被轉移至一或多個遮罩層，例如藉由使用形成遮罩72的合適蝕刻製程。此蝕刻製程可包括反應離子蝕刻(reactive ion etch,RIE)、中性束蝕刻(neutral beam etch,NBE)、感應耦合電漿(inductive coupled plasma)蝕刻、相似製程、或上述之組合。此蝕刻可為非等向性(anisotropic)的。接著，在例如灰化(ashing)或濕式剝除(wet strip)製程中去除光阻。
如第5A-5B圖所示，在操作106，在各個相應的凹槽76中形成隔離結構78。上述隔離結構78可包括或為絕緣材料，例如氧化物(例如氧化矽)、氮化物(nitride)、相似材料、或上述之組合，且可藉由高密度電漿化學氣相沉積(high density plasma CVD,HDP-CVD)、流動式化學氣相沉積(flowable CVD,FCVD)(例如，於遠端控制(remote)電漿系統中沉積以化學氣相沉積為主的材料且後硬化(post curing)此材料使其轉變為例如氧化物的其他材料)、相似製程、或上述之組合以形成此絕緣材料。可使用任意容許製程形成其他絕緣材料。在所繪示的實施例中，隔離結構78包括藉由流動式化學氣相沉積製程形成的氧化矽。例如化學機械拋光(chemical mechanical polish,SMP)的平坦化製程可去除任何過量的絕緣 材料及任何殘餘的遮罩(例如，用於蝕刻凹槽76及形成鰭片結構74)以將絕緣材料的頂表面形成為大體上與鰭片結構74的頂表面共平面。可接著凹蝕此絕緣材料以形成隔離結構78。凹蝕此絕緣材料使得鰭片結構74自相鄰隔離結構78之間突出，其從而可描繪至少一部份的鰭片結構74作為半導體基板70上的主動區。可使用適用蝕刻製程凹蝕此絕緣材料，例如對上述絕緣材料具有選擇性的蝕刻製程。舉例來說，可採用使用CERTAS®蝕刻、應用材料公司(Applied Materials)的SICONI工具或稀釋氫氟酸(dilute hydrofluoric,dHF)的化學氧化物去除(chemical oxide removal)。此外，隔離結構78的頂表面可具有如圖所繪示的平坦(flat)表面、凸(convex)面、凹(concave)面(例如碟狀(dishing))、或上述之組合，其可由蝕刻製程所導致。
如第6A-6B圖所示，在操作108，在基板上形成虛置閘極結構212。虛置閘極結構212位於鰭片結構74之上且側向延伸垂直於鰭片結構74。各個虛置閘極結構212包括閘極介電層80、閘極電極層82、及硬遮罩84。在置換閘極製程中，上述閘極介電層80可以是界面介電質。可藉由依序形成相應的層，且接著圖案化此些相應的層至虛置閘極結構212中以形成上述用於虛置閘極結構212的閘極介電層80、閘極電極層82、及硬遮罩84。舉例來說，用於界面介電質的膜層可包括或為氧化矽、氮化矽、相似材料、或上述之多層膜，且可以是熱及/或化學成長於鰭片結構74上、或藉由例如電漿增強化學氣相沉積、原子層沉積、或其他沉積技術共形沉積。用於閘極電極層82的膜層可包括或為矽(例如，多晶矽)或其他藉由化學氣相沉 積、物理氣相沉積、或其他沉積技術沉積的其他材料。用於硬遮罩84的膜層可包括或為氮化矽、氮氧化矽、碳氮化矽、相似材料、或上述之組合，藉由化學氣相沉積、物理氣相沉積、原子層沉積、或其他沉積技術沉積。可接著圖案化用於硬遮罩84、閘極電極層82、及閘極介電層80的膜層，舉例來說，使用微影技術及一或多道如前述的蝕刻製程，以形成用於各個虛置閘極結構212的硬遮罩84、閘極電極層82、及閘極介電層80。
在一些實施例中，在形成虛置閘極結構212之後，可在主動區中形成輕摻雜汲極(lightly doped drain,LDD)區(未具體繪示)。舉例來說，可使用虛置閘極結構212作為遮罩以佈植摻質至主動區(例如，鰭片結構74)中。舉例來說，示例摻質可包括或為，用於p型裝置的硼(boron)及用於n型裝置的磷(phosphorus)或砷(arsenic)，但可使用其他摻質。上述輕摻雜汲極區可具有範圍在約1015cm-3至約1017cm-3的摻質濃度。
如第7A-7B圖所示，在操作110，在虛置閘極結構212的側壁上形成密封間隔層86。共形地形成密封間隔層86在基板70上。在一範例中，密封間隔層86由具有小於4的介電常數的材料形成，例如低介電常數介電材料。舉例來說，密封間隔層86可以由包含碳氧化矽(silicon oxycarbide,SiOC)材料的材料製成。在一具體範例中，密封間隔層86由無氮之碳氧化矽材料(nitrogen free silicon oxycarbide material)製成。
在一範例中，可藉由任何合適沉積製程形成密封間隔層86。在一具體範例中，可藉由原子層沉積製程形成密封間隔層86。在一範例中，用於原子層沉積製程的製程氣體可包 括具有矽(Si)及碳(C)源的含矽及碳的前驅物，以及包括氧源的含氧前驅物。前述矽(Si)及碳(C)源及含氧前驅物可在原子層沉積製程期間交替地供應。在一具體範例中，前述含矽及碳的前驅物為無氮之含矽及碳的前驅物。在一些範例中，此含矽及碳的前驅物可具有主要的Si-C-Si(矽-碳-矽)線性鍵結結構作為其特定的化學/功能結構。一般認為，矽鍵結之間鍵結的碳的數目可能影響所得薄膜層的密度，從而可透過控制矽鍵結之間形成的碳的數目來調整或改變薄膜介電常數。一般認為，碳原子的數目越多，則所得到的薄膜層的介電常數就越低。
此外，主要由Si-C-Si線性鍵結結構形成的薄膜層也被認為較主要由Si-O-Si、Si-H、或其他含矽鍵結所形成的薄膜層具有更低的密度。因此，藉由選擇具有Si-C-Si(矽-碳-矽)線性鍵結結構的前驅物作為其特定化學/功能結構，可獲得具有相對低的介電常數的密封間隔層86，例如，小於4，例如約3.0-3.5。含矽及碳的前驅物的合適範例包括SiCl3-CH2-SiCl3、SiCl2-(CH2)2-SiCl2、SiCl-(CH2)3-SiCl、SiCl2=C=SiCl2、及相似材料。應注意的是，附於鍵結結構末端的氯(chlorine)元素可被認為是在化學反應期間將經歷熱裂解(pyrolysis)程序的離去基(leaving group)，從前驅物中主要的Si-C-Si鍵結結構中留下以觸發反應。因此，根據需要也可使用包括其他元素例如Br、F、或相似元素的其他合適的離去基團。含氧前驅物的合適範例包括水蒸氣(H2O)、O2、O3、CO、CO2、及相似材料。
在操作110的密封間隔層原子層沉積製程期間，可交替地提供用於反應的包括矽及碳源前驅物及含氧前驅物的 不同氣體。原子層沉積製程的週期包括交替流送(flow)(或脈衝(pulse))及清除(purge)操作，其中各前驅物在週期期間流送(或脈衝)並且隨後被清除至少一次。舉例來說，流送前述矽及碳源前驅物至轉移基板(例如，在其上形成裝置結構，例如，如第7A-7B圖所示)的原子層沉積工具腔中，且接著，自原子層沉積工具腔中清除前述矽及碳源前驅物。在一些範例中，前述矽及碳源前驅物可在被清除之前與基板上可用的反應位置反應。在一些範例中，上述反應可能使反應位置飽和，或者矽及碳源前驅物可能沒有與基板上一些可用的反應位置反應。在清除矽及碳源前驅物之後，接著流送氧源前驅物至原子層沉積工具腔中，且接著，自原子層沉積工具腔清除前述氧源前驅物。同樣地，在一些範例中，前述氧源前驅物可在被清除之前與基板上可用的反應位置反應。在一些範例中，上述反應可能使反應位置飽和，或者氧源前驅物可能沒有與基板上一些可用的反應位置反應。
交替的矽及碳源前驅物以及氧源前驅物之間脈衝及清除的週期可被進行任意次數直到形成預期的密封間隔層86的厚度。總沉積時間範圍可在約300秒至約900秒，例如約600秒。交替的矽及碳源前驅物以及氧源前驅物之間的總週期範圍可在約15個週期至20個週期，例如約18個週期。
在一範例中，上述密封間隔層86可具有約3.2至約3.7的介電常數，例如約3.5。
應注意的是，此處描述的密封間隔層86可形成為犧牲層及/或表面保護層以提供界面保護層，此界面保護層可 防止隨後形成於其上的薄膜堆疊在後續蝕刻/圖案化製程中受到傷害。因此，可控制密封間隔層86的厚度在足以提供界面保護層的範圍內。在一範例中，密封間隔層86可具有範圍在10埃(Å)至50埃的厚度，例如20埃至35埃。
如第8A-8B圖所示，在操作112，進行電漿處理製程於密封間隔層86上。如第8A-8B圖所標示的，此電漿處理製程藉由電漿83處理密封間隔層86以改變基板表面性質，形成經處理密封間隔層87。上述電漿表面處理製程可有效地併入某些元素以與密封間隔層86中的不飽和鍵反應，從而改善鍵結能並使薄膜結構緻密化以形成具有相對高的薄膜密度的經處理密封間隔層87。來自經處理密封間隔層87的較高薄膜密度可在虛置閘極去除製程期間防止界面保護層及隨後將形成於其上的薄膜堆疊受到電漿傷害。此外，亦可進行上述處理製程以修飾密封間隔層86之表面的表面形貌(morphology)及/或表面粗糙度(surface roughness)以改善經處理密封間隔層87的附著力(adhesion)及可靠性(robustness)。在一實施例中，上述表面處理製程可創造出粗糙表面，其表面粗糙度範圍在約6埃至約60埃。
在一實施例中，可藉由供應包括含氫氣體或惰性氣體之製程氣體至電漿製程腔中以進行表面處理製程。前述含氫氣體可擇自由H2、H2O、H2O2、上述之組合及相似氣體所組成的群組。在一示例性實施例中，用於進行基板處理製程的含氫氣體包括H2氣體。此外，在一特定實施例中，上述製程氣體可包括惰性氣體以進行表面處理製程。前述惰性氣體的範例包 括Ar、He及相似氣體。應注意的是，藉由使用含氫氣體以進行表面處理製程的製程參數可配置為與藉由使用惰性氣體以進行表面處理製程的製程參數相似。
在一範例中，上述電漿處理製程包括在電漿製程腔中具有微波產生器產生的微波電漿。用於操作112的電漿處理製程的微波產生器可在約0.3GHz至約300GHz的頻率範圍下產生範圍在約10瓦(Watt)至約3000瓦的功率。可控制電漿製程時間範圍在約100秒至約1000秒，例如約600秒。
如先前所討論的，此處使用密封間隔層86作為界面保護層以及犧牲層，以保護隨後將在其上形成的薄膜結構免於在後續蝕刻/圖案化製程中受到傷害。在密封間隔層86上進行的電漿處理製程將密封間隔層86轉換成經處理密封間隔層87。經處理密封間隔層87具有緻密且強化的薄膜結構，其為裝置結構提供穩固的電漿阻抗及強大的界面保護。透過這樣的處理，其後在其上形成的膜層可在蝕刻/圖案化製程中受到良好的電漿保護。
在電漿處理製程之後，由於經處理密封間隔層87具有較高的薄膜密度，其可具有較密封間隔層86稍大的介電常數。在一範例中，經處理密封間隔層87具有範圍在3.5至3.9的介電常數，例如約3.7。由於來自電漿處理製程的緻密化，經處理密封間隔層87亦具有較密封間隔層86大的薄膜密度。相對地，經處理密封間隔層87的厚度範圍可以縮小至約10%至20%的密封間隔層86的厚度。在一範例中，經處理密封間隔層87具有範圍在約15埃至約28埃的厚度。在上述處理之後，成為經處 理密封間隔層87的密封間隔層86的薄膜密度從1.7變為2.5。
如第9A-9B圖所示，在操作114，接著在經處理密封間隔層87上形成主體間隔層88。如第7A-7B圖所示，此主體間隔層88與沒有在其上進行電漿處理的密封間隔層86大體上為相同的材料。此主體間隔層88作為用於半導體裝置的間隔部件89的主要結構作用。因此，足夠厚度的主體間隔層88被實施以使半導體裝置的操作變的可行。因此，主體間隔層88具有較經處理密封間隔層87大的厚度。在一範例中，主體間隔層88具有範圍在約50埃至約200埃的厚度。
如先前所討論的，主體間隔層88由具有小於4的介電常數的材料形成，例如低介電常數介電材料。舉例來說，如先前所討論的，與形成密封間隔層86使用相同的材料，主體間隔層88可以由包含碳氧化矽(silicon oxycarbide,SiOC)材料的材料製成。在一範例中，主體間隔層88由無氮之碳氧化矽材料(nitrogen free silicon oxycarbide material)製成。
同樣地，可藉由任何合適沉積製程形成主體間隔層88，例如原子層沉積製程。在一具體範例中，可藉由使用具有矽(Si)及碳(C)源的含矽及碳的前驅物，以及包括氧源的含氧前驅物的原子層沉積製程形成主體間隔層88。在一具體範例中，前述含矽及碳的前驅物為無氮之含矽及碳的前驅物。此含矽及碳的前驅物可具有主要的Si-C-Si(矽-碳-矽)線性鍵結結構作為其特定的化學/功能結構。含矽及碳的前驅物的合適範例包括SiCl3-CH2-SiCl3、SiCl2-(CH2)2-SiCl2、SiCl-(CH2)3-SiCl、SiCl2=C=SiCl2、及相似材料。含氧前驅物的合適範例包括水 蒸氣(H2O)、O2、O3、CO、CO2、及相似材料。
在一範例中，上述主體間隔層88可具有約3.2至約3.7的介電常數，例如約3.5。上述主體間隔層88的薄膜密度可在約1.5至約2.0，例如約1.7。
如先前所討論的，由於主體間隔層88與形成密封間隔層86使用相同的材料形成，所以可以理解，由於經處理密封間隔層87具有較高的薄膜密度，故經處理密封間隔層87可具有較主體間隔層88稍大的介電常數。由於來自電漿處理製程的緻密化，經處理密封間隔層87亦具有較主體間隔層88大的薄膜密度。
如第10A-10B圖所示，在操作116，接著圖案化或非等向性蝕刻經處理密封間隔層87及主體間隔層88以形成期望輪廓，從而形成間隔部件89。此間隔部件89包括經處理密封間隔層87及主體間隔層88。應注意的是，經處理密封間隔層87隨後可被犧牲及去除，僅留下部分的主體間隔層88作為基板上的間隔部件89。此蝕刻製程可包括反應離子蝕刻、中性束蝕刻、或其他蝕刻製程。在一實施例中，間隔部件86包括介電材料，例如氮化矽或氮氧化矽。
如第11A-11B圖所示，在操作118，在基板70上形成用於源極/汲極區的凹槽90。如所繪示的，在虛置閘極結構212的兩側上的鰭片結構74中形成凹槽90。可藉由蝕刻製程進行凹蝕。上述蝕刻製程可為等向性(isotropic)或非等向性(anisotropic)，或者，可以是對於半導體基板70的一個或多個晶面(crystalline plane)為選擇性的。因此，基於所實施的蝕刻 製程，凹槽90可具有各種剖面輪廓。此蝕刻製程可為乾蝕刻，例如反應離子蝕刻、中性束蝕刻、或相似製程，或為例如使用四甲基氫氧化銨(tetramethyalammonium hydroxide,TMAH)、氫氧化銨(ammonium hydroxide,NH4OH)或其他蝕刻劑的濕蝕刻。
應注意的是，上述蝕刻製程以對間隔部件89傷害最小的方式選擇性蝕刻基板70上的鰭片結構74。因此，如第11A圖所示，當在基板70中形成凹槽90，如第11B圖所示，至少一部分的鰭片結構74自隔離結構78之間被去除，且如第11B圖所示的間隔部件89可以最小的高度/寬度損失的方式保持在基板70上。
如第12A-12B圖所示，在操作120，在基板70上形成凹槽90之後，可進行磊晶沉積製程以成長源極/汲極區92。此磊晶源極/汲極區92可包括或為矽鍺(SixGe1-x，其中X可約在0至1)、碳化矽、磷化矽、純的或大體上純的鍺、三五族化合物半導體、二六族化合物半導體、或相似材料。舉例來說，用於形成三五族化合物半導體的材料包括InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP、及相似材料。可藉由磊晶成長一材料於凹槽90中以形成位於凹槽90中的磊晶源極/汲極區92，例如藉由金屬有機化學氣相沉積(metal-organic CVD,MOCVD)、分子束磊晶(molecular beam epitaxy,MBE)、液相磊晶(liquid phase epitaxy,LPE)、氣相磊晶(vapor phase epitaxy,VPE)、選擇性磊晶成長(selective epitaxial growth,SEG)、相似製程、或上述之組合。如第12A及12B圖所繪示，由於隔離結構78以及間隔部件89的阻擋 (block)，磊晶源極/汲極區92首先在凹槽90中垂直成長，在此期間磊晶源極/汲極區92不會水平成長。在完全填充凹槽90並且從間隔部件89垂直向外之後，磊晶源極/汲極區92可垂直及水平成長以形成刻面(facet)，其可對應於半導體基板70的晶面。在一些範例中，用於p型裝置及n型裝置之磊晶源極/汲極區的材料是不同的。在凹蝕或磊晶成長期間，適當的遮罩可允許在不同的裝置中使用不同的材料。
本領域具有通常知識者將可容易理解關於第11A-11B圖至第12A-12B圖之凹蝕及磊晶成長可被省略，且可藉由使用虛置閘極結構212及間隔部件89作為遮罩以佈植摻質至鰭片結構74中來形成源極/汲極區。在一些實施磊晶源極/汲極區92的範例中，磊晶源極/汲極區92亦可被摻雜，例如在磊晶成長的過程中原位摻雜及/或在磊晶成長之後藉由佈植摻質至磊晶源極/汲極區92中。舉例來說，示例摻質可包括或為，用於p型裝置的硼(boron)及用於n型裝置的磷(phosphorus)或砷(arsenic)，但可使用其他摻質。磊晶源極/汲極區92(或其他源極/汲極區)可具有在約1019cm-3至約1021cm-3的摻質濃度。因此，如果合適的話，可藉由摻雜(例如，如果合適的話，在磊晶成長的過程中藉由佈植及/或原位摻雜)及/或磊晶成長描繪出(delineate)源極/汲極區，其可進一步在描繪的源極/汲極區中描繪出主動區。
如第13A-13B圖所示，在操作122，形成接觸蝕刻終止層(contact etch stop layer,CESL)96覆蓋虛置閘極結構212。接觸蝕刻終止層96可提供一種機制(mechanism)以在形成 例如接觸件(contact)或通孔(via)時停止蝕刻製程。蝕刻終止層96可由與鄰近的膜層或部件中具有不同蝕刻選擇性的介電材料形成。在磊晶源極/汲極區92的表面、間隔部件89的側壁及頂表面、硬遮罩84的頂表面、以及隔離結構78的頂表面上形成蝕刻終止層96。此蝕刻終止層96可包括或可為含氮材料、含矽材料、及/或含碳材料。此外，蝕刻終止層96可包括或為氮化矽、碳氮化矽、氮化碳、氮氧化矽、碳氧化矽、相似材料、或上述之組合。可藉由沉積製程沉積蝕刻終止層96，例如電漿增強原子層沉積(Plasma Enhanced ALD,PEALD)、化學氣相沉積、或其他沉積技術。
如第14A-14B圖所示，在操作124，在蝕刻終止層96之上形成層間介電層99。上述層間介電層99可包括例如四乙氧基矽烷(tetraethylorthosilicate,TEOS)氧化物、未摻雜的矽酸鹽玻璃(un-doped silicate glass,USG)、摻雜矽的氧化物，例如硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、熔融矽石玻璃(fused silica glass,FSG)、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、摻雜硼的矽酸鹽玻璃(boron doped glass,BSG)、SiOxCy、旋轉塗佈玻璃(Spin-On-Glass)、旋轉塗佈聚合物(Spin-On-Polymers)、碳矽材料、上述之化合物(compound)、上述之複合物(composite)、及/或其他合適介電材料。可藉由旋轉塗佈、化學氣相沉積、流動式化學氣相沉積、電漿增強化學氣相沉積、物理氣相沉積、或其他沉積技術沉積層間介電層99。在一實施例中，藉由流動式化學氣相沉積(flowable CVD,FCVD)製程形成層間介電層99以在相鄰虛置閘極結構212之間 填充。應注意的是，在熱退火製程之後，可藉由例如化學機械拋光製程將上述層間介電層99平坦化以根據所需提供平坦表面。
如第15A-15B圖所示，在操作126，接下來，自基板70去除虛置閘極結構212以如第15A-15B圖所描繪的在層間介電層99中定義出開口50，其稍後可允許形成例如金屬閘極結構的置換閘極結構56於其中以繼續製造如第16A-16B圖所示的半導體裝置結構201。回頭參考第15A-15B圖，在虛置閘極結構212的去除製程期間，進行一系列的電漿蝕刻/圖案化製程。在一些範例中，可進行灰化(ashing)製程及/或去殘渣(de-scum)製程以去除來自基板70的蝕刻殘留物(residual)。因此，基板70上的結構，包括間隔部件89、接觸蝕刻終止層96及層間介電層99，會在電漿製程中經歷電漿攻擊，這可能對薄膜結構造成非預期的傷害，尤其是對於與虛置閘極結構212直接接觸的間隔部件89。因此，藉由使用包括經處理密封間隔層87以及主體間隔層88的間隔部件89，例如複數間隔層結構，此經處理密封間隔層87可作為在虛置閘極結構去除製程期間直接曝露於電漿中的界面保護層，從而防止了主體間隔層88暴露至電漿。此外，由於經處理密封間隔層87具有相對緻密的薄膜結構且相對具有電漿阻抗，此經處理密封間隔層87能夠保持在侵蝕性的電漿暴露以及甚至去殘渣氧氣暴露中。在去殘渣製程期間暴露於氧氣中通常被視為是可能非預期的影響間隔部件89的介電常數的顯著因素，因為由其所產生的氧氣元素通常增加間隔部件89的介電常數數值。因此，經處理密封間隔層87的逐漸消耗使 得主體間隔層88在侵蝕性電漿暴露期間及甚至在去殘渣氧氣暴露期間遭受攻擊。因此，在虛置閘極結構去除製程期間的侵蝕性的電漿曝露及去殘渣氧氣曝露期間，經處理密封間隔層87的厚度被控制並確定在沒有早期耗盡(其可能將附近的主體間隔層89非預期的暴露至電漿)的情況下，允許逐漸消耗的合適範圍。因此，在第15A圖所描繪的位置中，經處理密封間隔層87與虛置閘極結構212直接接觸，在去除虛置閘極結構212之後，經處理密封間隔層87被消耗並大體上自基板70上去除，雖然，在其他範例中，在去除虛置閘極結構212之後，至少一部分的經處理密封間隔層87可沿著主體間隔層89保持在先前經處理密封間隔層87與虛置閘極結構212直接接觸的位置。相對地，在第15B圖所描繪的位置中，其中間隔部件89，尤其是經處理密封間隔層87，在沒有電將暴露的情況下被覆蓋在接觸蝕刻終止96及層間介電層99底下，包括經處理密封間隔層87及主體間隔層88兩者的間隔部件89可保持在靠著源極/汲極區92的側壁內襯的基板70上。
在操作128，在去除虛置閘極結構212之後，可接著在開口50中填充及形成置換閘極結構56。如第16A-16B圖所示，上述置換閘極結構56可為金屬閘極結構，其包括界面層(未繪示)、高介電常數介電層53、功函數調整層54及金屬電極結構55形成於其中以形成金屬閘極結構。
儘管並無意圖進行限制，本揭露的一或多個實施例對於半導體裝置以及其形成方法提供許多益處。舉例來說，本揭露實施例提供用於在形成接觸蝕刻終止層之前形成具有 複數薄膜層的間隔部件的方法。上述間隔部件可包括密封間隔層及主體間隔層。電漿處理此密封間隔層以形成經處理密封間隔層，此經處理密封間隔層具有電漿阻抗，以便在後續的虛置閘極電極去除製程中經歷電漿暴露時避免早期消耗或耗盡。因此，在自基板去除虛置閘極電極之後，在一些位置處，上述經處理密封間隔層可沿著主體間隔層保持在基板上，而在一些位置則只留下主體間隔層。
在一實施例中，一種半導體裝置包括主動區，位於基板上，上述主動區包括源極/汲極區；閘極結構，位於上述主動區之上，上述源極/汲極區靠近上述閘極結構；間隔部件，沿著上述閘極結構之側壁具有第一部分且沿著上述源極/汲極區具有第二部分，其中上述間隔部件的上述第一部分沿著上述閘極結構之側壁包括主體間隔層，其中上述間隔部件的上述第二部分包括上述主體間隔層及經處理的密封間隔層，上述經處理的密封間隔層係沿著上述源極/汲極區設置且位於上述主體間隔層及上述源極/汲極區之間、以及接觸蝕刻終止層，位於上述間隔部件上。在一實施例中，層間介電層位於上述接觸蝕刻終止層上。在一實施例中，上述主體間隔層具有小於4的介電常數。在一實施例中，上述主體間隔層為無氮之碳氧化矽材料(nitrogen free silicon oxycarbide material)。在一實施例中，上述經處理的密封間隔層具有較上述主體間隔層大的介電常數。在一實施例中，上述經處理的密封間隔層具有較上述主體間隔層大的薄膜密度。在一實施例中，上述閘極結構包括設置在高介電常數膜層上的金屬閘極電極。在一實施例中，上述 接觸蝕刻終止層為含氮化矽之材料。在一實施例中，上述主體間隔層的厚度大於上述經處理的密封間隔層。
在另外的實施例中，一種半導體裝置的形成方法包括藉由使用第一製程氣體的第一原子層沉積製程在基板上形成密封間隔層、藉由第二製程氣體電漿處理上述密封間隔層以形成經處理的密封間隔層，其中上述第一製程氣體與上述第二製程氣體不同，藉由使用上述第一製程氣體的第二原子層沉積製程在上述密封間隔層上形成主體間隔層、以及沿著閘極結構的側壁將上述經處理的密封間隔層及上述主體間隔層圖案化至閘極間隔部件中。在一實施例中，電漿處理上述密封間隔層更包括透過施加微波功率至放置上述基板的電漿製程腔以在上述第二製程氣體中形成電漿。在一實施例中，上述第一製程氣體包括含矽及碳的前驅物及含氧前驅物。在一實施例中，上述含矽及碳的前驅物為無氮之含矽及碳的前驅物。在一實施例中，上述含氧前驅物包括水蒸氣。在一實施例中，上述含矽及碳的前驅物具有線性Si-C-Si鍵結結構。在一實施例中，上述主體間隔層的厚度大於該上述處理的密封間隔層。在一實施例中，上述第二製程氣體包括含氫氣體、惰性氣體、或上述之組合。
在另外的實施例中，一種半導體裝置的形成方法包括形成間隔部件，上述間隔部件沿著位於基板上的閘極結構的側壁包括經處理的密封間隔層及主體間隔層，其中上述閘極結構係形成在主動區之上，上述主動區在上述基板上包括源極/汲極區，上述源極/汲極區接近上述閘極結構，以及自沿著上 述閘極結構的側壁去除上述閘極結構及至少一部份的上述經處理的密封間隔層，其中去除上述閘極結構而沿著上述源極/汲極區保持經處理的密封間隔層不被去除。在一實施例中，自沿著上述閘極結構的側壁去除上述閘極結構及上述至少一部份的上述經處理的密封間隔層更包括沿著上述閘極結構的側壁及沿著上述源極/汲極區保持主體間隔層不被去除。在一實施例中，上述閘極結構為虛置閘極結構。
以上概略說明了本揭露數個實施例的特徵，使所屬技術領域內具有通常知識者對於本揭露可更為容易理解。任何所屬技術領域內具有通常知識者應瞭解到本說明書可輕易作為其他結構或製程的變更或設計基礎，以進行相同於本揭露實施例的目的及/或獲得相同的優點。任何所屬技術領域內具有通常知識者亦可理解與上述等同的結構或製程並未脫離本揭露之精神及保護範圍內，且可在不脫離本揭露之精神及範圍內，當可作更動、替代與潤飾。

Claims (20)

  1. 一種半導體裝置，包括：一主動區，位於一基板上，該主動區包括一源極/汲極區；一閘極結構，位於該主動區之上，該源極/汲極區靠近該閘極結構；一間隔部件，沿著該閘極結構之側壁具有一第一部分且沿著該源極/汲極區具有一第二部分，其中該間隔部件的該第一部分沿著該閘極結構之側壁包括一主體間隔層，其中該間隔部件的該第二部分包括該主體間隔層及一經處理的密封間隔層，該經處理的密封間隔層係沿著該源極/汲極區設置且位於該主體間隔層及該源極/汲極區之間；以及一接觸蝕刻終止層，位於該間隔部件上。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括：一層間介電層，位於該接觸蝕刻終止層上。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該主體間隔層具有小於4的介電常數。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該主體間隔層為無氮之碳氧化矽材料(nitrogen free silicon oxycarbide material)。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該經處理的密封間隔層具有較該主體間隔層大的介電常數。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該經處理的密封間隔層具有較該主體間隔層大的薄膜密度。
  7. 如申請專利範圍第1項所述之半導體裝置，其中該閘極結構 包括一金屬閘極電極，該金屬閘極電極係設置在一高介電常數膜層上。
  8. 如申請專利範圍第1項所述之半導體裝置，其中該接觸蝕刻終止層為含氮化矽之材料。
  9. 如申請專利範圍第1項所述之半導體裝置，其中該主體間隔層的厚度大於該經處理的密封間隔層。
  10. 一種半導體裝置的形成方法，包括：藉由使用一第一製程氣體的一第一原子層沉積製程在一基板上形成一密封間隔層；藉由一第二製程氣體電漿處理該密封間隔層以形成一經處理的密封間隔層，其中該第一製程氣體與該第二製程氣體不同；藉由使用該第一製程氣體的一第二原子層沉積製程在該密封間隔層上形成一主體間隔層；以及沿著一閘極結構的側壁將該經處理的密封間隔層及該主體間隔層圖案化至一閘極間隔部件中。
  11. 如申請專利範圍第8項所述之半導體裝置的形成方法，其中該電漿處理該密封間隔層更包括：透過施加微波功率至放置該基板的一電漿製程腔以在該第二製程氣體中形成電漿。
  12. 如申請專利範圍第10項所述之半導體裝置的形成方法，其中該第一製程氣體包括一含矽及碳的前驅物及一含氧前驅物。
  13. 如申請專利範圍第12項所述之半導體裝置的形成方法，其 中該含矽及碳的前驅物為無氮之含矽及碳的前驅物。
  14. 如申請專利範圍第12項所述之半導體裝置的形成方法，其中該含氧前驅物包括水蒸氣。
  15. 如申請專利範圍第12項所述之半導體裝置的形成方法，其中該含矽及碳的前驅物具有一線性Si-C-Si鍵結結構。
  16. 如申請專利範圍第10項所述之半導體裝置的形成方法，其中該主體間隔層的厚度大於該經處理的密封間隔層。
  17. 如申請專利範圍第10項所述之半導體裝置的形成方法，其中該第二製程氣體包括含氫氣體、惰性氣體、或上述之組合。
  18. 一種半導體裝置的形成方法，包括：形成一間隔部件，該間隔部件沿著位於一基板上的一閘極結構的側壁包括一經處理的密封間隔層及一主體間隔層，其中該閘極結構係形成在一主動區之上，該主動區在該基板上包括一源極/汲極區，該源極/汲極區接近該閘極結構；以及自沿著該閘極結構的側壁去除該閘極結構及至少一部份的該經處理的密封間隔層，其中去除該閘極結構而沿著該源極/汲極區保持經處理的密封間隔層不被去除。
  19. 如申請專利範圍第16項所述之半導體裝置的形成方法，其中自沿著該閘極結構的側壁去除該閘極結構及該至少一部份的該經處理的密封間隔層更包括：沿著該閘極結構的側壁及沿著該源極/汲極區保持主體間隔層不被去除。
  20. 如申請專利範圍第18項所述之半導體裝置的形成方法，其中該閘極結構為一虛置閘極結構。
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