CN109585368B - 半导体封装结构、半导体封装结构的形成方法以及半导体组装结构的形成方法 - Google Patents

半导体封装结构、半导体封装结构的形成方法以及半导体组装结构的形成方法 Download PDF

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CN109585368B
CN109585368B CN201810199539.2A CN201810199539A CN109585368B CN 109585368 B CN109585368 B CN 109585368B CN 201810199539 A CN201810199539 A CN 201810199539A CN 109585368 B CN109585368 B CN 109585368B
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package structure
stress buffering
component
stress
structure component
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CN109585368A (zh
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邹贤儒
吴志伟
王卜
施应庆
卢思维
林俊成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例涉及半导体封装结构、半导体封装结构的形成方法以及半导体组装结构的形成方法。一种半导体封装结构包含第一封装结构组件，所述第一封装结构组件包含第一侧、与所述第一侧相对的第二侧及位于所述第一侧上方的多个凹陷拐角。所述半导体封装结构包含置于所述凹陷拐角处的多个第一应力缓冲结构，且各所述第一应力缓冲结构具有弯曲表面。所述半导体封装结构包含连接到所述第一封装结构组件的第二封装结构组件及放置于之间的多个连接件。所述半导体封装结构包含位于所述第一封装结构组件与所述第二封装结构组件之间的底胶材料，且所述第一应力缓冲结构的所述弯曲表面的至少一部分与所述底胶材料接触且嵌入于所述底胶材料中。

Description

半导体封装结构、半导体封装结构的形成方法以及半导体组 装结构的形成方法
技术领域
本揭露涉及半导体封装结构、半导体封装结构的形成方法以及半导体组装结构的形成方法。
背景技术
贯穿集成电路(IC)开发的显著趋势是IC组件的大小减小。此些集成改进本质上是二维(2D)的，其中IC集成于半导体晶片的表面上。尽管光刻技术中的明显改进已实现2D IC形成中的更大成果，但存在对可在二维中达成的密度的物理限制。并且，当将更多装放置到一个芯片中时，需要更复杂设计及更多成本。
在对进一步增加的电路密度的尝试中，已开发三维(3D)IC。举例来说，可将两个裸片接合在一起；且在每一裸片之间构造电连接。然后，通过使用线接合及/或导电垫将经堆迭裸片接合到载体衬底。在另一实例中，开发一种衬底上覆芯片上覆芯片(chip on chip-on-substrate，Co(CoS))或衬底上覆晶片上覆芯片(chip-on wafer on substrate，CoWoS)技术。
发明内容
根据本发明的一实施例，一种用于形成半导体组装结构的方法包括：提供衬底，所述衬底包括多个切割道区域；在所述切割道区域中形成多个凹槽，其中使所述凹槽交叉以形成多个交叉区域；将多个第一应力缓冲结构放置于所述交叉区域中，其中所述第一应力缓冲结构中的一个的直径大于所述凹槽的宽度；及在放置所述第一应力缓冲结构之后沿着所述凹槽进行切割。
根据本发明的一实施例，一种用于形成半导体封装结构的方法包括：提供第一封装结构组件，所述第一封装结构组件包括第一侧及与所述第一侧相对的第二侧，其中所述第一封装结构组件包括位于所述第一侧上的多个凹陷拐角及放置于所述凹陷拐角处的多个第一应力缓冲结构；在所述第一侧面对第二封装结构组件的情况下将所述第一封装结构组件接合到所述第二封装结构组件；及在所述第一封装结构组件与所述第二封装结构组件之间形成底胶材料，其中所述第一应力缓冲结构的至少一部分与所述底胶材料接触且嵌入于所述底胶材料中。
根据本发明的一实施例，一种半导体封装结构包括：第一封装结构组件，其包括第一侧、与所述第一侧相对的第二侧及位于所述第一侧处的多个凹陷拐角；多个第一应力缓冲结构，其放置于所述凹陷拐角处，其中所述第一应力缓冲结构中的每一个具有弯曲表面；第二封装结构组件，其连接到所述第一封装结构组件的所述第一侧；多个连接件，其放置于所述第一封装结构组件与所述第二封装结构组件之间，且所述连接件电耦合所述第一封装结构组件与所述第二封装结构组件；及底胶材料，其位于所述第一封装结构组件与所述第二封装结构组件之间，其中所述第一应力缓冲结构的所述弯曲表面的至少一部分与所述底胶材料接触且嵌入于所述底胶材料中。
附图说明
当与附图一起阅读时，从以下详细说明最优选地理解本揭露的方面。应注意，根据工业中的标准实践，各种构件未按比例绘制。实际上，为论述清晰起见，可任意地增加或减小各种构件的尺寸。
图1展示表示根据本揭露的方面的用于形成半导体组装结构的方法的流程图。
图2展示表示根据本揭露的方面的用于形成半导体封装结构的方法的流程图。
图3A到7C图解说明一或多项实施例中的根据本揭露的方面构造的各个制造阶段处的半导体组装结构。
图8到9图解说明一或多项实施例中的根据本揭露的方面构造的各个制造阶段处的半导体封装结构。
图10到12图解说明一或多项实施例中的根据本揭露的方面构造的各个制造阶段处的半导体封装结构。
具体实施方式
以下揭露内容提供用于实施所提供标的物的不同构件的许多不同实施例或实例。下文阐述组件及布置的特定实例以简化本揭露。当然，此些仅为实例且不打算为限制性的。举例来说，以下说明中第一构件形成于第二构件上方或上可包含其中第一及第二构件形成为直接接触的实施例，且还可包含其中额外构件可形成于第一与第二构件之间使得第一与第二构件可不直接接触的实施例。另外，本揭露可在各种实例中重复元件符号及/或字母。此重复是出于简化及清晰的目的且自身不规定所论述的各种实施例及/或配置之间的关系。
此外，本文中为了便于说明可使用空间相对术语(例如“下面”、“下方”、“下部”、“上面”、“上部”、“上”及例如此类)来阐述一个元件或构件与另一元件或构件的关系，如各图中所图解说明。除图中所绘示的定向外，所述空间相对术语还打算涵盖装置在使用或操作时的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相对阐述语可同样相应地进行解释。
如本文中所使用，例如“第一”、“第二”及“第三”等术语阐述各种元件、组件、区域、层及/或区段，此些元件、组件、区域、层及/或区段不应受此些术语限制。此些术语可仅用于区分一个元件、组件、区域、层或区段与另一元件、组件、区域、层或区段。例如“第一”、“第二”及“第三”等术语在本文中使用时不暗示顺序或次序，除非内容脉络清楚地指示。
如本文中所使用，术语“大约”、“大体上”、“大体”及“约”用于阐述且考虑到小的变化。当联合事件或情景使用时，所述术语可指其中事件或情景精确地发生的例项，以及其中事件或情景在某一紧密近似程度上发生的例项。举例来说，当联合数值使用时，所述术语可指小于或等于那个数值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或者小于或等于±0.05％)的变化范围。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或者小于或等于±0.05％)，那么所述值可被视为“大体上”相同或相等。举例来说，“大体上”平行可指相对于0°小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或者小于或等于±0.05°)的角度变化范围。举例来说，“大体上”垂直可指相对于90°小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或者小于或等于±0.05°)的角度变化范围。
还可包含其它构件及工艺。举例来说，可包含测试结构以帮助对3D封装或3DIC装置进行验证测试。举例来说，测试结构可包含形成于重布层中或衬底上的允许对3D封装或3DIC进行测试的测试垫、探针及/或探测卡的使用及例如此类。可对中间结构以及最终结构执行验证测试。另外，本文中所揭露的结构及方法可联合并入有已知良好裸片的中间验证的测试方法来使用以增加良率且降低成本。
对于高阶电子电路的当前共同需要是使用集成于单个封装组件中的多个集成电路装置(“裸片”)。如此，开发3D封装结构的配置作为(举例来说)CoCoS或CoWoS技术。通过使用导电凸块(例如微凸块)而将具有不同功能的集成电路裸片安装到晶片。执行热回焊步骤以通过使导电凸块熔化及回焊而完成裸片与晶片之间的机械及电连接。另外，集成电路裸片通过贯穿衬底通路在晶片的相对侧处与导电凸块耦合。晶片的相对侧处的导电凸块大于IC裸片与晶片之间的导电凸块。通常，那些导电凸块称为“球栅阵列”或受控塌陷芯片连接(C4)凸块。在将IC裸片安装到晶片且制备C4凸块之后，对晶片执行单粒化操作以形成与IC裸片堆迭在一起的若干个中介层。在单粒化操作期间，将中介层切粒为具有边缘及拐角的矩形形状。稍后，通过使用C4凸块将中介层安装于电路板上。IC裸片因此能够通过衬底封装结构上覆晶片上覆芯片而接收及传输来从外部装置的讯号。
然而，由于存在中介层与电路板之间的热不匹配，因此发现中介层可遭受由于热碰撞系数(CTE)不匹配及翘曲不匹配而由物理应力导致的裂缝。进一步观察到，其中接触底胶材料的中介层充当裂缝起始点的拐角及/或边缘。有时，紧密毗邻于拐角/边缘的底胶材料还遭受应力，因此导致底胶从裂缝起始点的脱层。
本揭露提供一种半导体封装结构、一种用于形成半导体封装结构的方法及一种用于形成半导体组装结构的方法以在热循环及/或可靠性加压期间保护半导体封装结构免于裂缝问题。
图1是表示根据本揭露的方面的用于形成半导体组装结构10的方法的流程图。用于形成半导体组装结构10的方法包含操作102：提供包含多个切割道区域的衬底。用于形成半导体组装结构10的方法进一步包含操作104：在切割道区域中形成多个凹槽。使所述凹槽交叉以形成多个交叉区域。用于形成半导体组装结构10的方法进一步包含操作106：将多个第一应力缓冲结构放置于交叉区域中。第一应力缓冲结构中的一个的直径大于凹槽的宽度。用于形成半导体组装结构10的方法进一步包含操作108：在放置第一应力缓冲结构之后沿着凹槽进行切割。将根据一或多项实施例进一步阐述用于形成半导体组装结构10的方法。应注意，可在各项方面的范围内重新安排或以其它方式修改用于形成半导体组装结构10的方法的操作。应进一步注意，可在方法10之前、期间及之后提供额外工艺，且本文中可仅简要地阐述某些其它工艺。因此，其它实施方案在本文中所阐述的各项方面的范围内是可能的。
图2是表示根据本揭露的方面的用于形成半导体封装结构11的方法的流程图。在本揭露的某些实施例中，用于形成半导体封装结构11的方法可在用于形成半导体组装结构10的方法之后执行，但不限于此。用于形成半导体封装结构11的方法包含操作110：提供包含第一侧及与所述第一侧相对的第二侧的第一封装结构组件。第一封装结构组件包含位于第一侧上的多个凹陷拐角及放置于所述凹陷拐角处的多个第一应力缓冲结构。用于形成半导体封装结构11的方法进一步包含操作112：在第一侧面对第二封装结构组件的情况下将第一封装结构组件接合到所述第二封装结构组件。用于形成半导体封装结构11的方法进一步包含操作114：在第一封装结构组件与第二封装结构组件之间形成底胶材料。第一应力缓冲结构的至少一部分与底胶材料接触且嵌入于底胶材料中。将根据一或多项实施例进一步阐述用于形成半导体封装结构11的方法。应注意，可在各项方面的范围内重新安排或以其它方式修改用于形成半导体组装结构11的方法的操作。应进一步注意，可在方法11之前、期间及之后提供额外工艺，且本文中可仅简要地阐述某些其它工艺。因此，其它实施方案在本文中所阐述的各项方面的范围内是可能的。
图3A到7C是图解说明一或多项实施例中的根据本揭露的方面构造的各个制造阶段处的半导体组装结构的图式。图3A是平面图，且图3B是沿着图3A的A-A'线的剖面图。参考图3A及图3B，根据操作102提供衬底202。在本揭露的某些实施例中，衬底202是包含多个切割道区域204及由切割道区域204界定的多个芯片区域206的半导体晶片。在某些实施例中，芯片区域206布置成通过与切割道区域204交叉而彼此分开的阵列。在某些实施例中，切割道区域204的宽度可介于大体上100微米(μm)与大体上500μm之间，但不限于此。根据本揭露的某些实施例，下文详细地阐述形成于芯片区域206上的结构。
请参考图3B。在某些实施例中，衬底202包含半导体材料，例如硅(Si)、锗(Ge)、金刚石或例如此类。在其它实施例中，衬底202可包含化合物材料，例如SiGe、碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)、磷化铟(InP)、碳化硅锗SiGeC、磷化铟镓(GaInP)、此些化合物材料的组合或例如此类。另外，衬底202可为绝缘体上硅(SOI)衬底。衬底202可包含主动及被动装置(未展示)。如所属领域的技术人员将认识到，多种装置(例如晶体管、电容器、电阻器、此些装置的组合及例如此类)可用于形成用于一或多个裸片的设计的结构及功能需要。可使用任何适合方法形成所述装置。在本揭露的某些实施例中，衬底202是其中通常不包含主动装置的中介层，尽管中介层可包含被动装置。
参考图3B，对半导体晶片执行半导体操作以在衬底202中形成贯穿衬底通路(TSV)210，在衬底202的表面202b上方形成互连结构212，及在衬底202的表面202b上方形成多个连接件214。如图3B中所展示，TSV 210是从衬底202的表面202b延伸到衬底202的深度中的导电通路。在某些实施例中，TSV 210包含金属通路及加内衬于金属通路的侧壁上的阻障层。金属通路可由铜(Cu)、铜合金、钨(W)、钨合金或例如此类形成而成。阻障层(未展示)充当扩散阻障且可由耐火金属、耐火金属氮化物、耐火金属氮化硅及其组合形成而成。举例来说但不限于，可使用钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、氮化硅钛(TiSiN)、氮化钨(WN)或其组合。在某些实施例中，在TSV 210与衬底202之间形成绝缘层216以便隔离TSV210与形成于衬底202中的其它连接。
互连结构212(有时称为重布层(RDL))形成于衬底202的表面202b上方且电耦合到TSV 210及形成于衬底202中的电路。互连结构212包含多个介电层、导电线及通路。介电层可包含氧化硅(SiO)、氮化硅(SiN)、碳化硅(SiC)、氧氮化硅(SiON)、低介电系数材料(例如硼磷硅酸盐玻璃(BPSG))、熔融硅玻璃(FSG)、氧碳化硅(SiOC)、旋涂聚合物、硅碳材料、其化合物、其组合物、其组合或例如此类。导电线形成于介电层中，且形成于同一介电层中的导电线以组合形成称为导电层。通路形成于不同导电层的导电线之间且电耦合不同导电层的导电线。导电线及通路可包含Cu、W、铝(Al)、其组合或例如此类。
连接件214形成于互连结构212上方且电耦合到互连结构212。连接件214可为焊球、金属柱、微凸块、无电镀镍无电镀钯浸金技术(ENEPIG)形成凸块或例如此类。连接件214可包含导电材料，例如焊料、Cu、Al、金(Au)、镍(Ni)、银(Ag)、钯(Pd)、锡(Sn)、其组合或例如此类。
仍参考图3B，至少一或多个半导体装置220可形成于衬底202的表面202b上方。在本揭露的某些实施例中，半导体装置220可为裸片220，且裸片220接合到衬底202的芯片区域206。裸片220可包含逻辑裸片，例如中央处理单元(CPU)、图形处理单元(GPU)、此些装置的组合或例如此类。裸片220可包含存储器裸片，例如DRAM裸片、SRAM裸片、此些装置的组合或例如此类。在某些实施例中，裸片220可包含输入/输出(I/O)裸片，例如宽I/O裸片。在某些实施例中，接合到衬底202的裸片220可为相同类型的裸片。举例来说但不限于，如图3B中所展示接合到衬底202的裸片220可全部为DRAM裸片。仍在某些实施例中，接合到衬底202的裸片220可为不同类型的裸片。举例来说但不限于，如图3B中所展示接合到衬底202的裸片220可为逻辑裸片及存储器裸片。在本揭露的某些实施例中，裸片220包含可包含逻辑裸片及存储器裸片两个的裸片堆迭(未展示)。可替代地采用半导体裸片的任何适合组合及半导体裸片的任何数目，且所有此类数目、组合及功能性都完全打算包含于本揭露的范围内。
在本揭露的某些实施例中，半导体装置220透过(举例来说但不限于)倒置接合而接合到衬底202，其中半导体装置220的连接件222接合到衬底202的连接件214。如图3B中所展示，然后向半导体装置220与衬底202之间的空间中及环绕连接件222/214施配底胶材料224。底胶材料224可包含(举例来说但不限于)液体环氧树脂、可变形凝胶、硅橡胶或例如此类。且然后使底胶材料224固化而变硬以便减少对连接件222/214的损坏且保护连接件222/214。接下来，将模塑料226成型于半导体装置220上。在某些实施例中，模塑料226包含聚合物、环氧树脂、SiO填充剂材料、其的组合或例如此类。在某些实施例中，将半导体装置220埋入于模塑料226中，且在使模塑料226固化之后可执行平坦化操作。执行平坦化操作以提供大体上平坦顶部表面且暴露半导体装置220的顶部表面，如图3B中所展示。
仍参考图3B，将多个连接件230放置于每一芯片区域206中。将连接件230放置于与表面202b相对的表面202a上。在本揭露的某些实施例中，执行薄化操作以从表面202a使衬底202变薄直到暴露TSV 210为止。且可在衬底202的表面202a上方形成介电层232。接下来，在介电层232上方形成连接件230，且连接件230电耦合到TSV 210，如图3B中所展示。连接件230可为焊球、金属柱、C4凸块、微凸块、ENEPIG形成凸块或例如此类。连接件230可包含焊料、Cu、Al、Au、Ni、Ag、Pd、Sn、其组合或例如此类。
图4A是衬底202的仰视图，在衬底202上方形成有连接件230，且连接件230在表面202a处于每一芯片区域206中布置成阵列。如上文所提及，芯片区域206通过与切割道区域204交叉而彼此分开。在本揭露的某些实施例中，根据操作104在切割道区域204中形成多个凹槽240。可在表面202a上方以连续方式在切割道区域204上形成凹槽240，使得凹槽240的平坦布局大体上类似于切割道区域204的平坦布局。因此，使凹槽240交叉以形成多个交叉区域242。在某些实施例中，由于相邻芯片区域206在切割道区域204上通过凹槽240分开，因此交叉区域242毗邻于四个不同芯片区域206的四个拐角，如图4A中所展示。在某些实施例中，可以非连续方式形成凹槽240，然而仍使凹槽240交叉以形成交叉区域242。在本揭露的某些实施例中，可通过使用激光切割、激光微喷射流切割、坡口切割、刀片锯割或例如此类而形成凹槽240。在某些实施例中，当采用坡口切割时，凹槽240可包含倾斜侧壁，如图4B中所展示，图4B是凹槽240的放大图式。在某些实施例中，当采用两步骤切割时，凹槽240可包含垂直侧壁，如图4C中所展示，图4C是凹槽240的放大图式。在又一些实施例中，凹槽240可包含弯曲侧壁。另外，取决于采用来形成凹槽240的切割方法，凹槽240的侧壁可具有平滑或粗糙表面。
参考图5A到5C，根据操作106在表面202a上方交叉区域242中形成多个第一应力缓冲结构250。换句话说，在每一交叉区域242中容纳每一第一应力缓冲结构250。在本揭露的某些实施例中，可通过将多个聚合物材料放置于交叉区域242上方而形成第一应力缓冲结构250。如图5A到5C中所展示，凹槽的交叉区域242填充有聚合物材料。此外，聚合物材料可从交叉区域242溢出。因此，在使聚合物材料固化以形成第一应力缓冲结构250之后，第一应力缓冲结构250中的一个的直径D大于凹槽240的宽度W，如图5A到5C中所展示。且第一应力缓冲结构250可分别具有弯曲表面。在某些实施例中，第一应力缓冲结构250可包含无填充剂的基于环氧树脂的材料。在某些实施例中，第一应力缓冲结构250可在基于环氧树脂的材料中包含填充剂。如图5A中所展示，第一应力缓冲结构250与连接件230间隔开。此外，第一应力缓冲结构250彼此间隔开，如图5A中所展示。
参考图6，在放置第一应力缓冲结构250之后，根据操作108从表面202a沿着凹槽240切割衬底202。因此，将衬底202的芯片区域206切粒成多个半导体组装结构200，例如中介层芯片。在本揭露的某些实施例中，由于个别半导体组装结构200包含接合到中介层衬底202的裸片220，因此半导体组装结构200可称为中介层封装结构组件上倒装芯片粒。在某些实施例中，将第一应力缓冲结构250中的每一个切割成保持于衬底202的四个拐角处的四个部分。
参考图7A到7C，个别半导体组装结构200包含第一侧200a及与第一侧200a相对的第二侧200b(展示于图8中)。更重要的是，半导体组装结构200包含第一侧202a上的多个凹陷拐角202C。凹陷拐角202C中的每一个是交叉区域242的一部分。半导体组装结构200进一步包含放置于凹陷拐角202C处的多个第一应力缓冲结构250。如图7B到7C中所展示，第一应力缓冲结构250分别具有弯曲表面250c。另外，第一应力缓冲结构250中的每一个包含大体上与半导体组装结构200的拐角侧壁202s对准的两个垂直侧壁250s，如图7B到7C中所展示。
图8到9是图解说明一或多项实施例中的根据本揭露的方面构造的各个制造阶段处的半导体封装结构的图式。参考图8，根据操作110提供第一封装结构组件。所述第一封装结构组件可为通过执行上述操作102到108而形成的半导体组装结构200，但不限于此。应理解，为了简洁全部省略TSV 210、互连结构212、连接件214/222及底胶材料224，且图8中仅展示一个半导体装置220，但所属领域的技术人员将根据前述说明容易地认识到那些元件及任何其它所需元件的形成及位置。第一封装结构组件200包含第一侧200a及与第一侧相对的第二侧200b。更重要的是，第一封装结构组件200包含凹陷拐角202C及放置于凹陷拐角202C处的多个第一应力缓冲结构250。在本揭露的某些实施例中，提供第二封装结构组件260。第二封装结构组件260可为有机衬底、电路板、电介质衬底或具有高密度互连件的半导体衬底。在某些实施例中，第二封装结构组件260的衬底可为由纤维玻璃或类似材料制成且包含印刷到板上以用于连接各种组件及封装结构的电线的印刷电路板(PCB)。第二封装结构组件260可包含形成于衬底上方的多个连接件262。连接件262可包含Cu、Cu合金、Sn、Sn合金、Au、Ni、Pd、其组合或例如此类。参考图8，根据操作112在第一侧200a面对第二封装结构组件260的情况下将第一封装结构组件200接合到第二封装结构组件260。第二封装结构组件260透过连接件230及连接件262电耦合到第一封装结构组件200。在本揭露的某些实施例中，由于第一应力缓冲结构250的高度小于连接件230的高度，因此第一应力缓冲结构250与第二封装结构组件260间隔开，如图8中所展示。
参考图9，根据操作114在第一封装结构组件200与第二封装结构组件260之间形成底胶材料264。因此，获得半导体封装结构270。底胶材料264可包含(举例来说但不限于)在第一封装结构组件200与第二封装结构组件260之间施配且然后被固化而变硬的液体环氧树脂、可变形凝胶、硅橡胶或例如此类。在本揭露的某些实施例中，底胶材料264包含填充剂。底胶材料264用于减少对电连接件230/262的损坏且保护电连接件230/262。在某些实施例中，第一应力缓冲结构250的至少一部分与底胶材料264接触且嵌入于底胶材料264中。可理解，当第一应力缓冲结构250不包含填充剂而底胶材料264包含填充剂时，第一应力缓冲结构250的弯曲表面的至少一部分与底胶材料264接触且嵌入于底胶材料264中。可理解，当第一应力缓冲结构250及底胶材料264两个都包含填充剂时，第一应力缓冲结构250及底胶材料264被视为包含两个合并部分的连续结构。且可推断出，第一封装结构组件200与第二封装结构组件260之间的此类连续结构覆盖第一封装结构组件200的凹陷拐角202C。
发现，可产生衬底202与第二封装结构组件260之间的热不匹配及/或翘曲不匹配，且因此半导体封装结构270可在热循环及/或可靠性加压期间遭受物理应力。此外，进一步观察到，拐角通常充当裂缝起始点。通过在第一封装结构组件200的凹陷拐角202C处提供第一应力缓冲结构250，应力得以缓冲，裂缝起始点被消除，且因此裂缝及脱层问题得以缓解。
请参考图10到12，其为图解说明一或多项实施例中的根据本揭露的方面构造的各个制造阶段处的半导体封装结构的示意图。应理解，为了清晰及简化通过相同元件符号而识别图3A到9及图10到12中的类似构件。此外，图3A到9及图10到12中的类似元件可包含类似材料，且因此为了简洁而省略那些细节。在本揭露的某些实施例中，可根据用于形成半导体组装结构10的方法提供半导体组装结构或第一半导体封装结构200'。第一半导体组件200'可类似于上述第一半导体组件200，且因此仅详述其差异。参考图10，其为根据操作102提供的衬底202的仰视图。衬底202可包含多个切割道区域及由所述切割道区域界定的多个芯片区域206。可对半导体晶片执行半导体操作以在衬底202中形成TSV(未展示)，在衬底202的表面上方形成互连结构(未展示)，及在衬底202的表面上方形成多个连接件(未展示)。可在衬底202的表面上方形成至少一或多个半导体装置220，例如裸片。且可替代地采用半导体裸片的任何适合组合及半导体裸片的任何数目，且所有此类数目、组合及功能性都完全打算包含于本揭露的范围内。如上文所提及，半导体装置220透过连接件接合到衬底202。可向裸片220与衬底202之间的空间中及环绕连接件施配底胶材料(未展示)。将模塑料226(展示于图12中)成型于半导体装置220上，且在某些实施例中，后续接着执行平坦化操作以提供大体上平坦顶部表面且暴露半导体装置220的顶部表面。
参考图10，将多个连接件230放置于每一芯片区域206中。将连接件230放置于与裸片220相对的表面202a上，且连接件230电耦合到TSV。在本揭露的某些实施例中，根据操作104在切割道区域中形成多个凹槽240，如图10中由虚线展示。可在切割道区域上以连续方式形成凹槽240，使得凹槽240的平坦布局大体上类似于切割道区域的平坦布局。因此，使凹槽240交叉以形成多个交叉区域242，如图10中所展示。在某些实施例中，由于相邻芯片区域206通过切割道区域上的凹槽240分开，因此交叉区域242毗邻于四个不同芯片区域206的四个拐角，如图10中所展示。
仍参考图10，根据操作106在表面202a上方交叉区域242中形成多个第一应力缓冲结构250。在本揭露的某些实施例中，同时在表面202a上方凹槽240中形成多个第二应力缓冲结构252。在本揭露的某些实施例中，可通过将多个聚合物材料放置于凹槽240及交叉区域242上方而形成第一应力缓冲结构250及第二应力缓冲结构252。如图10中所展示，凹槽240及交叉区域242填充有聚合物材料。此外，聚合物材料可从凹槽240及交叉区域242溢出。因此，在使聚合物材料固化之后，第一应力缓冲结构250中的一个的直径D及第二应力缓冲结构252的宽度大于凹槽240的宽度W，如图10中所展示。且第一应力缓冲结构250及第二应力缓冲结构252可分别具有弯曲表面。在某些实施例中，第一应力缓冲结构250可包含无填充剂的基于环氧树脂的材料。在某些实施例中，第一应力缓冲结构250可在基于环氧树脂的材料中包含填充剂。如图10中所展示，第一应力缓冲结构250及第二应力缓冲结构252与连接件230间隔开。此外，第二应力缓冲结构252中的每一个接触且连接两个毗邻第一应力缓冲结构250。换句话说，第一应力缓冲结构250及第二应力缓冲结构252彼此连接以形成应力缓冲框架，如图10中所展示。
参考图11，在放置第一应力缓冲结构250及第二应力缓冲结构252之后，根据操作108从表面202a沿着凹槽240切割衬底202。因此，将衬底202的芯片区域206切粒成多个半导体组装结构200'，例如中介层芯片。在本揭露的某些实施例中，由于个别半导体组装结构200'包含接合到中介层衬底202的裸片220，因此半导体组装结构200'可称为中介层封装结构组件上倒装芯片粒。在某些实施例中，将第一应力缓冲结构250中的每一个切割成保持于衬底202的四个拐角上的四个部分。将第二应力缓冲结构252中的每一个切割成保持于衬底202的四个边缘上的两个部分。
图12中展示半导体组装结构200'的剖面图。参考图12，半导体组装结构200'包含第一侧202a及第二侧202b。更重要的是，半导体组装结构200'包含第一侧202a上方的多个凹陷拐角202C及第一侧202a上方的多个凹陷边缘202E。凹陷拐角202C中的每一个是交叉区域242的一部分，且凹陷边缘中的每一个是凹槽240的一部分。连接件230附近的虚线表示衬底202的表面以及凹陷拐角202C及凹陷边缘202E的开口。裸片220附近的虚线表示凹陷拐角202C及凹陷边缘202E的底部。连接上述两条虚线的倾斜虚线表示凹陷拐角202C及凹陷边缘202E的侧壁。半导体组装结构200'进一步包含放置于凹陷拐角202C处的多个第一应力缓冲结构250及放置于凹陷边缘202E上方的多个第二应力缓冲结构252。第一应力缓冲结构250分别具有弯曲表面。另外，第一应力缓冲结构中的每一个包含大体上与半导体组装结构200'的拐角侧壁对准的两个垂直侧壁。第二应力缓冲结构252分别具有弯曲表面。另外，第二应力缓冲结构252中的每一个包含大体上与半导体组装结构200'的边缘侧壁对准的垂直侧壁，如图12中所展示。
参考图12，在本揭露的某些实施例中，根据操作110提供第一封装结构组件，例如半导体组装结构200'，且根据操作112在第一侧200a面对第二封装结构组件260的情况下将第一封装结构组件200'接合到第二封装结构组件260。第二封装结构组件260透过连接件230及连接件262电耦合到第一封装结构组件200'。在本揭露的某些实施例中，由于第一应力缓冲结构250及第二应力缓冲结构252的高度小于连接件230的高度，因此第一应力缓冲结构250及第二应力缓冲结构252全部与第二封装结构组件260间隔开，如图12中所展示。
仍参考图12，根据操作114在第一封装结构组件200'与第二封装结构组件260之间形成底胶材料264。因此，获得半导体封装结构270'。在某些实施例中，第一应力缓冲结构250的至少一部分及第二应力缓冲结构252的至少一部分与底胶材料264接触且嵌入于底胶材料264中。可理解，当第一应力缓冲结构250不包含填充剂时，第一应力缓冲结构250的弯曲表面的一部分及第二应力缓冲结构252的弯曲表面的一部分与底胶材料264接触且嵌入于底胶材料264中。
将了解，在前述方法中，在凹槽的交叉区域中形成第一应力缓冲结构。换句话说，在半导体组装结构或第一半导体封装结构组件的凹陷拐角处形成第一应力缓冲结构。如上文所提及，拐角经常充当裂缝起始点，因此通过在第一封装结构组件的凹陷拐角处提供第一应力缓冲结构，应力得以缓冲，裂缝起始点被消除，且因此裂缝及脱层问题得以缓解。
根据本揭露的一项实施例，提供一种用于形成半导体组装结构的方法。所述方法包含：提供衬底，所述衬底包含多个切割道区域；在所述切割道区域中形成多个凹槽，其中使所述凹槽交叉以形成多个交叉区域；将多个第一应力缓冲结构放置于所述交叉区域中，其中所述第一应力缓冲结构中的一个的直径大于所述凹槽的宽度；及在放置所述第一应力缓冲结构之后沿着所述凹槽进行切割。
根据另一实施例，提供一种用于形成半导体封装结构的方法。所述方法包含：提供第一封装结构组件，所述第一封装结构组件包括第一侧及与所述第一侧相对的第二侧，其中所述第一封装结构组件包括位于所述第一侧上的多个凹陷拐角及放置于所述凹陷拐角处的多个第一应力缓冲结构；在所述第一侧面对第二封装结构组件的情况下将所述第一封装结构组件接合到所述第二封装结构组件；及在所述第一封装结构组件与所述第二封装结构组件之间形成底胶材料，其中所述第一应力缓冲结构的至少一部分与所述底胶材料接触且嵌入于所述底胶材料中。
根据本揭露的一项实施例，提供一种半导体封装结构。所述半导体封装结构包含：第一封装结构组件，所述第一封装结构组件包含第一侧、与所述第一侧相对的第二侧及位于所述第一侧上方的多个凹陷拐角；多个第一应力缓冲结构，其放置于所述凹陷拐角处，其中所述第一应力缓冲结构中的每一个具有弯曲表面；第二封装结构组件，其连接到所述第一封装结构组件的所述第一侧；多个连接件，其放置于所述第一封装结构组件与所述第二封装结构组件之间，且所述连接件电耦合所述第一封装结构组件与所述第二封装结构组件；及底胶材料，其位于所述第一封装结构组件与所述第二封装结构组件之间，其中所述第一应力缓冲结构的所述弯曲表面的至少一部分与所述底胶材料接触且嵌入于所述底胶材料中。
前述内容概述数个实施例的构件，使得所属领域的技术人员可更优选地理解本揭露的方面。所属领域的技术人员应了解，其可容易地使用本揭露作为用于设计或修改其它工艺及结构以用于执行本文中所介绍的实施例的相同目的及/或达成本文中所介绍的实施例的相同优点的基础。所属领域的技术人员还应认识到，此类等效构造不背离本揭露的精神及范围，且其可在本文中在不背离本揭露的精神及范围的情况下做出各种改变、替代及更改。
符号说明
200 半导体组装结构/第一封装结构组件/第一半导体组件
200' 第一半导体封装结构/第一半导体组件
200a 第一侧
200b 第二侧
202 衬底/中介层衬底
202a 表面/第一侧
202b 表面/第二侧
202C 凹陷拐角
202E 凹陷边缘
202s 拐角侧壁
204 切割道区域
206 芯片区域
210 贯穿衬底通路
212 互连结构
214 连接件
216 绝缘层
220 半导体装置/裸片
222 连接件
224 底胶材料
226 模塑料
230 连接件/电连接件
232 介电层
240 凹槽
242 交叉区域
250 第一应力缓冲结构
250c 弯曲表面
250s 垂直侧壁
252 第二应力缓冲结构
260 第二封装结构组件
262 连接件/电连接件
264 底胶材料
270 半导体封装结构
270' 半导体封装结构/半导体组装结构
D 直径
W 宽度

Claims (33)

1.一种用于形成半导体组装结构的方法，其包括：
提供衬底，所述衬底包括第一表面，与所述第一表面相对的第二表面，及多个在第一表面的切割道区域，其中至少一个半导体装置与模塑料放置于所述第二表面；
在所述第一表面的所述切割道区域中，经切割所述第一表面形成多个凹槽，其中使所述凹槽交叉以形成多个交叉区域；
将多个第一应力缓冲结构放置于所述交叉区域中，其中所述第一应力缓冲结构中的一个的直径大于所述凹槽的宽度；
在放置所述第一应力缓冲结构之后沿着所述凹槽进行切割以形成第一封装结构组件；及
接合所述第一封装结构组件到第二封装结构组件，其中所述第一应力缓冲结构与所述第二封装结构组件间隔开。
2.根据权利要求1所述的方法，其中所述衬底包括由所述切割道区域界定的多个芯片区域。
3.根据权利要求2所述的方法，其进一步包括在放置所述第一应力缓冲结构之前将多个连接件放置于每一芯片区域中，且在放置所述第一应力缓冲结构的同时将多个第二应力缓冲结构放置于所述凹槽中；其中所述第一应力缓冲结构及所述第二应力缓冲结构与所述连接件间隔开。
4.根据权利要求3所述的方法，其中在所述切割道区域中形成所述多个凹槽包括斜面切割操作。
5.根据权利要求1所述的方法，其中所述第一应力缓冲结构的所述放置进一步包括：
将多个聚合物材料放置于所述交叉区域上方；及
使所述聚合物材料固化以形成所述第一应力缓冲结构。
6.根据权利要求1所述的方法，其中所述第一应力缓冲结构包括基于环氧树脂的材料。
7.根据权利要求6所述的方法，其中所述第一应力缓冲结构在所述基于环氧树脂的材料中包括填充剂。
8.根据权利要求3所述的方法，其中所述第二应力缓冲结构接触所述第一应力缓冲结构。
9.根据权利要求3所述的方法，其中所述第二应力缓冲结构的宽度大于所述凹槽的所述宽度，且所述第二应力缓冲结构的宽度小于所述第一应力缓冲结构的直径。
10.一种用于形成半导组装结构的方法，其包括：
接收半导体晶片，所述半导体晶片包括第一表面、与所述第一表面相对的第二表面，及多个芯片区域和在所述第一表面上方将个别芯片区域间隔开的切割道区域，其中至少半导体装置及模制化合物放置在所述第二表面上方；
在所述切割道区域中，将多个连接件放置于所述芯片区域中的一个中；
在所述第一表面上方的所述切割道区域中，经切割所述第一表面形成多个凹槽，其中使所述凹槽交叉以形成多个交叉区域；
将多个第一应力缓冲结构及多个第二应力缓冲结构放置于所述交叉区域处，其中所述第一应力缓冲结构中的一个的直径大于所述凹槽的宽度；
通过沿着所述凹槽进行切割而切穿所述第一应力缓冲结构中的一个，形成第一封装结构组件；其中所述第一应力缓冲结构及所述第二应力缓冲结构与所述连接件间隔开；及
接合所述第一封装结构组件到第二封装结构组件，其中所述第一应力缓冲结构与所述第二封装结构组件间隔开。
11.根据权利要求10所述的方法，其中所述第一应力缓冲结构包括基于环氧树脂的材料。
12.根据权利要求10所述的方法，其中所述第二应力缓冲结构接触所述第一应力缓冲结构。
13.根据权利要求10所述的方法，其中在所述切割道区域中形成所述多个凹槽包括斜面切割操作。
14.一种半导体封装结构，其包括：
第一封装结构组件，其包括第一侧、与所述第一侧相对的第二侧，及在所述第一侧处的多个凹陷拐角；
多个第一应力缓冲结构，其放置于所述凹陷拐角处，其中所述第一应力缓冲结构中的每一个具有弯曲表面；
多个第二应力缓冲结构，其放置于所述第一封装结构组件的第一侧处的多个凹陷边缘上方；
第二封装结构组件，其连接到所述第一封装结构组件的所述第一侧，其中所述第一应力缓冲结构与所述第二封装结构组件间隔开；
多个连接件，其放置于所述第一封装结构组件与所述第二封装结构组件之间，且所述连接件电耦合所述第一封装结构组件与所述第二封装结构组件；及
底胶材料，其位于所述第一封装结构组件与所述第二封装结构组件之间，其中所述第一应力缓冲结构的所述弯曲表面的至少一部分与所述底胶材料接触且嵌入于所述底胶材料中；
其中所述第一应力缓冲结构及所述第二应力缓冲结构与所述连接件间隔开。
15.根据权利要求14所述的半导体封装结构，其中所述第一应力缓冲结构包括基于环氧树脂的材料。
16.根据权利要求14所述的半导体封装结构，其中所述第一应力缓冲结构与所述第二封装结构组件经由所述底胶材料间隔开。
17.根据权利要求14所述的半导体封装结构，其中所述多个凹陷边缘中的一个连接两个毗邻第一应力缓冲结构，且所述第二应力缓冲结构接触所述第一应力缓冲结构。
18.一种半导体封装结构，其包括：
第一封装结构组件，其包括第一侧、与所述第一侧相对的第二侧，在所述第一侧处的凹陷拐角，及在所述第一侧上方且耦合到所述凹陷拐角的凹陷边缘；
第一应力缓冲结构，其放置于所述凹陷拐角处；
第二应力缓冲结构，其放置于所述凹陷边缘上方；
第二封装结构组件，其连接到所述第一封装结构组件的所述第一侧，其中所述第一应力缓冲结构与所述第二封装结构组件间隔开；
连接件，其放置于所述第一封装结构组件与所述第二封装结构组件之间；
及
底胶材料，其位于所述第一封装结构组件与所述第二封装结构组件之间，
其中所述第一应力缓冲结构具有与所述第一封装结构组件接触的第一表面及耦合到所述第一表面且与所述底胶材料接触的第二表面；且
其中所述第一应力缓冲结构及所述第二应力缓冲结构与所述连接件间隔开。
19.根据权利要求18所述的半导体封装结构，其中所述第一应力缓冲结构的所述第一表面完全与所述第一封装结构组件接触。
20.根据权利要求18所述的半导体封装结构，其中所述第一应力缓冲结构的所述第二表面完全与所述底胶材料接触且嵌入于所述底胶材料内。
21.根据权利要求18所述的半导体封装结构，其中所述第一应力缓冲结构包括耦合到所述第一表面及所述第二表面的第三表面，且所述第三表面与所述第一封装结构组件的侧壁表面对准。
22.根据权利要求21所述的半导体封装结构，其中所述第一封装结构组件包括衬底及模制化合物，且所述第一应力缓冲结构的所述第三表面与所述衬底的侧壁表面及所述模制化合物的侧壁表面对准。
23.根据权利要求21所述的半导体封装结构，其中所述第一应力缓冲结构的所述第三表面的一部分与所述底胶材料接触，且所述第三表面的一部分通过所述底胶材料暴露。
24.根据权利要求18所述的半导体封装结构，其中所述第一应力缓冲结构包括基于环氧树脂的材料。
25.根据权利要求24所述的半导体封装结构，其中所述第一应力缓冲结构在所述基于环氧树脂的材料中包括填充剂。
26.根据权利要求18所述的半导体封装结构，其中所述连接件电耦合所述第一封装结构组件与所述第二封装结构组件。
27.根据权利要求18所述的半导体封装结构，其中所述第一应力缓冲结构的侧壁表面及所述第二应力缓冲结构的侧壁表面通过所述底胶材料暴露。
28.根据权利要求18所述的半导体封装结构，其中所述第二应力缓冲结构耦合到所述第一应力缓冲结构。
29.一种半导体封装结构，其包括：
第一封装结构组件，其包括第一侧、与所述第一侧相对的第二侧、在所述第一侧处的凹陷拐角，及在所述第一侧处耦合到所述凹陷拐角的凹陷边缘；
第一应力缓冲结构，其放置于所述凹陷拐角处；
第二应力缓冲结构，其放置于所述凹陷边缘上方；
第二封装结构组件，其连接到所述第一封装结构组件的所述第一侧，其中所述第一应力缓冲结构与所述第二封装结构组件间隔开；
多个连接件，其放置于所述第一封装结构组件与所述第二封装结构组件之间，且所述连接件电耦合所述第一封装结构组件与所述第二封装结构组件；及
底胶材料，其位于所述第一封装结构组件与所述第二封装结构组件之间，
其中所述第一应力缓冲结构及所述第二应力缓冲结构放置在所述底胶材料与所述第一封装结构组件之间；且
其中所述第一应力缓冲结构及所述第二应力缓冲结构与所述连接件间隔开。
30.根据权利要求29所述的半导体封装结构，其中所述第一应力缓冲结构的侧壁表面及所述第二应力缓冲结构的侧壁表面通过所述底胶材料暴露。
31.根据权利要求30所述的半导体封装结构，其中所述第一应力缓冲结构的所述侧壁表面及所述第二应力缓冲结构的所述侧壁表面与所述第一封装结构组件的侧壁表面对准。
32.根据权利要求29所述的半导体封装结构，其中所述第一应力缓冲结构包括基于环氧树脂的材料。
33.根据权利要求32所述的半导体封装结构，其中所述第一应力缓冲结构在所述基于环氧树脂的材料中包括填充剂。
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