CN104282650A - 具有坝体结构的中介层上管芯组件及其制造方法 - Google Patents

具有坝体结构的中介层上管芯组件及其制造方法 Download PDF

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Publication number
CN104282650A
CN104282650A CN201310422113.6A CN201310422113A CN104282650A CN 104282650 A CN104282650 A CN 104282650A CN 201310422113 A CN201310422113 A CN 201310422113A CN 104282650 A CN104282650 A CN 104282650A
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China
Prior art keywords
intermediary layer
substrate
layer chip
back side
chip
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CN201310422113.6A
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吴志伟
卢思维
林俊成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to CN201811363828.8A priority Critical patent/CN109599380A/zh
Publication of CN104282650A publication Critical patent/CN104282650A/zh
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Abstract

本发明提供了一种半导体封装件，包括中介层芯片，其具有正面、后面和位于背面上由中介层芯片的第一拐角边缘和第二拐角边缘限定的拐角区。管芯接合至中介层芯片的正面。至少一个坝体结构形成于中介层芯片背面的拐角区上。坝体结构包括与中介层芯片的第一拐角边缘和第二拐角边缘中的至少一个边缘对齐的边缘。本发明还提供了一种形成组件的方法。

Description

具有坝体结构的中介层上管芯组件及其制造方法
技术领域
本发明总体涉及半导体领域，更具体地，涉及具有坝体结构的中介层上管芯组件及其制造方法
背景技术
当前对集成电路的制造和封装的普遍需求是使用中介层来容纳单个或多个集成电路管芯。贯穿中介层的通孔或硅通孔的使用日益增加。这些通孔允许安装在中介层一面上的集成电路管芯和部件与安装在中介层的另一面上的诸如焊料球的接线端子之间的电耦合。而且，通孔技术使得中介层组件的晶圆级加工成为可能。例如，这种技术日益适用于增加存储器或储存设备的密度而不增加电路板面积。随着对诸如智能手机和平板电脑的手持式和便携式设备的需求的增加，对电路板面积和电路板尺寸的限制也在增加，而具有通孔的中介层组件的使用可满足这些要求。这些技术应用于半导体晶圆，其中，可执行通孔连接、用于连接部件的导电图案化和部件安装。
发明内容
根据本发明的一个方面，提供一种半导体封装件，包括：中介层芯片，具有正面、背面和位于背面并且由中介层芯片的第一拐角边缘和第二拐角边缘限定的拐角区；管芯，接合至中介层芯片的正面；以及至少一个坝体结构，位于中介层芯片的背面的拐角区上。其中，坝体结构包括与中介层芯片的第一拐角边缘和第二拐角边缘中的至少一个边缘对齐的边缘。
优选地，该半导体封装件还包括：位于中介层芯片的正面上并且围绕管芯的聚合物层。
优选地，聚合物层包括与坝体结构的边缘对齐的外边缘。
优选地，坝体结构包括聚合物。
优选地，该半导体封装件，还包括：位于中介层芯片的背面上的多个凸块结构。
优选地，中介层芯片包括：半导体衬底，具有第一面和与第一面相对的第二面；衬底通孔，穿过半导体衬底；互连结构，形成于半导体衬底的第一面上并且电连接至衬底通孔；以及多个凸块结构，形成于半导体衬底的第二面上并且电连接至衬底通孔。
优选地，坝体结构形成于半导体衬底的第二面上而不与衬底通孔电连接。
优选地，该半导体封装件还包括：接合至中介层芯片的背面的衬底，坝体结构位于衬底与中介层芯片之间的间隙中。
根据本发明的另一方面，提供了一种形成组件的方法，包括：提供具有正面和背面的晶圆，晶圆包括被划线区分隔的多个芯片区；将管芯接合至晶圆的正面以形成晶圆上管芯组件；在晶圆的背面上的划线区的交叉部分上形成多个坝体结构；以及对划线区执行切割工艺以将晶圆上管芯组件分离成多个单个组件。
优选地，多个芯片区中的每一个均包括与划线区的交叉部分邻近的四个拐角区，并且坝体结构被形成为延伸至四个拐角区。
优选地，在执行切割工艺之后，坝体结构保留在芯片区的四个拐角区上。
优选地，在执行切割工艺之后，坝体结构包括与单个组件的外边缘对齐的边缘。
优选地，形成多个坝体结构包括分布液体聚合物材料。
优选地，该方法还包括：在形成多个坝体结构之前，在晶圆的背面上形成多个凸块结构。
优选地，该方法还包括：在晶圆的正面上形成聚合物层以围绕管芯。
优选地，晶圆包括：半导体衬底，具有第一面和与第一面相对的第二面；衬底通孔，穿过半导体衬底；互连结构，形成在半导体衬底的第一面上并且电连接至衬底通孔；以及多个凸块结构，形成在半导体衬底的第二面上并且电连接至衬底通孔。
优选地，多个坝体结构没有电连接至衬底通孔。
根据本发明的又一方面，提供了一种半导体封装件，包括：中介层芯片，具有正面、背面和位于背面上并且由中介层芯片的成对的第一拐角边缘和成对的第二拐角边缘限定的四个拐角区；管芯，接合至中介层芯片的正面；聚合物层，形成在中介层芯片的正面上并且围绕管芯；四个聚合物坝体结构，位于中介层芯片背面的四个拐角区上，四个聚合物坝体结构中的每一个均包括与中介层芯片的第一拐角边缘对齐的第一边缘和与中介层芯片的第二拐角边缘对齐的第二边缘；以及衬底，接合至中介层芯片的背面，四个聚合物坝体结构位于衬底与中介层芯片之间。
优选地，每个聚合物坝体结构的第一边缘均与聚合物层的外边缘对齐。
优选地，中介层芯片包括：半导体衬底，具有第一面和与第一面相对的第二面；衬底通孔，穿过半导体衬底；互连结构，形成在半导体衬底的第一面上并且电连接至衬底通孔；以及多个凸块结构，位于半导体衬底的第二面上并且电连接至衬底通孔。其中，多个凸块结构位于衬底与中介层芯片之间。
附图说明
图1A是根据一个实施例的中介层的顶视图；
图1B是图1A中所示中介层的截面图；
图2为示出了根据各个实施例的晶圆上管芯组件的形成的截面图；
图3为示出了图2中所示半导体晶圆的背面结构的形成的截面图；
图4至图7为示出了根据各个实施例的晶圆上管芯组件背面上的坝体结构的形成的中间阶段的底视图；
图8为示出了图7所示中介层上管芯组件的截面图；
图9为示出了根据各个实施例的中介层上管芯组件形成在衬底上的截面图；
图10为示出了根据其它实施例的晶圆上管芯组件背面上的坝体结构形成的底视图；
图11为示出了图10所示单个组件的截面图；以及
图12为示出了根据各个实施例的中介层上管芯组件形成在衬底上的截面图。
具体实施方式
下面，详细论述本发明的实施例的制造与使用。然而，应该理解，这些实施例提供了许多可以在各种具体环境中实现的可应用的创造性概念。所论述的具体实施例仅仅是示意性的，而不限制本发明的范围。
根据各个实施例，提供了具有坝体结构的中介层上管芯组件及其制造方法。说明了根据实施例形成中介层上管芯组件的中间阶段。论述了实施例的变型。在各个附图和说明的实施例中，相同的附图编号用于标示相同的元件。
图1A示出了根据一个实施例的中介层的顶视图。图1B示出了根据一个实施例的图1A中所示中介层的截面图，其中图1B中的截面图是沿着图1A中所示的线1B-1B获得的。参见图1A，提供了包括多个芯片区（或管芯区）10的半导体晶圆100，其中在芯片区10上制造互连结构和金属凸块。在一个实施例中，半导体晶圆100包括通过两组交叉的划线区12而彼此分隔开的芯片区10的阵列。第一组划线区12沿着第一方向延伸，而第二组划线区12沿着第二方向延伸。根据一个实施例，形成于芯片区10上的结构会在下面详细描述。
参见图1B，对半导体晶圆100执行半导体工艺以形成半导体衬底14中的衬底通孔（TSV）结构16、半导体衬底14上的互连结构20以及互连结构20上的金属凸块30。
例如半导体衬底14可包括例如块状硅（掺杂或未掺杂的）或绝缘体上半导体（SOI）衬底中的有源层。还可使用诸如多层衬底或梯度衬底的其它衬底。半导体衬底14包括正面14A和背面14B。在一些实施例中，电路（未示出）形成在半导体衬底14的正面14A的内部和/或上面。例如，电路可包括互连的以执行一种或多种功能的各种有源器件和/或无源器件。有源器件可包括N型金属氧化物半导体（NMOS）器件、P型金属氧化物半导体（PMOS）器件和其它类型的晶体管，而无源器件可包括电容器、电阻器、二极管、光电二极管、熔丝等。所执行的功能可包括存储器结构、处理器结构、传感器、放大器、功率分布、输入/输出电路等等。在一些实施例中，有源器件并不在半导体衬底14的正面14A的内部和/或上面形成。
TSV结构16是从正面14A延伸至半导体衬底14深处的导电通孔。在一些实施例中，TSV结构16包括金属通孔和衬垫金属通孔侧壁的阻挡层。金属通孔可由铜、铜合金、钨、钨合金等形成。阻挡层（未示出）用于阻挡扩散并且可由耐熔金属、耐熔金属氮化物、耐熔金属硅氮化物以及它们的组合形成。例如，可使用TaN、Ta、Ti、TiN、TiSiN、WN或它们的组合。在一些实施例中，绝缘层18形成于TSV结构16与半导体衬底14之间，以便将TSV结构16与在半导体衬底14中形成的其它连接件隔离。绝缘层18可包括通过热氧化工艺或使用包括SACVD（次常压化学汽相沉积）、PECVD（等离子体增强化学汽相沉积）、PEALD（等离子体增强原子层沉积）和未来开发的沉积技术的多种技术中的任一种技术而形成的氧化层。
互连结构20形成于半导体衬底14上方，并且用于电连接至在半导体衬底14中形成的TSV结构16和电路。互连结构20可包括多个介电层22、金属线24和金属通孔26。介电层22可包括层间介电（ILD）质和/或金属间介电（IMD）质。金属线24形成于介电层22中，其中，位于同一介电层22中的金属线24统称为金属层。金属通孔26形成于不同金属层中的金属线24之间并且将其互连。在一个实施例中，介电层22包括至少一个并且可能是多个具有低介电常数（k）值的低k介电层。例如，介电层22中的低k介电材料的k值可低于约3.0或低于约2.5。根据一些实施例，互连结构20还包括位于介电层22上方的钝化层28。诸如聚酰亚胺层（未示出）的附加层、钝化后互连件（PPI，未示出）也可形成在钝化层28的内部和/上面。
第一凸块结构30形成于互连结构20上方并且电连接至互连结构20。在一些实施例中，第一凸块结构30为铜凸块、焊料凸块或它们的组合。在可选实施例中，每个第一凸块结构30均包括铜柱和焊料盖顶，其中镍层、金层、钯层或它们的组合可添加到铜柱与焊料盖顶之间。
图2为示出晶圆上管芯组件的形成的截面图，其中，多个管芯40分别接合至半导体晶圆100的芯片区10上。在一个实施例中，管芯40通过倒装芯片接合附接至芯片区10上，其中，管芯40的第二凸块结构42接合至半导体晶圆100的第一凸块结构30上。管芯40可为包括逻辑电路管芯、存储器管芯等的器件管芯，或者可为包括接合至中介层的管芯、封装衬底等的封装件。根据一些实施例，底部填充物46分散在管芯40与半导体晶圆100之间的空间中，然后固化底部填充物46。接下来，将聚合物层48模制在管芯40和半导体晶圆100上。在一个实施例中，聚合物层48是模塑料、环氧树脂等。聚合物层48可覆盖管芯40、底部填充物46和钝化层28。在一个实施例中，在聚合物层48固化后，执行诸如研磨的平坦化步骤以使聚合物层48的顶面平齐。聚合物层48的剩余部分的顶面48A可高于管芯40的背面40B或与之平齐。图2中所示结构为晶圆上管芯组件200，其中，管芯40接合至用作中介层晶圆的半导体晶圆100。
图3为示出了半导体晶圆100的背面结构的形成的截面图。图3中所示的晶圆上管芯组件200是翻转倒置的，因而使半导体衬底14朝上。对半导体衬底14的背面14B执行背面研磨以使半导体衬底14变薄，直到露出TSV结构16。介电层50和第三凸块结构52形成于半导体衬底14的背面14B上，其中，根据一些实施例，第三凸块结构52形成在芯片区10上并且电连接至TSV结构16。在一个实施例中，第三凸块结构52为焊料凸块。再分配线（RDL，未示出）可选地形成于介电层50内部和/或上面，其中，该形成过程类似于介电层22中的金属线和通孔的形成。第三凸块结构52可用于接合至附加的电气部件（未示出），这些部件可能为封装衬底、印刷电路板（PCB）等。例如，第三凸块结构52的直径大于第一凸块结构30的直径或大于第二凸块结构42的直径。
图4至图7为根据各个实施例的示出了在晶圆上管芯组件200的背面上形成坝状结构的中间阶段的底视图。
图4是晶圆上管芯组件200的底视图，其中，第三凸块结构52的阵列形成在半导体晶圆100的背面上的每个芯片区10上。相邻的芯片区10由划线区12分隔开，并且划线区12形成设置有坝体结构的交叉部分12A。每个芯片区10均包括与交叉部分12A邻近的四个拐角区10C，并且根据一些实施例，随后形成的坝体结构会延伸至四个拐角区10C。
参见图5，坝体结构60在半导体晶圆100的背面上形成。在一个实施例中，坝体结构60形成在与凸块结构52邻近的介电层50上，而并未电连接至互连结构20。坝体结构60位于交叉部分12A上并且延伸至相邻的芯片区10的拐角区10C，从而在晶圆上管芯组件200的背面上形成坝体结构60的栅格阵列。坝体结构60具有的宽度（Wd）大于或等于划线区12的宽度（Ws）。例如，Wd≥80um。在一些实施例中，宽度（Wd）大于或等于第三凸块结构52的宽度（Wb）。例如，Wd≥（1至4）*Wb。坝体结构60的高度与第三凸块结构52的高度（Hb）一样或比其略小。如果用于坝体结构60的材料具有高粘合性，则可从与晶圆级的加工和封装兼容的各种材料中选择。在一个实施例中，坝体结构60由聚合物材料形成。例如，可使用诸如环氧树脂或树脂等流体状的液体材料。可执行固化步骤以使坝体结构60固化。在一些实施例中，在随后的切割工艺后，坝体结构60会部分保留在芯片区10上，以便控制该组件与另一衬底之间的间隙。在一些实施例中，坝体结构60可被认为是“应力释放部件”，其能够在相邻的芯片区10之间形成支撑并且建立栅格矩阵以减少或消除晶圆式翘曲。
接下来，参见图6，对划线区12执行切割工艺以使单个组件300相互分离，因此将晶圆100的芯片区10切割成接合至相应管芯40的多个中介层芯片10A。例如，在切割工艺中使用刀片或激光。在至少一个实施例中，单个组件300包括接合至中介层芯片10A的管芯40，而中介层芯片10A用于将管芯40连接至另一衬底，使得每个组件300也都被认为是中介层上管芯组件300。在切割工艺过程中，每个坝体结构60都被切割成保留在中介层芯片10A的四个拐角区10C上的四个部分60A，因此保留部分60A用作在中介层上管芯组件300的背面上的坝体结构。如图7所示，在中介层上管芯组件300中，坝体结构60A形成在中介层芯片10A的四个拐角区10C上，其中，四个拐角区10C受成对的第一拐角边缘10A1和第二拐角边缘10A2限定。因此，如图7所示，坝体结构60A的外边缘60A1和60A2与中介层芯片10A的拐角边缘10A1和10A2基本对齐。
图8为示出了图7中所示中介层上管芯组件300的截面图，其中，第三凸块结构52和坝体结构60A朝上。除非另有说明外，这些实施例中的参考数字代表图1至图3所示实施例中的类似元件。在中介层上管芯组件300中，管芯40接合至中介层芯片10A的正面10Af上并且被聚合物层48围绕，而凸块结构52形成在中介层芯片10A的背面10Ab上，并且坝体结构60A形成在中介层芯片10A的背面10Ab的拐角区10C上。拐角区10C由拐角边缘10A1和10A2限定。在一个实施例中，坝体结构60A的外边缘60A1或60A2与中介层芯片10A的拐角边缘10A1基本对齐。在一个实施例中，坝体结构60A的外边缘60A1或60A2与聚合物层48的外边缘48A1基本对齐。
在中介层上管芯组件300上形成坝体结构60A之后，可实施其它封装工艺。图9为示出了根据各个实施例的在衬底上形成中介层上管芯组件的截面图。除非另有说明，这些实施例中的参考数字代表图1至图3所示实施例中的类似元件。中介层上管芯组件300附接至衬底400以形成半导体封装件500。衬底400可为具有高密度互连件的有机衬底、电路板、介电质衬底或半导体衬底。在一个实施例中，衬底400为印刷电路板（PCB），其由玻璃纤维或类似材料制成并且包括印制在板上用于连接各个部件和封装件的电引线。中介层上管芯组件300通过将第三凸块结构52连接至衬底400上的连接件402上而电耦合至衬底400。在一些实施例中，连接件402由铜、铜合金、锡、锡合金、金、镍、钯或它们的组合形成。可选择执行回流工艺以使第三凸块结构52和连接件402相应连接。根据一些实施例，在产生的封装件500中，坝体结构60A与衬底400接触。坝体结构60A成为障碍物以控制组件300与衬底400之间的间隙，从而防止回流工艺过程中的凸块桥接和/或回流冷却工艺过程中由于中介层芯片10A与衬底400之间的CTE（热膨胀系数）不匹配和翘曲不匹配而导致的凸块破裂。与使环氧树脂坝体分布在表面状况有偏差的封装衬底上的方法相比，本发明在将晶圆式组件200连接至衬底400之前将坝体结构60设置在晶圆式组件200的介电层上，使得坝体结构的高度和宽度更容易被控制并且显著提高了坝体形成的产量和稳定性。
图10为示出了根据其它实施例的在晶圆上管芯组件的背面上形成的坝体结构的顶视图。除非另有说明，这些实施例中的参考数字代表图4至图7所述实施例中类似的元件。将坝体结构70设置在相邻的芯片区10的拐角区10C上，从而在晶圆上管芯组件200的背面上形成了坝体结构70的栅格阵列。在一个实施例中，宽度（Wd）等于第三凸块结构52的宽度（Wb）。在一些实施例中，宽度（Wd）大于或小于第三凸块结构52的宽度（Wb）。坝体结构70的高度与第三凸块结构52的高度（Hb）相同或比其略小。在一个实施例中，坝体结构70由聚合物材料形成。例如，可使用诸如环氧树脂或树脂等流体状的液体材料。可执行固化步骤以使坝体结构70固化。
图11为示出了从图10所示的晶圆上管芯组件200中分离出的单个组件300”的截面图。除非另有说明，这些实施例中的参考数字代表图7所示实施例中类似的元件。对划线区12执行切割工艺之后，分离出多个中介层上管芯组件300”。在至少一个实施例中，单个组件300”包括接合至中介层芯片10A的管芯40，而中介层芯片10A用于将管芯40连接至另一衬底，单个组件300”还包括位于中介层芯片10A的背面拐角区10C上的至少一个坝体结构70。
图12为示出了根据各个实施例的在衬底400上形成中介层上管芯组件300”的截面图。除非另有说明，这些实施例中的参考数字代表图9中所示实施例中类似的元件。中介层上管芯组件300”附接至衬底400以形成半导体封装件500”。中介层上管芯组件300”通过将第三凸块结构52连接至衬底400上的连接件402而电耦合至衬底400。可选地，执行回流工艺以使第三凸块结构52和连接器402相应连接。根据一些实施例，在产生的封装件500”中，坝体结构70与衬底400接触。坝体结构70成为障碍物以控制组件300”与衬底400之间的间隙。
根据一些实施例，一种半导体封装件，包括：中介层芯片，其具有正面、背面和位于背面上的由中介层芯片的第一拐角边缘和第二拐角边缘限定的拐角区；管芯，接合至中介层芯片的正面；以及至少一个坝体结构，位于中介层芯片的背面的拐角区上。坝体结构包括与中介层芯片的第一拐角边缘和第二拐角边缘的至少其中一个对齐的边缘。
根据一些实施例，形成一种组件的方法，包括：提供具有正面、背面和通过划线区被分隔开的多个芯片区的晶圆；将管芯接合至晶圆的正面以形成晶圆上管芯组件；在晶圆背面的划线区的交叉部分上形成多个坝体结构；以及对划线区执行切割工艺以将晶圆上管芯组件分成多个单个组件。
根据一些实施例，一种半导体封装件，包括：中介层芯片，其具有正面、背面和位于背面且由中介层芯片成对的第一拐角边缘和第二拐角边缘限定的四个拐角区；管芯，接合至中介层芯片的正面；聚合物层，形成在中介层芯片的正面并且围绕管芯；四个聚合物坝体结构，位于中介层芯片的背面的四个拐角区上，其中四个聚合物坝体结构中的每一个均包括与中介层芯片的第一拐角边缘对齐的第一边缘和与中介层芯片的第二拐角边缘对齐的第二边缘；以及衬底，接合至中介层芯片的背面，其中四个聚合物坝体结构设置在衬底与中介层芯片之间。
尽管已经通过参考本发明的示例性实施例详细地示出和描述了本发明，但本领域的技术人员应当理解本发明有很多的变型实施例。虽然详细描述了实施例及其特征，但是应该理解，在不背离本发明的精神和范围的情况下，在此可作出各种变化、替代和改变。
上述方法实施例示出了示例性步骤，但并非要求按说明的顺序执行。根据本公开的实施例的精神和范围，视情况而定，步骤可以增加、替代、改变顺序和/或消除。结合不同权利要求和/或不同实施例的实施例都在本发明的范围内，而这在本领域技术人员阅读说明书之后将会显而易见。

Claims (10)

1.一种半导体封装件，包括：
中介层芯片，具有正面、背面和位于所述背面并且由所述中介层芯片的第一拐角边缘和第二拐角边缘限定的拐角区；
管芯，接合至所述中介层芯片的正面；以及
至少一个坝体结构，位于所述中介层芯片的背面的拐角区上；
其中，所述坝体结构包括与所述中介层芯片的第一拐角边缘和第二拐角边缘中的至少一个边缘对齐的边缘。
2.根据权利要求1所述的半导体封装件，还包括：位于所述中介层芯片的正面上并且围绕所述管芯的聚合物层。
3.根据权利要求2所述的半导体封装件，其中，所述聚合物层包括与所述坝体结构的边缘对齐的外边缘。
4.根据权利要求1所述的半导体封装件，其中，所述坝体结构包括聚合物。
5.根据权利要求1所述的半导体封装件，还包括：位于所述中介层芯片的背面上的多个凸块结构。
6.根据权利要求1所述的半导体封装件，其中，所述中介层芯片包括：
半导体衬底，具有第一面和与所述第一面相对的第二面；
衬底通孔，穿过所述半导体衬底；
互连结构，形成于所述半导体衬底的第一面上并且电连接至所述衬底通孔；以及
多个凸块结构，形成于所述半导体衬底的第二面上并且电连接至所述衬底通孔。
7.一种形成组件的方法，包括：
提供具有正面和背面的晶圆，所述晶圆包括被划线区分隔的多个芯片区；
将管芯接合至所述晶圆的正面以形成晶圆上管芯组件；
在所述晶圆的背面上的所述划线区的交叉部分上形成多个坝体结构；以及
对所述划线区执行切割工艺以将所述晶圆上管芯组件分离成多个单个组件。
8.根据权利要求7所述的方法，其中，所述多个芯片区中的每一个均包括与所述划线区的交叉部分邻近的四个拐角区，并且所述坝体结构被形成为延伸至所述四个拐角区。
9.根据权利要求7所述的方法，其中，所述晶圆包括：
半导体衬底，具有第一面和与所述第一面相对的第二面；
衬底通孔，穿过所述半导体衬底；
互连结构，形成在所述半导体衬底的第一面上并且电连接至所述衬底通孔；以及
多个凸块结构，形成在所述半导体衬底的第二面上并且电连接至所述衬底通孔。
10.一种半导体封装件，包括：
中介层芯片，具有正面、背面和位于所述背面上并且由所述中介层芯片的成对的第一拐角边缘和成对的第二拐角边缘限定的四个拐角区；
管芯，接合至所述中介层芯片的正面；
聚合物层，形成在所述中介层芯片的正面上并且围绕所述管芯；
四个聚合物坝体结构，位于所述中介层芯片背面的所述四个拐角区上，所述四个聚合物坝体结构中的每一个均包括与所述中介层芯片的第一拐角边缘对齐的第一边缘和与所述中介层芯片的第二拐角边缘对齐的第二边缘；以及
衬底，接合至所述中介层芯片的背面，所述四个聚合物坝体结构位于所述衬底与所述中介层芯片之间。
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