CN109509783A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109509783A
CN109509783A CN201810181613.8A CN201810181613A CN109509783A CN 109509783 A CN109509783 A CN 109509783A CN 201810181613 A CN201810181613 A CN 201810181613A CN 109509783 A CN109509783 A CN 109509783A
Authority
CN
China
Prior art keywords
region
semiconductor region
semiconductor
type
type impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201810181613.8A
Other languages
English (en)
Chinese (zh)
Inventor
小野升太郎
大田浩史
条尚生
一条尚生
山下浩明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Publication of CN109509783A publication Critical patent/CN109509783A/zh
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
CN201810181613.8A 2017-09-15 2018-03-06 半导体装置 Withdrawn CN109509783A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-178413 2017-09-15
JP2017178413A JP2019054169A (ja) 2017-09-15 2017-09-15 半導体装置

Publications (1)

Publication Number Publication Date
CN109509783A true CN109509783A (zh) 2019-03-22

Family

ID=61256686

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810181613.8A Withdrawn CN109509783A (zh) 2017-09-15 2018-03-06 半导体装置

Country Status (4)

Country Link
US (2) US20190088738A1 (https=)
EP (1) EP3457440A1 (https=)
JP (1) JP2019054169A (https=)
CN (1) CN109509783A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112993007A (zh) * 2019-12-13 2021-06-18 南通尚阳通集成电路有限公司 超结结构及超结器件

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6981890B2 (ja) * 2018-01-29 2021-12-17 ルネサスエレクトロニクス株式会社 半導体装置
CN115566038B (zh) * 2021-07-01 2025-09-26 深圳尚阳通科技股份有限公司 超结器件及其制造方法
CN116137283B (zh) * 2021-11-17 2025-09-12 苏州东微半导体股份有限公司 半导体超结功率器件
JP7793067B2 (ja) * 2022-09-05 2025-12-26 三菱電機株式会社 半導体装置、半導体装置の制御方法、および半導体装置の製造方法
JP2024103227A (ja) * 2023-01-20 2024-08-01 株式会社デンソー ダイオード、ダイオードを内蔵する電界効果トランジスタ、及びダイオードの製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260984A (ja) * 1999-03-10 2000-09-22 Toshiba Corp 高耐圧半導体素子
US20040016959A1 (en) * 2001-10-16 2004-01-29 Hitoshi Yamaguchi Semiconductor device and its manufacturing method
US20090273031A1 (en) * 2008-05-02 2009-11-05 Kabushiki Kaisha Toshiba Semiconductor device
CN101794816A (zh) * 2009-01-23 2010-08-04 株式会社东芝 半导体器件
CN102804386A (zh) * 2010-01-29 2012-11-28 富士电机株式会社 半导体器件
CN104241376A (zh) * 2014-09-01 2014-12-24 矽力杰半导体技术(杭州)有限公司 超结结构及其制备方法和半导体器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3731520B2 (ja) * 2001-10-03 2006-01-05 富士電機デバイステクノロジー株式会社 半導体装置及びその製造方法
JP4194890B2 (ja) * 2003-06-24 2008-12-10 株式会社豊田中央研究所 半導体装置とその製造方法
JP4967236B2 (ja) * 2004-08-04 2012-07-04 富士電機株式会社 半導体素子
JP4768259B2 (ja) * 2004-12-21 2011-09-07 株式会社東芝 電力用半導体装置
JP2007300034A (ja) * 2006-05-02 2007-11-15 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP4696986B2 (ja) * 2006-03-17 2011-06-08 トヨタ自動車株式会社 スーパージャンクション構造を有する半導体装置の製造方法
JP4564509B2 (ja) * 2007-04-05 2010-10-20 株式会社東芝 電力用半導体素子
JP6369173B2 (ja) * 2014-04-17 2018-08-08 富士電機株式会社 縦型半導体装置およびその製造方法
DE102016113129B3 (de) * 2016-07-15 2017-11-09 Infineon Technologies Ag Halbleitervorrichtung, die eine Superjunction-Struktur in einem SiC-Halbleiterkörper enthält

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260984A (ja) * 1999-03-10 2000-09-22 Toshiba Corp 高耐圧半導体素子
US20040016959A1 (en) * 2001-10-16 2004-01-29 Hitoshi Yamaguchi Semiconductor device and its manufacturing method
US20090273031A1 (en) * 2008-05-02 2009-11-05 Kabushiki Kaisha Toshiba Semiconductor device
CN101794816A (zh) * 2009-01-23 2010-08-04 株式会社东芝 半导体器件
CN102804386A (zh) * 2010-01-29 2012-11-28 富士电机株式会社 半导体器件
CN104241376A (zh) * 2014-09-01 2014-12-24 矽力杰半导体技术(杭州)有限公司 超结结构及其制备方法和半导体器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112993007A (zh) * 2019-12-13 2021-06-18 南通尚阳通集成电路有限公司 超结结构及超结器件

Also Published As

Publication number Publication date
US20190088738A1 (en) 2019-03-21
EP3457440A1 (en) 2019-03-20
JP2019054169A (ja) 2019-04-04
US20200119142A1 (en) 2020-04-16

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Application publication date: 20190322