CN109473392A - 晶片的加工方法 - Google Patents
晶片的加工方法 Download PDFInfo
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- 238000003672 processing method Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 72
- 239000003566 sealing material Substances 0.000 claims abstract description 48
- 230000011218 segmentation Effects 0.000 claims abstract description 36
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 21
- 238000007789 sealing Methods 0.000 claims abstract description 17
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 230000035699 permeability Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 3
- 229910001651 emery Inorganic materials 0.000 description 10
- 239000006229 carbon black Substances 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L21/561—Batch processing
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- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
- B28D5/02—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- Power Engineering (AREA)
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- Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
提供晶片的加工方法,该方法包含:第1切削槽形成工序,从晶片的正面侧沿着分割预定线通过第1切削刀具形成深度相当于完工厚度的第1切削槽;密封工序,利用密封材料将晶片的正面密封;对准工序,对晶片的正面侧进行拍摄而检测对准标记,根据对准标记检测待切削的分割预定线;第2切削槽形成工序,从晶片的正面侧沿着分割预定线通过具有比第1切削刀具的第1厚度小的第2厚度的第2切削刀具在第1切削槽的密封材料中形成深度相当于完工厚度的第2切削槽;保护部件粘贴工序,在晶片的正面上粘贴保护部件;和分割工序,从晶片的背面侧将晶片磨削至完工厚度而使第2切削槽露出,将晶片分割成正面和4个侧面被密封材料围绕的各个器件芯片。
Description
技术领域
本发明涉及晶片的加工方法,对晶片进行加工而形成5S模制封装。
背景技术
作为实现LSI或NAND型闪存等各种器件的小型化和高密度安装化的构造,例如,对器件芯片按照芯片尺寸进行封装而得的芯片尺寸封装(CSP)已被用于实际的使用中,并被广泛地使用于移动电话、智能手机等。此外,近年来,在该CSP中,开发并实用化了不仅利用密封材料将芯片的正面密封还将整个侧面密封的CSP,即,所谓的5S模制封装。
以往的5S模制封装是通过以下工序制作的。
(1)在半导体晶片(以下,有时大致称为晶片)的正面上形成被称为器件(电路)和凸块的外部连接端子。
(2)从晶片的正面侧沿着分割预定线对晶片进行切削,形成深度相当于器件芯片的完工厚度的切削槽。
(3)利用含有炭黑的密封材料将晶片的正面密封。
(4)将晶片的背面侧磨削到器件芯片的完工厚度而使切削槽中的密封材料露出。
(5)由于晶片的正面被含有炭黑的密封材料密封,所以将晶片正面的外周部分的密封材料去除而使目标图案等对准标记露出,实施根据该对准标记来检测待切削的分割预定线的对准。
(6)根据对准,从晶片的正面侧沿着分割预定线对晶片进行切削,从而分割成正面和整个侧面被密封材料密封的5S模制封装。
如上述那样,由于晶片的正面被包含炭黑的密封材料密封,所以形成于晶片正面的器件等完全无法用肉眼看到。为了解决该问题以便能够进行对准,如上述(5)所记载的那样,本申请人开发出如下的技术:将晶片正面的密封材料的外周部分去除而使目标图案等对准标记露出,根据该对准标记来检测待切削的分割预定线,从而执行对准(参照日本特开2013-074021号公报和日本特开2016-015438号公报)。
专利文献1:日本特开2013-074021号公报
专利文献2:日本特开2016-015438号公报
然而,在上述公开公报所记载的对准方法中,需要代替切割用的切削刀具而将边缘修整用的宽度较宽的切削刀具安装于主轴从而将晶片的外周部分的密封材料去除的工序,切削刀具的更换和通过边缘修整来去除外周部分的密封材料需要花费时间和劳力,存在生产性较差的问题。
发明内容
本发明是鉴于该点而完成的,其目的在于,提供能够透过包覆于晶片正面的包含炭黑的密封材料来实施对准工序的晶片的加工方法。
根据本发明,提供晶片的加工方法,该晶片在由交叉形成的多条分割预定线划分的正面的各区域内分别形成有器件,该器件具有多个凸块,该晶片的加工方法的特征在于,具有如下的工序:第1切削槽形成工序,从该晶片的正面侧沿着该分割预定线通过具有第1厚度的第1切削刀具来形成深度相当于器件芯片的完工厚度的第1切削槽;密封工序,在实施了该第1切削槽形成工序之后,利用密封材料将该晶片的包含该第1切削槽的正面密封;对准工序,在实施了该密封工序之后,通过红外线拍摄构件从该晶片的正面侧透过该密封材料对晶片的正面侧进行拍摄而检测对准标记,根据该对准标记来检测待切削的该分割预定线;第2切削槽形成工序,在实施了该对准工序之后,从该晶片的正面侧沿着该分割预定线通过具有比该第1切削刀具的该第1厚度小的第2厚度的第2切削刀具在该第1切削槽的该密封材料中形成深度相当于器件芯片的完工厚度的第2切削槽;保护部件粘贴工序,在实施了该第2切削槽形成工序之后,在该晶片的正面上粘贴保护部件;以及分割工序,在实施了该保护部件粘贴工序之后,从该晶片的背面侧将该晶片磨削至该器件芯片的完工厚度而使该第2切削槽露出,将该晶片分割成正面和4个侧面被该密封材料围绕的各个该器件芯片,在该密封工序中,通过具有使该红外线拍摄构件所接受的红外线透过的透过性的密封材料对该晶片的正面进行密封。
优选在对准工序中使用的红外线拍摄元件包含InGaAs拍摄元件。
根据本发明的晶片的加工方法,利用使红外线拍摄构件所接受的红外线透过的密封材料将晶片的正面密封,通过红外线拍摄构件透过密封材料来检测形成于晶片的对准标记,能够根据对准标记来实施对准,因此能够简单地实施对准工序,无需如以往那样将晶片的正面的外周部分的密封材料去除。
因此,能够从晶片的正面侧沿着在形成为深度相当于器件芯片的完工厚度的第1切削槽内所填充的密封材料形成第2切削槽,之后从晶片的背面侧将晶片磨削至器件芯片的完工厚度而使第2切削槽露出,由此,能够分割成正面和4个侧面被密封材料密封的各个器件芯片。
附图说明
图1是示出半导体晶片的立体图。
图2是示出第1切削槽形成工序的立体图。
图3是示出密封工序的立体图。
图4是示出对准工序的剖视图。
图5的(A)是示出第2切削槽形成工序的剖视图,图5的(B)是实施了第2切削槽形成工序之后的晶片的局部放大剖视图。
图6的(A)是示出分割工序的局部剖视侧视图,图6的(B)是器件芯片的放大剖视图。
标号说明
10:切削单元;11:半导体晶片;13:分割预定线;14、14A:切削刀具;15:器件;16:对准单元;17:电极凸块;18:拍摄单元;20:密封材料;23:第1切削槽;25:第2切削槽;26:磨削单元;27:器件芯片;34:磨削磨轮;38:磨削磨具。
具体实施方式
以下,参照附图对本发明的实施方式进行详细说明。参照图1,示出了适合通过本发明的加工方法来加工的半导体晶片(以下,有时简称为晶片)11的正面侧立体图。
在半导体晶片11的正面11a上呈格子状形成有多条分割预定线(间隔道)13。在由垂直的分割预定线13划分出的各区域内形成有IC、LSI等器件15。
在各器件15的正面上具有多个电极凸块(以下,有时简称为凸块)17,晶片11在其正面上具有:器件区域19,其形成有分别具有多个凸块17的多个器件15;以及外周剩余区域21,其围绕器件区域19。
在本发明实施方式的晶片的加工方法中,首先,作为第1工序,实施第1切削槽形成工序,从晶片11的正面侧沿着分割预定线13通过具有第1厚度的第1切削刀具来形成深度相当于器件芯片的完工厚度的第1切削槽。参照图2对该第1切削槽形成工序进行说明。
切削单元10具有:切削刀具14,其以能够装卸的方式安装于主轴12的前端部;以及对准单元16,其具有拍摄构件(拍摄单元)18。拍摄单元18除了具有利用可见光进行拍摄的显微镜和照相机之外,还具有对红外线图像进行拍摄的红外线拍摄元件。在本实施方式中,采用了InGaAs拍摄元件作为红外线拍摄元件。
在实施第1切削槽形成工序之前,首先,实施如下对准:拍摄单元18利用可见光来拍摄晶片11的正面,检测形成于各器件15的目标图案等对准标记,根据该对准标记来检测待切削的分割预定线13。
在实施对准之后,实施第1切削槽形成工序,使在箭头R1方向上高速旋转的切削刀具(第1切削刀具)14从晶片11的正面11a侧沿着分割预定线13按照相当于器件芯片的完工厚度的深度切入,并对吸引保持着晶片11的未图示的卡盘工作台在箭头X1方向上进行加工进给,从而沿着分割预定线13形成第1切削槽23。
一边按照分割预定线13的间距在与加工进给方向X1垂直的方向上将切削单元10进行分度进给,一边沿着在第1方向上延伸的分割预定线13依次实施该第1切削槽形成工序。
接着,在使未图示的卡盘工作台旋转90°之后,沿着在与第1方向垂直的第2方向上延伸的分割预定线13依次实施同样的第1切削槽形成工序。
在实施了第1切削槽形成工序之后,实施密封工序,如图3所示,向晶片11的正面11a涂布密封材料20,利用密封材料将包含第1切削槽23的晶片11的正面11a密封。由于密封材料20具有流动性,所以当实施密封工序时,密封材料20被填充到第1切削槽23中。
作为密封材料20,其组成按质量%包含环氧树脂或环氧树脂+酚醛树脂10.3%、二氧化硅填料85.3%、炭黑0.1~0.2%、其他成分4.2~4.3%。作为其他成分,例如,包含金属氢氧化物、三氧化锑、二氧化硅等。
当利用这种组成的密封材料20来包覆晶片11的正面11a从而将晶片11的正面11a密封时,密封材料20因包含在密封材料20中的极少量的炭黑而呈黑色,因此通常很难透过密封材料20看到晶片11的正面11a。
这里,向密封材料20中混入炭黑主要是为了防止器件15的静电破坏,目前在市场上还没有销售不含炭黑的密封材料。
密封材料20的涂布方法没有特别地限定,但优选将密封材料20涂布到凸块17的高度为止,接着利用蚀刻对密封材料20进行蚀刻,使凸块17冒出。
在实施了密封工序之后,实施如下的对准工序:从晶片11的正面11a侧通过红外线拍摄构件以透过密封材料20的方式对晶片11的正面11a进行拍摄,检测形成于晶片11的正面的至少两个目标图案等对准标记,根据这些对准标记来检测待切削的分割预定线13。
参照图4对该对准工序进行详细说明。在实施对准工序之前,将晶片11的背面11b侧粘贴在外周部安装于环状框架F的划片带T上。
在对准工序中,如图4所示,隔着划片带T利用切削装置的卡盘工作台40对晶片11进行吸引保持,使将晶片11的正面11a密封的密封材料20向上方露出。然后,利用夹具42对环状框架F进行夹持而固定。
在对准工序中,利用拍摄单元18的红外线拍摄元件对晶片11的正面11a进行拍摄。密封材料20由使拍摄单元18的红外线拍摄元件所接受的红外线透过的密封材料构成,因此,能够通过红外线拍摄元件来检测形成于晶片11的正面11a的至少两个目标图案等对准标记。
作为红外线拍摄元件,优选采用灵敏度较高的InGaAs拍摄元件。优选拍摄单元18具有能够对曝光时间等进行调整的曝光器件(exposure)。
接着,使卡盘工作台40进行θ旋转以便使连接这些对准标记而得的直线与加工进给方向平行,然后使图2所示的切削单元10按照对准标记与分割预定线13的中心之间的距离在与加工进给方向X1垂直的方向上移动,从而检测出待切削的分割预定线13。
在实施了对准工序之后,实施第2切削槽形成工序,如图5的(A)所示,从晶片11的正面11a侧沿着分割预定线13通过具有比第1切削刀具14的宽度小的宽度的第2切削刀具14A在正面11a被密封材料20密封的晶片11上形成深度相当于器件芯片的完工厚度的第2切削槽25。
当沿着在第1方向上延伸的分割预定线13依次实施了该第2切削槽形成工序之后,使卡盘工作台40旋转90°,沿着在与第1方向垂直的第2方向上延伸的分割预定线13依次实施该第2切削槽形成工序。
在实施了第2切削槽形成工序之后,实施保护部件粘贴工序,在晶片11的正面11a上粘贴保护带等保护部件22。在实施了保护部件粘贴工序之后,实施分割工序,从晶片11的背面11b侧将晶片11磨削至器件芯片的完工厚度而使第2切削槽25露出,将晶片11分割成正面和4个侧面被密封材料20密封的各个器件芯片27。
参照图6对该分割工序进行说明。利用磨削装置的卡盘工作台24隔着粘贴于晶片11的正面11a的正面保护带等保护部件22对晶片11进行吸引保持。
磨削单元26包含:主轴30,其以能够旋转的方式收纳在主轴外壳28中,通过未图示的电动机来进行旋转驱动;磨轮安装座32,其固定于主轴30的前端;以及磨削磨轮34,其以能够装卸的方式安装于磨轮安装座32。磨削磨轮34由环状的磨轮基台36和粘固在磨轮基台36的下端外周的多个磨削磨具38构成。
在分割工序中,一边使卡盘工作台24在箭头a所示的方向上例如按照300rpm进行旋转,一边使磨削磨轮34在箭头b所示的方向上例如按照6000rpm进行旋转,并且对未图示的磨削单元进给机构进行驱动而使磨削磨轮34的磨削磨具38与晶片11的背面11b接触。
然后,一边将磨削磨轮34按照规定的磨削进给速度向下方磨削进给规定的量,一边对晶片11的背面11b进行磨削。一边利用接触式或非接触式的厚度测量仪来测量晶片11的厚度,一边将晶片11磨削至规定的厚度例如100μm而使第2切削槽25露出,如图6的(B)所示,将晶片11分割成正面和4个侧面被密封材料20围绕的各个器件芯片27。
这样制造出的器件芯片27能够通过倒装芯片接合而安装在主板上,该倒装芯片接合将器件芯片27的正面背面反转而将凸块17与主板的导电焊盘连接。
Claims (2)
1.一种晶片的加工方法,该晶片在由交叉形成的多条分割预定线划分的正面的各区域内分别形成有器件,该器件具有多个凸块,
该晶片的加工方法的特征在于,具有如下的工序:
第1切削槽形成工序,从该晶片的正面侧沿着该分割预定线通过具有第1厚度的第1切削刀具来形成深度相当于器件芯片的完工厚度的第1切削槽;
密封工序,在实施了该第1切削槽形成工序之后,利用密封材料将该晶片的包含该第1切削槽的正面密封;
对准工序,在实施了该密封工序之后,通过红外线拍摄构件从该晶片的正面侧透过该密封材料对晶片的正面侧进行拍摄而检测对准标记,根据该对准标记来检测待切削的该分割预定线;
第2切削槽形成工序,在实施了该对准工序之后,从该晶片的正面侧沿着该分割预定线通过具有比该第1切削刀具的该第1厚度小的第2厚度的第2切削刀具在该第1切削槽中的该密封材料中形成深度相当于器件芯片的完工厚度的第2切削槽;
保护部件粘贴工序,在实施了该第2切削槽形成工序之后,在该晶片的正面上粘贴保护部件;以及
分割工序,在实施了该保护部件粘贴工序之后,从该晶片的背面侧将该晶片磨削至该器件芯片的完工厚度而使该第2切削槽露出,将该晶片分割成正面和4个侧面被该密封材料围绕的各个该器件芯片,
在该密封工序中,通过具有使该红外线拍摄构件所接受的红外线透过的透过性的密封材料对该晶片的正面进行密封。
2.根据权利要求1所述的晶片的加工方法,其中,
在该对准工序中使用的所述红外线拍摄构件包含InGaAs拍摄元件。
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