CN109346417A - 集成电路壳体 - Google Patents
集成电路壳体 Download PDFInfo
- Publication number
- CN109346417A CN109346417A CN201811144119.0A CN201811144119A CN109346417A CN 109346417 A CN109346417 A CN 109346417A CN 201811144119 A CN201811144119 A CN 201811144119A CN 109346417 A CN109346417 A CN 109346417A
- Authority
- CN
- China
- Prior art keywords
- contact portion
- carrier substrates
- integrated circuit
- forming part
- semiconductor body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 238000005266 casting Methods 0.000 claims abstract description 16
- 239000004020 conductor Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 4
- 229920000297 Rayon Polymers 0.000 claims description 3
- 239000012777 electrically insulating material Substances 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims description 2
- 238000007906 compression Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000010276 construction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000004512 die casting Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Abstract
本发明涉及具有一个半导体主体的集成电路壳体(IC‑壳体),其中半导体主体具有一个单片的集成电路及至少两个金属接触面,及该集成电路借助导体线路与两个电接触面连接以及半导体主体被设置在一个载体基底上,其中所述载体基底在上侧上具有盆槽状成型部,并且,所述半导体主体设置在该盆槽状成型部的底部区域中且与该载体基底力锁合地连接,及该载体基底具有至少两个连接接触部及这两个连接接触部与两个接触面连接以及半导体主体与载体基底的盆槽状成型部被一个浇注质量体覆盖,其中浇注质量体构成IC‑壳体的一部分及两个连接接触部的各一区段穿过IC壳体,其中这两个连接接触部设置在载体基底上,所述连接接触部包括导体线路区段,其中,所述导体线路区段延伸越过盆槽状成型部的边缘及在所述载体基底的盆槽状成型部外部的区域中的每个连接接触部与位于相应的连接接触部下面的载体基底构成一个孔状构形,其中相应的孔状构形被构成穿通接触部,以便提供与另一电构件的电连接。
Description
本申请是申请日为2016年1月11日、申请号为201610014083.9和发明名称为“集成电路壳体”的发明专利申请的分案申请。
技术领域
本发明涉及一种IC-壳体(集成电路壳体)。
背景技术
由DE 10 2007 032 142 A1公知了一种电子模块。由Andreas Veigel 等人的“压入技术–发展,应用,鉴定”第1版,Eugen G.Leuze出版社(Bad Saulgau)2009,ISBN 978-3-87480-252-9公知了一种接触装置。
发明内容
在此背景下,本发明的任务在于:提出一种装置,该装置对现有技术作出进一步发展。
该任务通过具有权利要求1所述特征的IC-壳体来解决。本发明的有利构型是从属权利要求的主题。
根据本发明的主题提供了一种具有半导体主体的集成电路壳体(IC-壳体),其中,半导体主体具有单片的集成电路及至少两个金属接触面,并且,该集成电路借助于导体线路与上述两个电接触面接线连接,并且,半导体主体被设置在载体基底上,其中所述载体基底在上侧上具有盆槽状成型部,并且,所述半导体主体设置在该盆槽状成型部的底部区域中并且与该载体基底力锁合地连接,并且,该载体基底具有至少两个连接接触部,并且,这两个连接接触部与上述两个接触面接线连接,并且,半导体主体与载体基底的盆槽状成型部被浇注质量体覆盖,其中,浇注质量体构成IC-壳体的一部分,并且,上述两个连接接触部的各一区段穿过IC壳体,其中,这两个连接接触部设置在载体基底上,所述连接接触部(80,90)包括导体线路区段,其中,所述导体线路区段延伸越过盆槽状成型部的边缘并且,在所述载体基底(50)的盆槽状成型部外部的区域中的每个连接接触部与位于相应的连接接触部下方的载体基底构成孔状成型部,其中,相应的孔状成型部构成穿通接触部,以便提供与另一电构件的电连接。
注意的是,概念“孔状成型部”应表示为载体基底中的贯穿开口,并且,该开口中的壁是金属的并且可导电,以便由此构造成导电的穿通接触部。特别是,穿通接触部构造成套筒形式。
可以理解,优选的是,该IC壳体由浇注质量体和载体基底构成,可替换并也优选的是,该壳体仅借助于浇注质量体构成,换句话说,位于内部的构件完全被浇注质量体包围。
可以理解,在借助于浇注质量体构成IC-壳体之前,载体基底的承载能力足以接收所述连接接触部及所述穿通接触部。应当指出,对于载体基底也惯用“引线框架(Lead-frame)”的名称,尤其是如果载体基底由一种金属或由多个金属条组成的话。
根据本发明的装置的优点在于,IC-壳体借助于该IC-壳体直接构成的穿通接触部可直接地与另一构件电接线连接。可取消将IC-壳体安装在承载印刷电路板上,其中,该承载印刷电路板包含穿通接触部。换句话说,借助根据本发明的装置可节省了连接平面,其方式是,(优选借助于压入销)到IC-壳体的穿通接触部中就能够与上级系统(例如插接器或者电缆)直接地连接。由此能够提高利润及降低接合成本。
在一个改进方案中,载体基底包括电绝缘的材料或者由电绝缘材料制成。优选作为载体基底材料的是:塑料连接物或者金属-塑料连接物,例如呈压铸件(Spritzgussteilen)形式的所谓“模塑互连器(molded interconnect devices)”。在这里,连接接触部被构成为载体基底上的金属条。
在一个可替代的金属的载体基底的实施形式中,将金属条构造在载体基底的表面上成为多余,在该实施形式中,连接接触部本身已经由金属的、然而相互隔离的各个条构成。
优选的是,穿通接触部优选具有圆形的横截面。优选的还在于,穿通接触部的长度与直径之间的纵横比至少大于等于1。
既能够将销压入到穿通接触部中也能够将销焊接到穿通接触部中。研究已表明:有利的是,在穿通接触部中,在孔内侧上构成有金属表面,其中,该金属表面被构成外接触部的一部分并且优选与外接触部一件式连接。
在一个变换的实施形式中,穿通接触部此外优选地力锁合及材料锁合地与载体基底连接。由此可得到特别牢固且低欧姆电阻的连接。
在一个实施形式中,接触面以传导粘胶或者以接合线材或者借助于焊接连接或者借助于烧结或者借助于热压缩接合与连接接触部进行电接线连接。
优选的还在于,在载体基底上设有与半导体主体间隔开的另一电子构件,并且,上述两个构件在一个方法步骤中被同一浇注质量体覆盖。针对上述两个构造元件的实例是霍尔传感器,该霍尔传感器或是侧向地或是叠堆状地设置在IC-壳体内部。
在一个非本发明的方案中,载体基底被构成平板。
优选地,所有的穿通接触部都被构成在载体基底的边缘区域中。在一个变换的实施形式中,不仅在载体基底的上面而且在其下面设有一个或多个半导体主体和/或一个或多个电子构件。由此可以用简单且成本上有利的方式来实现多芯片的技术方案,而无需承载印刷电路板()。
附图说明
以下将参照附图来详细地解释本发明。在此,相同的部件用相同的标号示出。所示的实施形式极其简化地图示,也就是说,间距及横向与竖直的延伸长度不是按比例的,并且,只要无另外的说明,也不具有可相互推导的几何关系。附图中示出:
图1:根据非本发明的IC-壳体的实施形式的横截面图,
图2:根据本发明的IC-壳体的第一实施形式的横截面图,
图3:根据本发明的IC-壳体的第二实施形式的横截面图,
图4:根据本发明的IC-壳体的第三实施形式的一个横截面图,
图5a:根据另一非本发明的IC-壳体的实施形式的横截面图,
图5b:图5a中所示的根据非本发明的IC-壳体的实施形式的沿线A-A的俯视图。
具体实施方式
图1的附图示出非本发明的实施形式的概要示图,IC-壳体10中具有半导体主体20,该半导体主体20具有上侧22及下侧24。半导体主体20具有未示出的单片集成电路,该单片集成电路具有第一金属接触面30及第二金属接触面40。这两个接触面30及40被构成在半导体主体20的上侧22上。
该集成电路借助未示出的导体线路与这两个电接触面30及40接线连接。此外设有载体基底50,该载体基底50具有上侧52及下侧54。半导体主体20以其下侧24在载体基底50的上侧52上借助于粘性连接部60与载体基底50力锁合地连接。粘性连接部60优选被构成双面粘性的薄膜。载体基底50具有第一金属面70及第一连接接触部80及第二连接接触部90。这两个连接接触部80及90包括穿过载体基底50构成的孔状第一穿通接触部100及穿过载体基底50构成的孔状第二穿通接触部110。这两个穿通接触部100及110具有圆形的横截面并且被构成在载体基底50的边缘区域中。
第一电子构件118与第一金属面70并且与第一连接接触部80接线连接。第一连接接触部80与第一穿通接触部100接线连接,并且,第二连接接触部90与第二穿通接触部110接线连接;其中,在上述两个穿通接触部100及110的内侧上构成相应的连接接触部80及90。在此情况下,在上述两个穿通接触部中,上述两个连接接触部80及90在载体基底50的上侧52上构成边缘面120并且在载体基底50的下侧54上构成边缘面130。这两个边缘面120及130与内侧135分别与相应的连接接触部80及90构成一体。
上述两个接触面30以及40分别借助于接合线材150与第二连接接触部90以及与第一连接接触部80接线连接。在此情况下,第一接触面40与第一金属面70接线连接。第一构件118与第一金属面70以及与第一连接接触部80接线连接。换句话说,第二接触面40与第一金属面70以及第一构件118以及第一连接接触部80构成串联电路。在载体基底50的整个上侧52上构造有浇注质量体200,从而还使得接合线材150、半导体主体20以及第一电子构件118被浇注质量体200覆盖或包围。在载体基底50的下侧54上以及在载体基底50的上侧52上,穿通接触部100及110不具有浇注质量体200,以确保与其它组件的电接触。此外,作为组件还包括有插接连接部分。载体基底50板状地由一种电绝缘材料优选一体地构成。该板优选具有小于2mm的厚度,最优选具有小于0.5mm的厚度。此外优选地,IC-壳体10具有方体的形状。
在图2中示出根据本发明的IC-壳体10的第一实施形式的横截面图。以下仅描述相对于图1中所示的非本发明实施形式的区别。载体基底50在上侧52上(优选居中地)具有盆槽状成型部300,该盆槽状成型部300具有底部区域310。在尤其被构成平面的底部区域310中,半导体主体20与电子构件118并排地布置。在这里,具有半导体主体20的上述两个接触面30及40的上侧22朝着底部区域310的方向指向。上述两个接触面30及40与第二连接接触部90以及与第一连接接触部80接线连接。这两个连接接触部70及80具有导体线路区段,其中,这些导体线路区段在盆槽的边缘上延伸至第一连接接触部100以及延伸至第二连接接触部110并且分别与所配属的连接接触部100及110接线连接。在这里,仅是盆槽被填充有浇注质量体200,也就是说,载体基底50的剩余上侧52以及载体基底50的下侧54不具有浇注质量体。
在图3中示出根据本发明的IC-壳体10的第二实施形式的横截面图。以下仅描述相对于图2中所示的第一实施形式的区别。在具有底部区域310的盆槽状成型部300中,在第一半导体主体20上以粘性层405设置了另一半导体主体400,其中,第二半导体主体400借助于接合线材150与连接接触部100及110接线连接。
在图4中示出根据本发明的IC-壳体10的第三实施形式的横截面图。以下仅描述相对于图2中所示的第一实施形式的区别。第二半导体主体400借助于传导粘胶被设置在载体基底50的下侧54上。此外,在下侧54上,在第二半导体主体400旁边设置有第二电子构件410。在下侧54上,除了穿通接触部100及110外,该载体基底50被浇注质量体200覆盖,从而使得构件400及410被浇注质量体200覆盖。
在图5a中示出根据另一非本发明的IC-壳体10的实施形式的沿线A-A的横截面图。以下仅描述相对于图1中所示的非本发明实施形式的区别。更确切地说,载体基底50是多件式并由一种金属构成,尤其是,第一连接接触部80设置在载体基底50的单独的件500上。在该单独的件500(该单独的件500也可称为引脚,Pin)上构造有第一穿通接触部100。通过设置金属的方式,使接合线材可直接地与第一连接接触部80接线连接,而无需使第一连接接触部80构成穿通接触部100,110中的侧壁。
在上侧52上的浇注质量体200仅设置到第一半导体主体20及接合线材150的区域上,并且,同样地,浇注质量体200在下侧54上也设置到载体基底20的中央区域上。
在图5b中示出图5a中所示的根据非本发明的IC-壳体10的实施形式的俯视图。以下仅描述相对于图5a中所示的实施形式的区别。在半导体主体20的上侧22上,在此设有总共四个接触面30,40,501和502以及四个分立的连接接触部80,90,580和590,其中,所有的接触面30,40,501和502借助于所配属的接合线材150与各连接接触部80,90,580和590接线连接。所述单独的件500包括接触面80,580及590。穿通接触部100及110被设在用于每个引脚的各连接区中。在载体基底上构成有金属连接面将成为多余。
Claims (8)
1.一种集成电路(IC)壳体(10),其具有半导体主体(20),其中,所述半导体主体(20)具有单片的集成电路和至少两个金属接触面(30,40),并且,该集成电路借助于导体线路与这两个电接触面(30,40)接线连接,并且,所述半导体主体(20)设置在载体基底(50)上,其中所述载体基底(50)在上侧(52)上具有盆槽状成型部,并且,所述半导体主体(20)设置在该盆槽状成型部的底部区域中并且与该载体基底(50)力锁合地连接,并且,所述载体基底(50)具有至少两个连接接触部(80,90),并且,这两个连接接触部(80,90)与上述两个接触面(30,40)接线连接,并且,所述半导体主体(20)与所述载体基底(50)的盆槽状成型部借助浇注质量体(200)覆盖,其中,所述浇注质量体(200)构成所述集成电路壳体(10)的一部分,并且,上述两个连接接触部(80,90)的区段分别穿过所述集成电路壳体(10)的浇注质量体,其特征在于:
上述两个连接接触部(80,90)设置在所述载体基底(50)上,所述连接接触部(80,90)包括导体线路区段,其中,所述导体线路区段延伸越过盆槽状成型部的边缘并且,在所述载体基底(50)的盆槽状成型部外部的区域中的每个连接接触部(80,90)与位于相应的连接接触部(80,90)下方的载体基底(50)构成孔状成型部,其中,相应的孔状成型部被构成穿通接触部(100,110),以便提供与另一电构件的电连接。
2.根据权利要求1所述的集成电路壳体(10),其特征在于:所述载体基底(50)包括电绝缘材料或由电绝缘材料制成。
3.根据权利要求1或2所述的集成电路壳体(10),其特征在于:所述穿通接触部(100,110)具有该穿通接触部的长度与直径之间的纵横比,该纵横比大于等于1。
4.根据以上权利要求中一项或多项所述的集成电路壳体(10),其特征在于:所述穿通接触部(100,110)在孔内侧上构成有金属表面作为外接触部(80)的一部分并且与该外接触部(80)一体地连接。
5.根据以上权利要求中一项或多项所述的集成电路壳体(10),其特征在于:所述接触面(30,40)以传导粘胶或者以接合线材(150)或者借助于焊接连接或者借助于烧结或者借助于热压缩接合与所述连接接触部(80,90)电接线连接。
6.根据以上权利要求中一项或多项所述的集成电路壳体(10),其特征在于:在所述载体基底(50)上设置有另一电子构件(120),该另一电子构件与所述半导体主体(20)间隔开并且借助浇注质量体(200)覆盖。
7.根据以上权利要求中一项或多项所述的集成电路壳体(10),其特征在于:所述穿通接触部(100,110)构成在所述载体基底(50)的边缘区域中。
8.根据以上权利要求中一项或多项所述的集成电路壳体(10),其特征在于:所述孔状成型部构造为穿通的开口,并且,该开口在内侧上是金属的且可传导。
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DE102015000063.2A DE102015000063A1 (de) | 2015-01-12 | 2015-01-12 | IC-Gehäuse |
CN201610014083.9A CN105789166B (zh) | 2015-01-12 | 2016-01-11 | 集成电路壳体 |
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JP6840466B2 (ja) * | 2016-03-08 | 2021-03-10 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージ及び半導体パッケージの製造方法 |
DE102017006406B4 (de) * | 2017-07-07 | 2021-04-29 | Tdk-Micronas Gmbh | Gehäustes IC-Bauelement |
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EP3057129A1 (de) | 2016-08-17 |
US20160204055A1 (en) | 2016-07-14 |
US10026684B2 (en) | 2018-07-17 |
CN105789166B (zh) | 2018-11-09 |
DE102015000063A1 (de) | 2016-07-14 |
EP3133642A2 (de) | 2017-02-22 |
CN105789166A (zh) | 2016-07-20 |
US20180130729A1 (en) | 2018-05-10 |
EP3133642A3 (de) | 2017-04-12 |
EP3133643A2 (de) | 2017-02-22 |
US9893005B2 (en) | 2018-02-13 |
EP3133643A3 (de) | 2017-03-29 |
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