CN109285808A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN109285808A
CN109285808A CN201710595707.5A CN201710595707A CN109285808A CN 109285808 A CN109285808 A CN 109285808A CN 201710595707 A CN201710595707 A CN 201710595707A CN 109285808 A CN109285808 A CN 109285808A
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layer
gate structure
semiconductor devices
protective layer
medium layer
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201710595707.5A priority Critical patent/CN109285808A/zh
Priority to US16/040,100 priority patent/US10741689B2/en
Publication of CN109285808A publication Critical patent/CN109285808A/zh
Priority to US16/835,526 priority patent/US10930785B2/en
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Abstract

一种半导体器件及其形成方法，其中方法包括：提供基底；在基底上形成第一介质层和位于第一介质层中的目标栅极结构，第一介质层中具有位于目标栅极结构上的第一槽；刻蚀第一槽侧壁的第一介质层以扩大第一槽的开口，形成第二槽；在第二槽中形成保护层，保护层的介电常数大于第一介质层的介电常数；在目标栅极结构和保护层两侧的第一介质层中形成插塞。所述方法提高了半导体器件的性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其形成方法。
背景技术
MOS(金属-氧化物-半导体)晶体管，是现代集成电路中最重要的元件之一。MOS晶体管的基本结构包括：半导体衬底；位于半导体衬底表面的栅极结构，所述栅极结构包括：位于半导体衬底表面的栅介质层以及位于栅介质层表面的栅电极层；位于栅极结构两侧半导体衬底中的源漏掺杂区。
MOS晶体管的工作原理是：通过在栅极结构施加电压，调节栅极结构底部沟道的电流来产生开关信号。
然而，现有技术中MOS晶体管构成的半导体器件的性能较差。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，以提高半导体器件的性能。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供基底；在基底上形成第一介质层和位于第一介质层中的目标栅极结构，第一介质层中具有位于目标栅极结构上的第一槽；刻蚀第一槽侧壁的第一介质层以扩大第一槽的开口，形成第二槽；在第二槽中形成保护层，保护层的介电常数大于第一介质层的介电常数；在目标栅极结构和保护层两侧的第一介质层中形成插塞。
可选的，刻蚀第一槽侧壁的第一介质层以扩大第一槽的开口的工艺包括湿法刻蚀工艺，参数包括：采用的溶液为氢氟酸溶液。
可选的，所述第一槽具有相对的第一侧壁和第二侧壁，第一侧壁和第二侧壁平行于目标栅极结构的延伸方向；在刻蚀第一槽侧壁的第一介质层的过程中，对第一槽第一侧壁的刻蚀量为3nm～10nm，对第一槽第二侧壁的刻蚀量为3nm～10nm。
可选的，所述保护层和插塞之间具有第一介质层的材料。
可选的，在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述保护层和插塞之间的第一介质层的尺寸在2nm以上。
可选的，所述保护层和插塞之间不具有第一介质层的材料。
可选的，形成所述保护层的步骤包括：在所述第二槽中以及第一介质层上形成保护材料层；去除第一介质层上的保护材料层，形成保护层。
可选的，所述保护层的相对介电常数为5.0～7.4；所述第一介质层的材料为氧化硅或低K介质材料。
可选的，所述保护层的材料为氮化硅、氮氧化硅或氮化硼。
可选的，在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述插塞的顶部尺寸大于插塞的底部尺寸。
可选的，形成所述第一介质层、目标栅极结构和第一槽的方法包括：在基底上形成第一介质层和贯穿第一介质层的初始栅极结构；去除部分初始栅极结构以降低初始栅极结构的高度，形成目标栅极结构和位于目标栅极结构上的第一槽。
可选的，所述初始栅极结构包括初始栅极结构本体和位于初始栅极结构本体侧壁的初始侧墙；所述目标栅极结构包括目标栅极结构本体和位于目标栅极结构本体侧壁的目标侧墙；去除部分初始栅极结构的方法包括：去除部分初始栅极结构本体以降低初始栅极结构本体的高度，形成目标栅极结构本体；去除部分初始栅极结构本体后，去除部分初始侧墙以降低初始侧墙的高度，形成目标侧墙。
可选的，在形成插塞之前，还包括：在所述第一介质层和保护层上形成第二介质层；在所述目标栅极结构和保护层两侧形成贯穿第一介质层和第二介质层的通孔；在所述通孔中形成插塞。
本发明还提供一种半导体器件，包括：基底；位于基底上的目标栅极结构；位于基底上的第一介质层，第一介质层包括第一子介质层和位于第一子介质层上的第二子介质层，第一子介质层覆盖目标栅极结构的侧壁；位于目标栅极结构顶部表面的保护层，保护层还延伸至目标栅极结构周围第一子介质层的部分表面，第二子介质层覆盖保护层的侧壁，保护层的介电常数大于第一介质层的介电常数；位于目标栅极结构和保护层两侧的第一介质层中的插塞。
可选的，所述保护层和插塞之间具有第一介质层的材料。
可选的，在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述保护层和插塞之间的第一介质层的尺寸在2nm以上。
可选的，所述保护层和插塞之间不具有第一介质层的材料。
可选的，所述保护层的相对介电常数为5.0～7.4；所述第一介质层的材料为氧化硅或低K介质材料。
可选的，所述保护层的材料为氮化硅、氮氧化硅或氮化硼。
可选的，在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述插塞的顶部尺寸大于插塞的底部尺寸。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的半导体器件的形成方法中，刻蚀第一槽侧壁的第一介质层以扩大第一槽的开口，形成第二槽，然后在第二槽中形成保护层。保护层的边缘至插塞边缘之间的距离大于目标栅极结构的边缘至插塞边缘之间的距离，且保护层的介电常数大于第一介质层的介电常数，使得目标栅极结构侧壁中的顶部区域至插塞之间的耐击穿性提高，避免漏电。
本发明技术方案提供的半导体器件中，保护层的边缘至插塞边缘之间的距离大于目标栅极结构的边缘至插塞边缘之间的距离，且保护层的介电常数大于第一介质层的介电常数，使得目标栅极结构侧壁中的顶部区域至插塞之间的耐击穿性提高，避免漏电。
附图说明
图1是一种半导体器件的结构示意图；
图2至图10是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有技术中形成的半导体器件的性能较差。
图1是一种半导体器件的结构示意图，半导体器件包括：基底；位于基底上的栅极结构140，栅极结构140包括位于基底上的栅介质层141以及位于栅介质层141上的栅电极层142；位于栅极结构140顶部表面的保护层150；位于栅极结构140侧壁和保护层150侧壁的侧墙130；位于栅极结构140和侧墙130两侧基底中的源漏掺杂区120；位于基底和源漏掺杂区120上的第一介质层110，第一介质层110覆盖侧墙130的侧壁；位于第一介质层110和保护层150上的第二介质层111；贯穿第二介质层111和第一介质层110的通孔，通孔暴露出源漏掺杂区120；在通孔中形成插塞160。
然而，上述半导体器件的性能较差，原因在于：
随着半导体器件特征尺寸的不断减小，插塞160和栅极结构140之间的距离不断减小。其次，在形成通孔的刻蚀工艺中，随着刻蚀深度的增加，一方面，较多的副产物的聚集在刻蚀区域，另一方，刻蚀气体难以进入刻蚀区域，因此导致通孔在栅极结构140宽度方向上的顶部尺寸大于底部尺寸。栅极结构140侧壁中的顶部区域与插塞160之间的距离较小。导致栅极结构140侧壁中的顶部区域与插塞160之间的电场强度较大，栅极结构140侧壁中的顶部区域与插塞160之间容易击穿，容易引起漏电。
为了解决上述问题，本发明提供一种半导体器件的形成方法，刻蚀第一槽侧壁的第一介质层以扩大第一槽的开口，形成第二槽；在第二槽中形成保护层，保护层的介电常数大于第一介质层的介电常数；在目标栅极结构和保护层两侧的第一介质层中形成插塞。所述半导体器件的性能得到提高。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图10是本发明一实施例中半导体器件形成过程的结构示意图。
参考图2，提供基底200。
本实施例中，以半导体器件为鳍式场效应晶体管为示例进行说明，相应的，基底200包括半导体衬底201和位于半导体衬底201上的鳍部202。
所述半导体衬底201可以是单晶硅、多晶硅或非晶硅。所述半导体衬底201的材料还可以为锗、锗化硅、砷化镓等半导体材料。本实施例中，半导体衬底201的材料为单晶硅。
本实施例中，所述鳍部202通过图形化半导体衬底201而形成。在其它实施例中，可以是：在半导体衬底上形成鳍部材料层，然后图形化所述鳍部材料层，从而形成鳍部。
本实施例中，所述半导体衬底201上还具有隔离结构203，所述隔离结构203覆盖鳍部202的部分侧壁表面。所述隔离结构203的顶部表面低于所述鳍部202的顶部表面。
所述隔离结构203的材料包括氧化硅。
在其它实施例中，所述半导体器件为平面式MOS晶体管，相应的，所述基底为平面式的半导体衬底。
接着，在基底200上形成第一介质层和位于第一介质层中的目标栅极结构，第一介质层中具有位于目标栅极结构上的第一槽。
参考图3，在基底200上形成第一介质层210和贯穿第一介质层210的初始栅极结构。
所述初始栅极结构包括初始栅极结构本体221和位于初始栅极结构本体221侧壁的初始侧墙220。
所述初始栅极结构本体221包括位于基底200上的初始栅介质层222、位于初始栅介质层222上的初始功函数层223和位于初始功函数层223上的初始栅电极层224。在其它实施例中，所述初始栅极结构本体仅包括位于基底上的初始栅介质层和位于初始栅介质层上的初始栅电极层。
本实施例中，所述初始栅极结构本体221横跨所述鳍部202、覆盖鳍部202的部分侧壁表面和部分顶部表面。其中，所述初始栅介质层222横跨所述鳍部202；所述初始栅介质层222位于部分隔离结构203表面、覆盖鳍部202的部分侧壁表面和部分顶部表面。
所述初始栅介质层222的材料为氧化硅。所述初始栅电极层224的材料为多晶硅。
当所述半导体器件的类型为N型时，所述初始功函数层223的材料包括TiAl；当所述半导体器件的类型为P型时，所述初始功函数层223的材料包括氮化钛。
所述初始侧墙220的材料为氮化硅、氮氧化硅或氮化硼。
所述第一介质层210的材料为氧化硅或低K(K小于3.9)介质材料。
具体的，在基底200上形成伪栅极结构；在所述伪栅极结构侧壁形成初始侧墙220；在伪栅极结构和初始侧墙220两侧的基底200中形成分别形成源漏掺杂区230；形成源漏掺杂区230后，在所述基底200和源漏掺杂区230上形成第一介质层210，第一介质层210覆盖初始侧墙220的侧壁、且暴漏出初始侧墙220和顶部表面和伪栅极结构的顶部表面；形成第一介质层210后，去除伪栅极结构，形成栅开口；在栅开口中形成初始栅极结构本体221。
所述源漏掺杂区230分别位于初始栅极结构两侧的基底200中，具体的，所述源漏掺杂区230分别位于初始栅极结构两侧的鳍部202中。
接着，去除部分初始栅极结构以降低初始栅极结构的高度，形成目标栅极结构和位于目标栅极结构上的第一槽。
所述目标栅极结构包括目标栅极结构本体和位于目标栅极结构本体侧壁的目标侧墙。
下面参考图4和图5介绍去除部分初始栅极结构以降低初始栅极结构的高度的方法。
参考图4，去除部分初始栅极结构本体221以降低初始栅极结构本体221的高度，形成目标栅极结构本体241。
所述目标栅极结构本体241包括位于基底200上的目标栅介质层242、位于目标栅介质层242上的目标功函数层243和位于目标功函数层243上的目标栅电极层244。所述目标栅介质层242对应初始栅介质层222，所述目标功函数层243对应初始功函数层223，所述目标栅电极层244对应初始栅电极层224。
在其它实施例中，所述目标栅极结构本体仅包括位于基底上的目标栅介质层和位于目标栅介质层上的目标栅电极层。
本实施例中，目标栅极结构本体241横跨鳍部202、覆盖鳍部202的部分侧壁表面和部分顶部表面。其中，目标栅介质层242横跨所述鳍部202；所述目标栅介质层242位于部分隔离结构203表面、覆盖鳍部202的部分侧壁表面和部分顶部表面。
参考图5，去除部分初始栅极结构本体221后，去除部分初始侧墙220以降低初始侧墙220的高度，形成目标侧墙240。
本实施例中，去除部分初始侧墙220以降低初始侧墙220的高度的工艺包括各向异性干刻工艺，参数包括：采用的气体包括碳氟基气体，如CH3F。
所述目标栅极结构包括目标栅极结构本体241和位于目标栅极结构本体241侧壁的目标侧墙240。第一介质层210中具有位于目标栅极结构上的第一槽250。
所述源漏掺杂区230分别位于目标栅极结构两侧的基底200中，具体的，所述源漏掺杂区230分别位于目标栅极结构两侧的鳍部202中。
参考图6，刻蚀第一槽250(参考图5)侧壁的第一介质层210以扩大第一槽250的开口，形成第二槽251。
刻蚀第一槽250侧壁的第一介质层210以扩大第一槽250的开口的工艺包括湿法刻蚀工艺，参数包括：采用的溶液为氢氟酸溶液。
所述第一槽250具有相对的第一侧壁和第二侧壁，第一侧壁和第二侧壁平行于目标栅极结构的延伸方向。
在刻蚀第一槽250侧壁的第一介质层210的过程中，对第一槽250第一侧壁的刻蚀量为3nm～10nm，对第一槽250第二侧壁的刻蚀量为3nm～10nm。选择此范围的意义在于：在使第二槽251的开口较大的同时，避免第二槽251的区域投影在源漏掺杂区230表面的面积过大。后续形成的保护层在目标栅极结构宽度方向上的尺寸较大，且保护层对形成后续插塞的空间的阻挡较小。
参考图7，在第二槽251(参考图6)中形成保护层260，保护层260的介电常数大于第一介质层210的介电常数。
形成所述保护层260的步骤包括：在所述第二槽251中以及第一介质层210上形成保护材料层(未图示)；去除第一介质层210上的保护材料层，形成保护层260。
去除第一介质层210上的保护材料层的工艺为平坦化工艺，如化学机械研磨工艺或回刻蚀工艺。
所述保护层260的相对介电常数为5.0～7.4。所述保护层260的相对介电常数还可以大于7.4，如10。
所述保护层260的材料为氮化硅、氮氧化硅或氮化硼。
接着，在目标栅极结构和保护层260两侧的第一介质层210中形成插塞。
本实施例中，还包括：在形成插塞之前，在所述第一介质层210和保护层260上形成第二介质层270；在所述目标栅极结构和保护层260两侧形成贯穿第一介质层210和第二介质层270的通孔，通孔底部暴露出源漏掺杂区230；在所述通孔中形成插塞。
参考图8，在所述第一介质层210和保护层260上形成第二介质层270。
所述第二介质层270的材料为氧化硅或低K(K小于3.9)介质材料。
形成第二介质层270的工艺为沉积工艺，如高密度等离子体化学气相沉积工艺。
参考图9，在所述目标栅极结构和保护层260两侧形成贯穿第一介质层210和第二介质层270的通孔280，通孔280底部暴露出源漏掺杂区230。
采用各向异性干刻工艺，刻蚀目标栅极结构和保护层260两侧的第一介质层210和第二介质层270，形成所述通孔280。
在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述通孔280的顶部尺寸大于通孔280的底部尺寸。
参考图10，在所述通孔280中形成插塞290。
在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述插塞290的顶部尺寸大于插塞290的底部尺寸。
所述插塞290的材料为金属，如钨。
本实施例中，还包括：在通孔280中形成插塞290之前，在所述通孔280底部的源漏掺杂区230表面形成金属硅化物层。在其它实施例中，不形成金属硅化物层。
具体的，在所述通孔280的侧壁和底部、以及第二介质层270上形成金属层；进行退火工艺，使金属层和源漏掺杂区230表面材料反应形成金属硅化物层；形成金属硅化物层后，在通孔280中和第二介质层270上形成插塞材料层；平坦化插塞材料层和金属层直至暴露出第二介质层270顶部表面，使通孔280中的插塞材料层形成插塞290。
本实施例中，还包括：形成金属层后，且在形成插塞材料层之前，在通孔280的侧壁和底部、以及第二介质层270上形成阻挡层；平坦化插塞材料层和金属层的过程中平坦化阻挡层直至暴露出第二介质层270顶部表面。在其它实施例中，不形成阻挡层。
所述阻挡层的材料为氮化钽或氮化钛。
本实施例中，所述保护层260和插塞290之间具有金属层和阻挡层的材料。在其它实施例中，保护层和插塞之间具有金属层的材料而不具有阻挡层的材料。
在其它实施例中，形成金属硅化物层后，去除通孔侧壁的金属层，相应的，保护层和插塞之间不具有金属层的材料。
本实施例中，所述保护层260和插塞290之间具有第一介质层210的材料。
在一个具体的实施例中，在平行于基底200顶部表面且垂直于目标栅极结构延伸方向上，所述保护层260和插塞290之间的第一介质层210的尺寸在2nm以上。保护层260和插塞290之间的第一介质层210的尺寸设计在2nm以上，好处包括：在达到保护层260和插塞290之间具有第一介质层210的基础上，使形成插塞290的工艺的可控性较高。
在其它实施例中，所述保护层和插塞之间不具有第一介质层的材料。
相应的，本实施例还提供一种采用上述方法形成的半导体器件，请继续参考图10，包括：基底200；位于基底200上的目标栅极结构；位于基底200上的第一介质层210，第一介质层210包括第一子介质层和位于第一子介质层上的第二子介质层，第一子介质层覆盖目标栅极结构的侧壁；位于目标栅极结构顶部表面的保护层260，保护层260还延伸至目标栅极结构周围第一子介质层的部分表面，第二子介质层覆盖保护层260的侧壁，保护层260的介电常数大于第一介质层的介电常数；位于目标栅极结构和保护层260两侧的第一介质层210中的插塞290。
在一个实施例中，所述保护层260和插塞290之间具有第一介质层的材料。具体的，在平行于基底200顶部表面且垂直于目标栅极结构延伸方向上，所述保护层260和插塞290之间的第一介质层210的尺寸在2nm以上。
在另一个实施例中，所述保护层和插塞之间不具有第一介质层的材料。
所述保护层260的相对介电常数为5.0～7.4；所述第一介质层210的材料为氧化硅或低K介质材料。
所述保护层260的材料为氮化硅、氮氧化硅或氮化硼。
所述目标栅极结构包括目标栅极结构本体241和位于目标栅极结构本体241侧壁的目标侧墙240。
所述半导体器件还包括：分别位于目标栅极结构两侧的基底200中的源漏掺杂区230；位于源漏掺杂区230和插塞290之间的金属硅化物层。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体器件的形成方法，其特征在于，包括：
提供基底；
在基底上形成第一介质层和位于第一介质层中的目标栅极结构，第一介质层中具有位于目标栅极结构上的第一槽；
刻蚀第一槽侧壁的第一介质层以扩大第一槽的开口，形成第二槽；
在第二槽中形成保护层，保护层的介电常数大于第一介质层的介电常数；
在目标栅极结构和保护层两侧的第一介质层中形成插塞。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，刻蚀第一槽侧壁的第一介质层以扩大第一槽的开口的工艺包括湿法刻蚀工艺，参数包括：采用的溶液为氢氟酸溶液。
3.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述第一槽具有相对的第一侧壁和第二侧壁，第一侧壁和第二侧壁平行于目标栅极结构的延伸方向；在刻蚀第一槽侧壁的第一介质层的过程中，对第一槽第一侧壁的刻蚀量为3nm～10nm，对第一槽第二侧壁的刻蚀量为3nm～10nm。
4.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述保护层和插塞之间具有第一介质层的材料。
5.根据权利要求4所述的半导体器件的形成方法，其特征在于，在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述保护层和插塞之间的第一介质层的尺寸在2nm以上。
6.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述保护层和插塞之间不具有第一介质层的材料。
7.根据权利要求1所述的半导体器件的形成方法，其特征在于，形成所述保护层的步骤包括：在所述第二槽中以及第一介质层上形成保护材料层；去除第一介质层上的保护材料层，形成保护层。
8.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述保护层的相对介电常数为5.0～7.4；所述第一介质层的材料为氧化硅或低K介质材料。
9.根据权利要求8所述的半导体器件的形成方法，其特征在于，所述保护层的材料为氮化硅、氮氧化硅或氮化硼。
10.根据权利要求1所述的半导体器件的形成方法，其特征在于，在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述插塞的顶部尺寸大于插塞的底部尺寸。
11.根据权利要求1所述的半导体器件的形成方法，其特征在于，形成所述第一介质层、目标栅极结构和第一槽的方法包括：在基底上形成第一介质层和贯穿第一介质层的初始栅极结构；去除部分初始栅极结构以降低初始栅极结构的高度，形成目标栅极结构和位于目标栅极结构上的第一槽。
12.根据权利要求11所述的半导体器件的形成方法，其特征在于，所述初始栅极结构包括初始栅极结构本体和位于初始栅极结构本体侧壁的初始侧墙；
所述目标栅极结构包括目标栅极结构本体和位于目标栅极结构本体侧壁的目标侧墙；
去除部分初始栅极结构的方法包括：去除部分初始栅极结构本体以降低初始栅极结构本体的高度，形成目标栅极结构本体；去除部分初始栅极结构本体后，去除部分初始侧墙以降低初始侧墙的高度，形成目标侧墙。
13.根据权利要求1所述的半导体器件的形成方法，其特征在于，在形成插塞之前，还包括：在所述第一介质层和保护层上形成第二介质层；在所述目标栅极结构和保护层两侧形成贯穿第一介质层和第二介质层的通孔；在所述通孔中形成插塞。
14.一种半导体器件，其特征在于，包括：
基底；
位于基底上的目标栅极结构；
位于基底上的第一介质层，第一介质层包括第一子介质层和位于第一子介质层上的第二子介质层，第一子介质层覆盖目标栅极结构的侧壁；
位于目标栅极结构顶部表面的保护层，保护层还延伸至目标栅极结构周围第一子介质层的部分表面，第二子介质层覆盖保护层的侧壁，保护层的介电常数大于第一介质层的介电常数；
位于目标栅极结构和保护层两侧的第一介质层中的插塞。
15.根据权利要求14所述的半导体器件，其特征在于，所述保护层和插塞之间具有第一介质层的材料。
16.根据权利要求15所述的半导体器件，其特征在于，在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述保护层和插塞之间的第一介质层的尺寸在2nm以上。
17.根据权利要求14所述的半导体器件，其特征在于，所述保护层和插塞之间不具有第一介质层的材料。
18.根据权利要求14所述的半导体器件，其特征在于，所述保护层的相对介电常数为5.0～7.4；所述第一介质层的材料为氧化硅或低K介质材料。
19.根据权利要求18所述的半导体器件，其特征在于，所述保护层的材料为氮化硅、氮氧化硅或氮化硼。
20.根据权利要求14所述的半导体器件，其特征在于，在平行于基底顶部表面且垂直于目标栅极结构延伸方向上，所述插塞的顶部尺寸大于插塞的底部尺寸。
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