CN109216444A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109216444A
CN109216444A CN201810086879.4A CN201810086879A CN109216444A CN 109216444 A CN109216444 A CN 109216444A CN 201810086879 A CN201810086879 A CN 201810086879A CN 109216444 A CN109216444 A CN 109216444A
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末代知子
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Abstract

实施方式提供一种具有较高的雪崩耐量的半导体装置。实施方式的半导体装置在配置有发射极层的单元区域中的集电极电极与第1导电型基极层之间设有第2导电型的第1集电极层。在配置有栅极布线的边界区域中的集电极电极与第1导电型基极层之间设有第2导电型的第2集电极层。第2集电极层中的第2导电型杂质浓度的峰值比第1集电极层中的第2导电型杂质浓度的峰值高。

Description

半导体装置
本申请基于日本专利申请第2017－127267号(申请日：2017年6月29日)主张优先权，本申请通过参照该基础申请而包含该基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置。
背景技术
将使用开关功能、放大、整流功能进行电力变换的半导体设备称作功率半导体设备。作为这样的功率半导体设备，主要的是：作为开关元件有双极型晶体管、晶闸管、MOSFET(Metal Oxide Silicon Field Effect Transistor)、IGBT(Insulated－Gate BipolarTransistor，绝缘栅双极型晶体管)；作为整流元件有pn二极管、pin二极管(p－intrinsic－n Diode)、SBD(Shottky Barrier Diode，肖特基势垒二极管)等的二极管。
其中，作为双极元件的IGBT由于拥有由MOS栅极带来的高速动作、低损失驱动、高耐压化、大电流驱动、较大的安全动作区域，所以在许多领域被使用，也被积极地进行开发。IGBT虽然与作为单极元件的MOSFET在高速动作方面稍差，但即使进行高耐压展开也为低损失，能够进行大电流驱动，所以应用范围较宽。在这样的IGBT的重要的设计事项之一中，有雪崩耐量，该雪崩耐量用于即使在开关动作时发生了雪崩现象的状态下元件也不破坏。
发明内容
技术方案提供一种具有较高的雪崩耐量的半导体装置。
技术方案的半导体装置具备：半导体层，具有第1主面和第2主面；集电极电极，设在上述第1主面上；发射极电极，设在上述第2主面上；栅极电极，设在上述第2主面侧的上述半导体层内，在第1方向上延伸；栅极布线，设在上述第2主面上，在与上述第1方向交叉的第2方向上延伸，与上述栅极电极连接；以及绝缘膜，设在上述栅极电极与上述半导体层之间。上述半导体层具有：第1导电型基极层；第2导电型基极层，设在上述第1导电型基极层与上述发射极电极之间；第1导电型的发射极层，设在上述第2导电型基极层与上述发射极电极之间，与上述发射极电极连接；第2导电型的第1集电极层，设在配置有上述发射极层的单元区域中的上述集电极电极与上述第1导电型基极层之间；第2导电型的第2集电极层，设在配置有上述栅极布线的边界区域中的上述集电极电极与上述第1导电型基极层之间，上述第2集电极层中的第2导电型杂质浓度的峰值比上述第1集电极层中的第2导电型杂质浓度的峰值高。
附图说明
图1是实施方式的半导体装置的示意俯视图。
图2是实施方式的半导体装置的示意俯视图。
图3是图1的A－A剖视图。
图4(a)是图3中的一部分的放大图，图4(b)是图2的B－B剖视图。
图5是图2的C－C剖视图。
图6(a)是通过模拟得到的IGBT的电流密度的分布图，图6(b)是集电极层的空穴注入效率比图6(a)低的情况下通过模拟得到的IGBT的电流密度的分布图。
具体实施方式
以下，参照附图对实施方式进行说明。另外，在各图中，对相同的要素赋予相同的标号。
在以下的实施方式中，设第1导电型为n型、第2导电型为p型而进行说明，但也可以设第1导电型为p型，设第2导电型为n型。
此外，在实施方式中，假设半导体材料为硅，但半导体材料并不限于硅，例如也可以是碳化硅、氮化镓、氧化镓等。
此外，在以下的实施方式中，杂质浓度及杂质数分别可以换称作载流子浓度和载流子数。
图1是实施方式的半导体装置的芯片的示意俯视图。
图2是表示栅极电极51及半导体层表面的各层的布局的一例的示意俯视图。
图3是图1的A－A剖视图。
图4(a)是图3中的一部分的放大图，图4(b)是图2的B－B剖视图。
图5是图2的C－C剖视图。
实施方式的半导体装置是如图3～图5所示在集电极电极11与发射极电极12之间设有半导体层20、电流在将集电极电极11与发射极电极12连结的方向(纵向)上流动的纵型IGBT构造的设备。
半导体层20拥有第1主面(图3～图5中的下表面)和其相反侧的第2主面(图3～图5中的上表面)，集电极电极11设在第1主面上，发射极电极12设在第2主面上。
在图1及图2中，将在相对于半导体层20的第1主面或第2主面平行的面内正交的2方向设为X方向及Y方向。
实施方式的半导体装置如图3所示，具有多个单元(cell)区域100、和位于多个单元区域100之间的边界的边界区域(或栅极布线区域)200。在单元区域100的外侧，以将单元区域100包围的方式形成有未图示的末端区域。
首先，参照图5对单元区域100的构造进行说明。
半导体层20是掺杂有杂质的硅层。单元区域100中的半导体层20具有p+型的第1集电极层21、n型的缓冲层23、n－型基极层(或漂移层)24、p型基极层25、n+型的发射极层26和p+型的基极接触层27(图2所示)。
缓冲层23及发射极层26的n型杂质浓度比n－型基极层24的n型杂质浓度高。杂质浓度例如表示峰值。
第1集电极层21被设置在集电极电极11上，接触在集电极电极11上。在第1集电极层21上设有缓冲层23。在缓冲层23上设有n－型基极层24。n－型基极层24上设有p型基极层25。在p型基极层25上设有发射极层26。
如图2所示，多个发射极层26在X方向上相互离开而被有选择地形成在p型基极层25的表面上，在Y方向上延伸。在p型基极层25的表面上，还形成有在Y方向上延伸的基极接触层27。发射极层26和基极接触层27在X方向上交替地排列。
实施方式的半导体装置具有沟槽栅极构造的栅极电极51。如图5所示，在第2主面侧的半导体层20内设有栅极电极51。在栅极电极51的侧面与半导体层20之间、以及栅极电极51的底侧与半导体层20之间设有绝缘膜41。绝缘膜41例如是硅氧化膜。
在形成在半导体层20的第2主面侧的沟槽的内壁上例如用热氧化法形成绝缘膜41，在该绝缘膜41的内侧作为栅极电极51而埋入例如多晶硅。
如图2所示，多个栅极电极51在X方向上延伸，在Y方向上相互离开。如图5所示，栅极电极51将发射极层26及p型基极层25贯通而达到n－型基极层24。栅极电极51的侧面隔着绝缘膜(栅极绝缘膜)41与发射极层26及p型基极层25对置。
在栅极电极51上设有层间绝缘膜42。以将层间绝缘膜42覆盖的方式，在发射极层26上设置发射极电极12，发射极电极12接触在发射极层26上。
发射极电极12如图4(b)所示，也被设置在基极接触层27上，接触在基极接触层27上。
如图1所示，在1个芯片内，发射极电极12被分割为多个。在发射极电极12的周围及分割的发射极电极12之间形成有栅极布线13。配置在被分割的发射极电极12之间的栅极布线13在Y方向上延伸。
发射极电极12及栅极布线13如图3所示，形成在设于半导体层20及栅极电极51之上的层间绝缘膜42的上表面上。在该层间绝缘膜42的上表面上，也形成有图1所示的栅极焊盘15。
如图1所示，配置在发射极电极12的周围的栅极布线13、配置在被分割的发射极电极12之间的1条栅极布线13及栅极焊盘15被一体地形成，并相互连续。
集电极电极11、发射极电极12、栅极布线13及栅极焊盘15由金属材料等构成。
如图3所示，栅极布线13被绝缘膜45覆盖。在发射极电极12的上表面及栅极焊盘15的上表面上，接合着金属线或板状的连接器。集电极电极11被接合在引线框上。
如图4(b)所示，在单元区域100中配置有多个发射极层26。在栅极布线区域200中，配置有栅极布线13，没有配置发射极层26。在图4(b)所示的截面中，栅极布线区域200位于比夹着该栅极布线区域200的2个单元区域100端部的发射极层26靠内侧。
如图4(a)及图4(b)所示，在栅极布线区域200的n－型基极层24的第2主面侧形成有p型半导体层28。p型基极层25从单元区域100延伸到栅极布线区域200的p型半导体层28的表面。p型半导体层28的底部处于比栅极电极51的底部及p型基极层25的底部深的位置。p型半导体层28经由p型基极层25及形成在其表面上的p+型的基极接触层27而连接在发射极电极12上。
如图4(a)所示，栅极电极51在栅极布线区域200的半导体层20内在X方向上被切断。p型半导体层28将栅极布线区域200中被切断的栅极电极51的底侧的角部覆盖。这样的p型半导体层28将电场容易集中的沟槽构造的栅极电极51的底角的电场缓和。
在栅极电极51的栅极布线区域200侧的端部，设有连接部52。连接部52被用与栅极电极51相同的材料(例如多晶硅)与栅极电极51一体地形成，以被抬起到半导体层20的上方的方式形成。在该连接部52与半导体层20的上表面(第2主面)之间设有绝缘膜41。
在连接部52之上设有布线53。如图2所示，布线53在Y方向上延伸、与Y方向上隔开间隔的多个栅极电极51的各自的连接部52接触。布线53由与栅极电极51相同的材料的例如多晶硅构成。
如图4(a)所示，在布线53与半导体层20的上表面之间设有绝缘膜41。在布线53上设有栅极布线13。多个栅极电极51经由连接部52及布线53而与栅极布线13连接。
如图3所示，在栅极电极51上的末端区域侧的端部，也设有连接部52。在末端区域与单元区域100的边界，也在连接部52之上设有布线53，在该布线53之上设有栅极布线13，栅极电极51经由连接部52及布线53而与栅极布线13连接。
栅极电极51的末端区域侧的端部的底角也被p型半导体层28覆盖。
在栅极布线区域200中，如图4(a)及图4(b)所示，在集电极电极11与缓冲层23之间设有p++型的第2集电极层22。
第2集电极层22中的p型杂质浓度的峰值(atoms/cm3)比第1集电极层21中的p型杂质浓度的峰值高。第2集电极层22中的每单位面积的p型杂质数(掺杂量)(atoms/cm2)比第1集电极层21中的每单位面积的p型杂质数(掺杂量)多。这些能够用SIMS(Secondary IonMass Spectrometry，次级离子质谱分析法)，SRA(Spreading Resistance Analysis，扩展电阻分析)等解析。
第1集电极层21和第2集电极层22以大致相同的厚度设在集电极电极11与缓冲层23之间的相同的层中。第2集电极层22没有形成在发射极层26的下方。
在以上说明的IGBT中，对集电极电极11与发射极电极12之间施加电压。被施加给集电极电极11的电位比被施加给发射极电极12的电位高。
在IGBT的导通动作时，对栅极电极51施加阈值以上的电位，在图5所示的单元区域100的p型基极层25的对置于栅极电极51的区域中形成反型层(n型的沟道)。并且，电流经由第1集电极层21、缓冲层23、n－型基极层24、沟道及发射极层26而在集电极电极11与发射极电极12之间流过。此时，从第1集电极层21向n型基极层24供给空穴，在n－型基极24中形成电子及空穴的高密度状态，能得到较低的导通电阻。
缓冲层23抑制栅极关断(off)状态下耗尽层到达第1集电极层21，抑制穿通。
IGBT由于是双极元件，所以有破坏耐量变弱的情况。如果从导通状态开始使栅极电压变得比阈值低而关断，则沟道消失，电子电流被切断。如果在组装有IGBT的电路上不连接使电流回流的元件(例如回流二极管)，则即使栅极导通时的经过沟道的电子电流被切断，IGBT也因雪崩电流而暂时继续流过电流。
此时生成的电子电流流入到p型集电极层中，通过电子与空穴效率良好地局部性地再结合而发生电流集中，有可能导致元件破坏。将能对抗该破坏的特性称作雪崩耐量，IGBT的重要的设计事项之一为雪崩耐量提高的设计。
通过模拟，判明雪崩耐量试验下的电流集中是根据来自p型集电极层的空穴注入效率而变化的。如果空穴注入效率较大，则空穴与流入到p型集电极层中的电子电流效率良好地再结合，所以变得更容易电流集中。即使将p型集电极层的面方向的整个区域的杂质浓度设计为相同，也会在因工艺偏差而产生的杂质浓度局部较高的部分随机地发生电流集中，有可能在单元区域(IGBT区域)发生元件破坏。
图6(a)及图6(b)是通过模拟得到的IGBT的电流密度的分布图，是包括许多栅极电极51的区域的模拟结果。图6(a)表示集电极层的空穴注入效率比图6(b)高的情况，图6(b)表示集电极层的空穴注入效率比图6(b)低的情况。
图6(a)及图6(b)中的纵向及横向分别对应于半导体层的纵向(厚度方向)及横向。
表示了设区域a的电流密度为1(A/cm2)，区域b、区域c、区域d、区域e电流密度变大的模拟结果。即，区域b的电流密度比区域a的电流密度大，区域c的电流密度比区域b的电流密度大，区域d的电流密度比区域c的电流密度大，区域e的电流密度比区域d的电流密度大。
在与图6(a)相比降低了空穴注入效率的图6(b)中，与图6(a)的情况相比电子和空穴变得难以再结合，没有再结合的电子电流在横向上扩展，电流集中程度下降。
根据实施方式，使栅极布线区域(边界区域)200的第2集电极层22中的p型杂质浓度的峰值比单元区域100的第1集电极层21中的p型杂质浓度的峰值高，及/或使第2集电极层22中的每单位面积的p型杂质数(掺杂量)比第1集电极层21中的每单位面积的p型杂质数(掺杂量)多。因而，栅极布线区域200与单元区域100相比，空穴注入效率较大。
因此，在雪崩时，在栅极布线区域200中，比单元区域100更先发生电流集中。由于来自单元区域100的发射极层26的电子在横向上扩散，扩展到栅极布线区域(边界区域)200，所以能够有效率地使栅极布线区域200产生电流集中部位。由于拥有较大的空穴注入效率的第2集电极层22从沟道区域离开而形成，所以不会因栅极布线区域200中的电流集中而破坏具有发射极层26及沟道等的要素的IGBT元件部。
通过以避开IGBT元件动作的单元区域100的方式，强制地使栅极布线区域200产生电流集中，能够避免IGBT元件部的破坏而使雪崩耐量提高。
例如通过离子注入法的p型杂质的注入，形成第1集电极层21及第2集电极层22。在半导体层20中，在对形成第1集电极层21及第2集电极层22的层(区域)整面进行了第1次的离子注入后，在将形成第1集电极层21的区域遮蔽后，对形成第2集电极层22的区域进行第2次的离子注入。
在图1中表示了发射极电极12在X方向上被2分割的例子，但根据芯片尺寸，也可以将发射极电极12在X方向上做成3分割以上。在此情况下，被分割的发射极电极12之间的栅极布线13被形成2条以上，即，单元区域100之间的栅极布线区域200被形成2条以上。因而，配置到栅极布线区域200中的第2集电极层22也被形成2个以上。在图2中，表示了发射极层26和基极接触层27在X方向上交替地排列的情况，但发射极层26和基极接触层27也可以沿着栅极电极51平行地配置。
上述实施方式中例示的各要素的配置、材料、条件、形状、尺寸等并不限定于例示，可以适当变更。此外，上述实施方式中例示的各要素只要在技术上可能，就可以组合，将它们组合后的形态也只要包含实施方式的特征，就包含在实施方式的范围中。
说明了本发明的一些实施方式，但这些实施方式是作为例子提示的，不是要限定发明的范围。这些新的实施方式能够以其他各种各样的形态实施，在不脱离发明的主旨的范围内能够进行各种各样的省略、替换、变更。这些实施方式及其变形包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明和其等价的范围中。

Claims (6)

1.一种半导体装置，其中，具备：
半导体层，具有第1主面和第2主面；
集电极电极，设在上述第1主面上；
发射极电极，设在上述第2主面上；
栅极电极，设在上述第2主面侧的上述半导体层内，在第1方向上延伸；
栅极布线，设在上述第2主面上，在与上述第1方向交叉的第2方向上延伸，与上述栅极电极连接；以及
绝缘膜，设在上述栅极电极与上述半导体层之间，
上述半导体层具有：
第1导电型基极层；
第2导电型基极层，设在上述第1导电型基极层与上述发射极电极之间；
第1导电型的发射极层，设在上述第2导电型基极层与上述发射极电极之间，与上述发射极电极连接；
第2导电型的第1集电极层，设在配置有上述发射极层的单元区域中的上述集电极电极与上述第1导电型基极层之间；
第2导电型的第2集电极层，设在配置有上述栅极布线的边界区域中的上述集电极电极与上述第1导电型基极层之间，上述第2集电极层中的第2导电型杂质浓度的峰值比上述第1集电极层中的第2导电型杂质浓度的峰值高。
2.一种半导体装置，其中，具备：
半导体层，具有第1主面和第2主面；
集电极电极，设在上述第1主面上；
发射极电极，设在上述第2主面上；
栅极电极，设在上述第2主面侧的上述半导体层内，在第1方向上延伸；
栅极布线，设在上述第2主面上，在与上述第1方向交叉的第2方向上延伸，与上述栅极电极连接；以及
栅极绝缘膜，设在上述栅极电极与上述半导体层之间，
上述半导体层具有：
第1导电型基极层；
第2导电型基极层，设在上述第1导电型基极层与上述发射极电极之间；
第1导电型的发射极层，设在上述第2导电型基极层与上述发射极电极之间，与上述发射极电极连接；
第2导电型的第1集电极层，设在配置有上述发射极层的单元区域中的上述集电极电极与上述第1导电型基极层之间；
第2导电型的第2集电极层，设在配置有上述栅极布线的边界区域中的上述集电极电极与上述第1导电型基极层之间，上述第2集电极层中的每单位面积的第2导电型杂质数比上述第1集电极层中的每单位面积的第2导电型杂质数多。
3.如权利要求1或2所述的半导体装置，其中，
上述半导体层还具有设在上述边界区域的上述第1导电型基极层内且与上述发射极电极连接的第2导电型半导体层。
4.如权利要求3所述的半导体装置，其中，
上述栅极电极在上述边界区域的上述半导体层内在上述第1方向上被切断；
上述第2导电型半导体层将切断后的上述栅极电极的底侧的角部覆盖。
5.如权利要求1或2所述的半导体装置，其中，
上述半导体层还具有第1导电型的缓冲层，该第1导电型的缓冲层设在上述第1集电极层与上述第1导电型基极层之间、以及上述第2集电极层与上述第1导电型基极层之间，该第1导电型的缓冲层的第1导电型杂质浓度比上述第1导电型基极层高。
6.如权利要求1或2所述的半导体装置，其中，
上述第1集电极层的厚度与上述第2集电极层的厚度大致相同。
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Application publication date: 20190115