CN109087915B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN109087915B
CN109087915B CN201810587258.4A CN201810587258A CN109087915B CN 109087915 B CN109087915 B CN 109087915B CN 201810587258 A CN201810587258 A CN 201810587258A CN 109087915 B CN109087915 B CN 109087915B
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patterns
semiconductor device
pattern
device isolation
isolation layer
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CN109087915A (zh
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赵文祺
金贤煜
辛宗灿
黄莉铃
梁在锡
郑臻愚
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了半导体器件。一种半导体器件包括栅极结构和邻近的接触。半导体器件包括连接到接触的连接器。在一些实施方式中，半导体器件包括连接到连接器的布线图案。此外，在一些实施方式中，连接器和半导体器件的第一单元与第二单元之间的边界相邻。

Description

半导体器件
技术领域
本公开涉及半导体器件，更具体地，涉及包括场效应晶体管的半导体器件。
背景技术
半导体器件可以包括具有金属氧化物半导体场效应晶体管(MOSFET)的集成电路。随着半导体器件变得高度集成，MOSFET可以在尺寸上按比例缩小，这可导致半导体器件的操作特性的劣化。例如，半导体器件中金属线的工艺余量(例如间隔)可减小，这可导致操作特性的劣化。因此，已发展了各种研究来制造在克服由半导体器件的高集成所致的限制的同时具有高性能的半导体器件。
发明内容
本发明构思的一些实施方式提供了包括高度集成的场效应晶体管的半导体器件。然而，本领域技术人员将由以下描述清楚地理解本发明构思的以上未提及的其它目的。
根据本发明构思的示例实施方式，一种半导体器件可以包括在第一方向上延伸的多个有源图案。半导体器件可以包括跨越所述多个有源图案并在交叉第一方向的第二方向上延伸的多个栅极结构。半导体器件可以包括在所述多个栅极结构中相邻的第一栅极结构与第二栅极结构之间在第二方向上延伸的器件隔离层。半导体器件可以包括在所述多个栅极结构与器件隔离层之间的多个接触图案。半导体器件可以包括分别连接到所述多个接触图案的多个连接图案。器件隔离层可以在所述多个连接图案之间，所述多个连接图案可以在第一方向上以第一距离彼此间隔开。半导体器件可以包括分别连接到所述多个连接图案的多个布线图案。此外，器件隔离层可以在所述多个布线图案之间，所述多个布线图案可以在第一方向上以比第一距离长的第二距离彼此间隔开。
根据一些实施方式，一种半导体器件可以包括在第一方向上延伸的多个有源图案。半导体器件可以包括跨越所述多个有源图案并在交叉第一方向的第二方向上延伸的器件隔离层。半导体器件可以包括与器件隔离层间隔开并在第二方向上延伸以跨越所述多个有源图案的栅极结构。半导体器件可以包括在栅极结构的相反侧上的所述多个有源图案上的多个源极/漏极杂质层。半导体器件可以包括连接到所述多个源极/漏极杂质层中的在器件隔离层与栅极结构之间的一个的接触图案。半导体器件可以包括连接图案，该连接图案连接到接触图案并在第一方向上以第一距离与和器件隔离层对准的轴线间隔开。此外，半导体器件可以包括布线图案，该布线图案连接到连接图案并在第一方向上以比第一距离长的第二距离与和器件隔离层对准的轴线间隔开。
根据一些实施方式，一种半导体器件可以包括衬底，该衬底包括含第一N阱区和第一P阱区的第一单元区、以及含第二N阱区和第二P阱区的第二单元区。半导体器件可以包括在衬底的第一单元区上的栅极结构。半导体器件可以包括在衬底上分别与栅极结构的相反的第一侧和第二侧相邻的第一源极/漏极杂质区和第二源极/漏极杂质区。半导体器件可以包括在衬底的第二单元区上的第三源极/漏极杂质区。半导体器件可以包括连接到第一源极/漏极杂质区并包含第一金属性材料的第一接触。半导体器件可以包括接触第一接触并延伸以重叠栅极结构的至少一部分的第一连接器。第一连接器可以包括不同于第一金属性材料的第二金属性材料。半导体器件可以包括连接到第三源极/漏极杂质区的第二接触。此外，半导体器件可以包括接触第二接触的第二连接器。
另外的示例实施方式的细节被包括在说明书和附图中。
附图说明
图1示出显示了根据本发明构思的示例实施方式的半导体器件的简化俯视图。
图2示出显示了根据本发明构思的示例实施方式的半导体器件的俯视图。
图3A、3B、3C和3D示出分别沿图2的线I-I'、II-II'、III-III'和IV-IV'截取的剖视图。
图4示出显示了根据本发明构思的示例实施方式的半导体器件的俯视图。
图5示出沿图4的线I-I'截取的剖视图。
图6示出显示了根据本发明构思的示例实施方式的半导体器件的俯视图。
图7、9和11示出显示了根据本发明构思的示例实施方式的半导体器件的一部分的俯视图。
图8、10和12分别示出沿图7、9和11的线I-I'截取的剖视图。
图13示出显示了根据本发明构思的示例实施方式的半导体器件的俯视图。
图14示出沿图13的线I-I'截取的剖视图。
具体实施方式
在下文中，将结合附图详细描述根据本发明构思的示例实施方式的半导体器件。
图1示出显示了根据本发明构思的示例实施方式的半导体器件的简化俯视图。
参照图1，半导体衬底100可以在其上提供有多个集成的标准单元SC，该多个集成的标准单元SC包括诸如逻辑加门或逻辑乘门的逻辑器件。例如，标准单元SC可以包括基本单元(例如与门、或门、或非、或者反相器)、复合单元(例如OAI(或/与/反相器)门和AOI(与/或/反相器)门)或存储元件(例如主-从触发器和锁存器)。
标准单元SC可以沿着第一方向D1和交叉第一方向D1的第二方向D2二维地布置。标准单元SC的每个可以包括其中形成NMOS场效应晶体管的P阱区PR和其中形成PMOS场效应晶体管的N阱区NR。
图2示出显示了根据本发明构思的示例实施方式的半导体器件的俯视图。图3A、3B、3C和3D示出分别沿图2的线I-I'、II-II'、III-III'和IV-IV'截取的剖视图。
参照图2及3A至3D，半导体衬底100可以在其上提供有沿第一方向D1布置的多个标准单元SC。标准单元SC的每个可以包括有源图案101、栅极结构GS、源极/漏极杂质层130、有源接触图案ACP1和ACP2、栅极接触图案GCP、通路图案VP1和VP2、布线图案CP、以及电源线PL1和PL2。当在此使用时，术语“接触图案”或术语“接触”可以指有源接触图案ACP1和ACP2中的一个。此外，当在此使用时，术语“连接图案”或术语“连接器”可以指通路图案VP、通路图案VP1或通路图案VP2。
半导体衬底100可以包括第一阱区R1和第二阱区R2。在一些实施方式中，NMOS场效应晶体管可以被提供在第一阱区R1上，PMOS场效应晶体管可以被提供在第二阱区R2上。
半导体衬底100可以是例如硅衬底、锗衬底、SOI(绝缘体上硅)衬底或GOI(绝缘体上锗)衬底。在第一阱区R1和第二阱区R2的每个处/中，多个有源图案101可以在第一方向D1上延伸，并且可以在交叉第一方向D1的第二方向D2上彼此间隔开。有源图案101可以是半导体衬底100的部分，并且可以由形成在半导体衬底100中的沟槽限定。
第一器件隔离层103可以设置在有源图案101之间，并且有源图案101的上部可以由第一器件隔离层103暴露。例如，第一器件隔离层103可以具有在有源图案101的顶表面之下的顶表面，并且有源图案101可以向上凸出超过第一器件隔离层103的顶表面。第一器件隔离层103可以在第二方向D2上将有源图案101彼此隔开。
第二器件隔离层105可以在第一方向D1上延伸并且可以限定第一阱区R1和第二阱区R2。第二器件隔离层105可以被提供在第一阱区R1的有源图案101与第二阱区R2的有源图案101之间。第二器件隔离层105可以具有比第一器件隔离层103的宽度大的宽度。第二器件隔离层105可以具有在比第一器件隔离层103的底表面的水平面低或与第一器件隔离层103的底表面的水平面基本相同的水平面处的底表面。第二器件隔离层105可以在第二方向D2上将第一阱区R1和第二阱区R2彼此隔开。第一器件隔离层103和第二器件隔离层105可以通过形成限定有源图案101的沟槽并用绝缘材料(例如硅氧化物层或硅氮化物层)填充沟槽的部分而形成。
栅极结构GS可以在第二方向D2上延伸，同时跨越第一阱区R1和第二阱区R2的有源图案101。栅极结构GS可以在标准单元SC的每个处/中以第一节距规则地布置。例如，栅极结构GS可以具有基本相同的第一宽度W1，并且可以以第一间隔S1在第一方向D1上彼此相等地间隔开。
栅极结构GS的每个可以包括栅极电介质层111、栅极阻挡金属图案113、栅极金属图案115和盖绝缘图案117。栅极间隔物121可以设置在栅极结构GS的每个的相反侧壁上。
栅极电介质层111可以沿第二方向D2延伸，并且可以共形地覆盖有源图案101的上部。栅极电介质层111可以从栅极阻挡金属图案113与有源图案101之间延伸到栅极阻挡金属图案113与栅极间隔物121之间。例如，栅极电介质层111可以从栅极金属图案115的底表面延伸到栅极金属图案115的相反侧壁。栅极电介质层111可以包括其介电常数大于硅氧化物的介电常数的高k电介质材料。栅极电介质层111可以包括例如金属氧化物、金属硅酸盐或金属硅酸盐氮化物。
栅极阻挡金属图案113可以设置在栅极电介质层111与栅极金属图案115之间，并且可以在栅极金属图案115与栅极间隔物121之间延伸。栅极阻挡金属图案113可以包括导电金属氮化物(例如钛氮化物、钽氮化物和/或钨氮化物)。栅极金属图案115可以包括金属性材料(例如钨、钛和/或钽)。盖绝缘图案117可以覆盖栅极金属图案115的顶表面。盖绝缘图案117还可以覆盖栅极间隔物121的顶表面。盖绝缘图案117可以具有与间隙填充绝缘层131的顶表面基本上共平面的顶表面。盖绝缘图案117和栅极间隔物121可以包括例如硅氧化物、硅氮化物、硅氮氧化物、硅碳氮化物(SiCN)或硅碳氮氧化物(SiCON)。
根据一些实施方式，第三器件隔离层107可以在第二方向D2上平行于栅极结构GS延伸，并且可以设置在标准单元SC中彼此相邻的标准单元SC(例如彼此相邻的一对标准单元SC)之间。第三器件隔离层107可以在第二方向D2上跨越有源图案101，并且可以在第一方向D1上将有源图案101彼此隔开。第三器件隔离层107可以在第一方向D1上将彼此相邻的场效应晶体管隔开。第三器件隔离层107可以包括例如硅氧化物层、硅氮化物层、硅氮氧化物层、硅碳氮化物(SiCN)层、硅碳氮氧化物(SiCON)层或其组合。例如，第三器件隔离层107可以包括硅氮化物和/或硅氧化物层。
第三器件隔离层107可以设置在栅极结构GS中彼此相邻的栅极结构GS(彼此相邻的一对栅极结构GS)之间。例如，第三器件隔离层107可以以第二间隔S2与设置在标准单元SC的边缘处的栅极结构GS间隔开。在一些实施方式中，第二间隔S2可以与第一间隔S1基本相同。第三器件隔离层107可以具有小于栅极结构GS的第一宽度W1的约两倍(即双倍)的第二宽度W2。例如，第三器件隔离层107的第二宽度W2可以与栅极结构GS的第一宽度W1基本相同。
第三器件隔离层107可以具有向上凸出超过有源图案101并穿透有源图案101的部分的上部。第三器件隔离层107可以具有比栅极结构GS的顶表面低且比有源图案101的顶表面高的顶表面。第三器件隔离层107可以具有在比第一器件隔离层103或第二器件隔离层105的底表面的水平面低或者与第一器件隔离层103或第二器件隔离层105的底表面的水平面基本相同的水平面处的底表面。第三器件隔离层107可以具有比有源图案101的顶表面低的底表面。
虚设间隔物123可以设置在第三器件隔离层107的上部的相反侧壁上。在一些实施方式中，虚设间隔物123可以包括与栅极间隔物121的材料相同的绝缘材料。虚设间隔物123可以具有比栅极间隔物121的顶表面低的顶表面。例如，虚设间隔物123可以具有比栅极间隔物121的高度小的高度。
源极/漏极杂质层130可以设置在栅极结构GS的每个的相反侧上的有源图案101上。第一阱区R1的源极/漏极杂质层130可以包括n型杂质，第二阱区R2的源极/漏极杂质层130可以包括p型杂质。源极/漏极杂质层130可以是从有源图案101生长的外延层。第一阱区R1的源极/漏极杂质层130可以是锗(Ge)外延层，第二阱区R2的源极/漏极杂质层130可以是硅碳化物(SiC)外延层。根据一些实施方式，第三器件隔离层107可以将在标准单元SC的边缘处在第一方向D1上彼此相邻的源极/漏极杂质层130彼此隔开。如图3D所示，通过外延生长形成的源极/漏极杂质层130可以在第二方向D2上彼此连接。当在此使用时，术语“源极/漏极杂质区”可以指源极/漏极杂质层130中的一个。
间隙填充绝缘层131可以填充栅极结构GS之间的空间并且可以覆盖源极/漏极杂质层130。在一些实施方式中，间隙填充绝缘层131的顶表面可以与栅极结构GS的顶表面基本上共平面。间隙填充绝缘层131可以覆盖第三器件隔离层107的顶表面。
在一些实施方式中，在间隙填充绝缘层131形成之前，蚀刻停止层135可以形成为具有基本均匀的厚度。蚀刻停止层135可以从栅极间隔物121的侧壁延伸到源极/漏极杂质层130上。蚀刻停止层135可以从栅极间隔物121的侧壁延伸到盖绝缘图案117的侧壁上。
层间绝缘层133可以设置在间隙填充绝缘层131上并且可以覆盖栅极结构GS的顶表面。间隙填充绝缘层131和层间绝缘层133可以由对于栅极间隔物121具有蚀刻选择性的绝缘材料形成，并且可以包括硅氧化物层、硅氮化物层、硅氮氧化物层和低k电介质层中的一个或更多个。
有源接触图案ACP1和ACP2可以穿透层间绝缘层133、间隙填充绝缘层131和蚀刻停止层135，并且可以连接到源极/漏极杂质层130。在一些实施方式中，有源接触图案ACP1和ACP2可以包括位于第三器件隔离层107与其邻近的栅极结构GS之间的第一有源接触图案ACP1、以及位于栅极结构GS中彼此相邻的栅极结构GS之间的第二有源接触图案ACP2。
有源接触图案ACP1和ACP2的每个可以连接到一个源极/漏极杂质层130或者连接到设置在第二方向D2上的多个源极/漏极杂质层130。有源接触图案ACP1和ACP2可以包括第一金属性材料，例如金属(例如钨、钛或钽)和/或导电金属氮化物(例如钛氮化物、钽氮化物或钨氮化物)。有源接触图案ACP1和ACP2的每个可以包括第一阻挡金属层141和第一金属层143。有源接触图案ACP1和ACP2的第一阻挡金属层141可以具有均匀的厚度，并且可以共形地覆盖源极/漏极杂质层130的顶表面。
栅极接触图案GCP可以穿透层间绝缘层133和栅极结构GS的盖绝缘图案117，并且可以连接到栅极金属图案115。栅极接触图案GCP可以与有源接触图案ACP1和ACP2同时形成，并且可以包括与有源接触图案ACP1和ACP2的第一金属性材料相同的第一金属性材料。类似于有源接触图案ACP1和ACP2，栅极接触图案GCP的每个可以包括第一阻挡金属层141和第一金属层143。栅极接触图案GCP的第一阻挡金属层141可以具有均匀的厚度，并且可以插置在第一金属层143与栅极金属图案115之间。栅极接触图案GCP可以具有与有源接触图案ACP1和ACP2的顶表面基本上共平面的顶表面。
第一蚀刻停止层151和第一层间电介质层153可以顺序地堆叠在层间绝缘层133上。第一蚀刻停止层151可以覆盖有源接触图案ACP1和ACP2的顶表面以及栅极接触图案GCP的顶表面。第一蚀刻停止层151可以包括例如硅氮化物(SiN)、硅氮氧化物(SiON)、硅碳化物(SiC)、硅碳氮化物(SiCN)或其组合。第一层间电介质层153可以包括其介电常数低于硅氧化物层的介电常数的电介质材料。
通路图案VP1和VP2可以形成在第一层间电介质层153和第一蚀刻停止层151中，并且可以连接到有源接触图案ACP1和ACP2。通路图案VP1和VP2可以包括不同于第一金属性材料的第二金属性材料，第二金属性材料可以具有比第一金属性材料的电阻率小的电阻率。例如，第二金属性材料可以包括铜或其合金。在本说明书中，铜合金可以意思是混合以极少量以下中的一种的铜：碳(C)、银(Ag)、钴(Co)、钽(Ta)、铟(In)、锡(Sn)、锌(Zn)、锰(Mn)、钛(Ti)、镁(Mg)、铬(Cr)、锗(Ge)、锶(Sr)、铂(Pt)、铝(Al)和锆(Zr)。通路图案VP1和VP2的每个可以包括第二阻挡金属层161和第二金属层163，第二阻挡金属层161可以插置在第二金属层163与有源接触图案ACP1或ACP2之间。
根据一些实施方式，通路图案VP1和VP2可以包括连接到第一有源接触图案ACP1的第一通路图案VP1、以及连接到第二有源接触图案ACP2的第二通路图案VP2。例如，第一通路图案VP1和第一有源接触图案ACP1可以在标准单元SC的每个的边缘处彼此电连接，第二通路图案VP2和第二有源接触图案ACP2可以在标准单元SC的每个的内部区域处彼此电连接。
根据一些实施方式，第一通路图案VP1的每个在第一有源接触图案ACP1上可以具有其长轴在第一方向D1上延伸的条形。例如，第一通路图案VP1可以具有比第一有源接触图案ACP1在第一方向D1上的宽度大的在第一方向D1上的长度。如俯视所观察地，第一通路图案VP1可以重叠栅极结构GS的一部分。第一通路图案VP1可以具有在第一方向D1上以第一距离d1与和第三器件隔离层107的侧壁对准的轴线间隔开的一个侧壁。
在一些实施方式中，相邻的标准单元SC的第一通路图案VP1可以隔着第三器件隔离层107彼此相邻。第一通路图案VP1可以在第一方向D1上以大于第三器件隔离层107的第二宽度W2的第二距离d2彼此间隔开。
第二蚀刻停止层171和第二层间电介质层173可以顺序地堆叠在第一层间电介质层153上。第二蚀刻停止层171和第二层间电介质层173可以覆盖第一通路图案VP1和第二通路图案VP2的顶表面。例如，第二蚀刻停止层171和第二层间电介质层173可以在第一通路图案VP1和第二通路图案VP2形成之后被形成。
在标准单元SC的每个处/中，布线图案CP可以设置在第二蚀刻停止层171和第二层间电介质层173中，并且可以连接到第一通路图案VP1和第二通路图案VP2。布线图案CP可以包括其电阻率小于第一金属性材料的电阻率的第三金属性材料。在一些实施方式中，第三金属性材料可以与第二金属性材料相同，并且可以包括例如铜或其合金。布线图案CP可以包括第三阻挡金属层181和第三金属层183。第三阻挡金属层181可以插置在布线图案CP的第三金属层183与第一通路图案VP1或第二通路图案VP2的第二金属层163之间。在该构造中，布线图案CP与通路图案VP1和VP2之间可以存在界面。
在一些实施方式中，布线图案CP可以将一个第一通路图案VP1连接到与所述一个第一通路图案VP1间隔开的另一个第一通路图案VP1，或者可以将第一通路图案VP1连接到第二通路图案VP2。布线图案CP的每个可以在第一方向D1上延伸，并且可以包括连接到第一有源接触图案ACP1的第一段。布线图案CP的每个还可以包括在第二方向D2上从第一段延伸的第二段。布线图案CP中的一个可以重叠有源接触图案ACP1和ACP2中的一个。
在一些实施方式中，布线图案CP的第一段可以跨越栅极结构GS。布线图案CP可以具有在第一方向D1上以大于第一距离d1的第三距离d3与和第三器件隔离层107的侧壁对准的轴线间隔开的一个侧壁。例如，布线图案CP的所述一个侧壁可以比第一通路图案VP1的所述一个侧壁与和第三器件隔离层107对准的轴线更远地间隔开。第一通路图案VP1的所述一个侧壁可以在第一方向D1上与和布线图案CP的所述一个侧壁对准的轴线间隔开。布线图案CP可以与第一通路图案VP1的一部分接触并与第二通路图案VP2的整个顶表面接触。例如，第一通路图案VP1的与布线图案CP接触的部分可以仅是第一通路图案VP1的第一部分，使得第一通路图案VP1的第二部分不接触布线图案CP。
标准单元SC的布线图案CP可以在第一方向D1上隔着第三器件隔离层107以第四距离d4彼此间隔开。第四距离d4可以大于第二距离d2。也就是，在第一方向D1上彼此相邻的布线图案CP之间的第四距离d4可以大于在第一方向D1上彼此相邻的第一通路图案VP1之间的第二距离d2。
第一电源线PL1和第二电源线PL2可以在第一方向D1上延伸，并且可以共同连接到标准单元SC。第一电源线PL1可以在第二方向D2上与第二电源线PL2间隔开。第一电源线PL1和第二电源线PL2通过通路图案VP1和VP2可以每个电连接到有源接触图案ACP1和ACP2中的至少对应的有源接触图案。
根据一些实施方式，即使栅极结构GS在节距上减小并且第三器件隔离层107在宽度上减小，也可以对在第一方向D1上彼此相邻的布线图案CP确保工艺余量。此外，由于第一通路图案VP1具有其长轴在第一方向D1上延伸的条形，可以在布线图案CP与第一通路图案VP1之间可靠地提供接触区域。
图4示出显示了根据本发明构思的示例实施方式的半导体器件的俯视图。图5示出沿图4的线I-I'截取的剖视图。图6示出显示了根据本发明构思的示例实施方式的半导体器件的俯视图。为了描述的简明，可以省略对与参照图2及3A至3D讨论的实施方式的技术特征相同的技术特征的描述。
参照图4和5，在俯视图中，与第三器件隔离层107相邻的第一通路图案VP1可以不重叠栅极结构GS。例如，第一通路图案VP1可以设置在第三器件隔离层107与其邻近的栅极结构GS之间。第一通路图案VP1可以具有小于第三器件隔离层107与其邻近的栅极结构GS之间的间隔S2的在第一方向D1上的宽度。
参照图6，半导体器件可以提供有通路图案，该通路图案包括连接到第一有源接触图案ACP1的第一通路图案VP1、连接到第二有源接触图案ACP2的第二通路图案VP2、以及连接到栅极接触图案GCP的第三通路图案VP3。第一至第三通路图案VP1、VP2和VP3可以每个具有其长轴在第一方向D1上延伸的条形。
在一些实施方式中，布线图案CP中的一个可以在第二方向D2上平行于第三器件隔离层107延伸，并且可以通过第一通路图案VP1电连接到第一有源接触图案ACP1。
或者，布线图案CP可以将与第三器件隔离层107相邻的第一通路图案VP1连接到与栅极结构GS连接的第三通路图案VP3。布线图案CP可以具有可比第一通路图案VP1的一个侧壁与第三器件隔离层107更远地间隔开并且可与第一通路图案VP1的一部分接触的一个侧壁。
图7、9和11示出显示了根据本发明构思的示例实施方式的半导体器件的一部分的俯视图。图8、10和12分别示出沿图7、9和11的线I-I'截取的剖视图。为了描述的简明，可以省略对与参照图2及3A至3D讨论的实施方式的技术特征相同的技术特征的描述。
参照图7和8，第一通路图案VP1中隔着第三器件隔离层107彼此相邻的第一第一通路图案VP1和第二第一通路图案VP1(即隔着第三器件隔离层107彼此相邻的一对第一通路图案VP1)可以以第二距离d2彼此间隔开，隔着第三器件隔离层107彼此相邻的布线图案CP可以以第四距离d4彼此间隔开。第四距离d4可以基本上等于或大于第二距离d2。
参照图9和10，第一通路图案VP1可以在第一方向D1上以第二距离d2彼此间隔开，布线图案CP可以以大于第二距离d2的第四距离d4彼此间隔开。此外，第一通路图案VP1的每个可以在第一方向D1上延伸并且可以重叠栅极结构GS的一部分。
如在俯视图中所观察地，布线图案CP的每个可以与第一通路图案VP1的一部分接触，并且可以不重叠第一有源接触图案ACP1。因为在布线图案CP之间提供了增大的间隔而且在布线图案CP与第一通路图案VP1之间确保了接触面积，所以即使标准单元SC在面积上减小，也可以对布线图案CP确保工艺余量。
参照图11和12，第一通路图案VP1的每个可以跨越至少一个栅极结构GS，并且可以从第一有源接触图案ACP1延伸到第二有源接触图案ACP2上。在该构造中，第一通路图案VP1的每个可以将第一有源接触图案ACP1电连接到第二有源接触图案ACP2。
图13示出显示了根据本发明构思的示例实施方式的半导体器件的俯视图。图14示出沿图13的线I-I'截取的剖视图。为了描述的简明，可以省略对与参照图2及3A至3D讨论的实施方式的技术特征相同的技术特征的描述。
参照图13和14，栅极结构GS可以在第二方向D2上延伸，同时跨越在第一方向D1上延伸的有源图案101。栅极结构GS可以具有基本相同的第一宽度W1，并且可以在第一方向D1上以第一间隔S1彼此相等地间隔开。
第四器件隔离层109可以在标准单元SC的边缘处在第一方向D1上将有源图案101彼此隔开。在一些实施方式中，第四器件隔离层109可以具有大于相邻的栅极结构GS之间的第一间隔S1的宽度W3。
虚设栅极结构DGS可以设置在标准单元SC的边缘处并且在第四器件隔离层109与有源图案101之间的边界处。虚设栅极结构DGS可以具有与栅极结构GS的堆叠结构相同的堆叠结构。
有源接触图案ACP1和ACP2可以连接到在栅极结构GS的每个的相反侧上的源极/漏极杂质层130。如上所讨论地，有源接触图案ACP1和ACP2可以包括位于第四器件隔离层109与其邻近的栅极结构GS之间的第一有源接触图案ACP1、以及位于栅极结构GS中彼此相邻的栅极结构GS之间的第二有源接触图案ACP2。
在一些实施方式中，通路图案VP可以连接到有源接触图案ACP1和ACP2，并且通路图案VP中的一个可以将多个(例如一对)第二有源接触图案ACP2彼此电连接。通路图案VP中的所述一个可以在第一方向D1上延伸以跨越栅极结构GS，并且可以与所述多个第二有源接触图案ACP2直接接触。
如上所讨论地，有源接触图案ACP1和ACP2可以包括第一金属性材料，通路图案VP可以包括其电阻率小于第一金属性材料的电阻率的第二金属性材料。
根据本发明构思的示例实施方式，与通路图案相比，布线图案可以在第一方向上与标准单元之间的边界处的器件隔离层更远地间隔开。因此，即使标准单元之间的间隔由于器件隔离层的宽度减小而减小，也对布线图案确保了工艺余量。通路图案可以具有其长轴在第一方向上延伸的条形，使得可以在布线图案与通路图案之间可靠地提供接触区域。
连接到标准单元的通路图案和布线图案可以由具有更低电阻率的金属性材料形成，从而降低连接到标准单元的连接线之间的电阻。
以上公开的主题将被认为是说明性的而非限制性的，并且所附权利要求旨在覆盖落入真正的精神和范围内的所有这样的修改、加强及另外的实施方式。因此，在法律允许的最大限度上，范围将由所附权利要求及其等同物的最宽可允许的解释确定，并且不应受前面详细描述的约束或限制。
本申请要求享有2017年6月14日在韩国知识产权局提交的韩国专利申请第10-2017-0075059号的优先权，其全部内容通过引用合并于此。

Claims (20)

1.一种半导体器件，包括：
多个有源图案，所述多个有源图案在第一方向上延伸；
多个栅极结构，所述多个栅极结构跨越所述有源图案并且在交叉所述第一方向的第二方向上延伸；
器件隔离层，其在所述多个栅极结构中相邻的第一栅极结构与第二栅极结构之间在所述第二方向上延伸；
多个接触图案，所述多个接触图案在所述多个栅极结构与所述器件隔离层之间；
多个连接图案，所述多个连接图案分别连接到所述多个接触图案，其中所述器件隔离层在所述多个连接图案之间，以及其中所述多个连接图案在所述第一方向上以第一距离彼此间隔开；以及
多个布线图案，所述多个布线图案分别连接到所述多个连接图案，其中所述器件隔离层在所述多个布线图案之间，以及其中所述多个布线图案在所述第一方向上以比所述第一距离长的第二距离彼此间隔开。
2.根据权利要求1所述的半导体器件，
其中所述器件隔离层包括比所述第一距离短的宽度，以及
其中所述器件隔离层在包括第一N阱区和第一P阱区的第一单元与包括第二N阱区和第二P阱区的第二单元之间的边界处。
3.根据权利要求1所述的半导体器件，其中所述器件隔离层包括比所述多个栅极结构中的一个的宽度的两倍短的宽度。
4.根据权利要求1所述的半导体器件，
其中所述器件隔离层在所述多个有源图案中的一个中，以及
其中所述器件隔离层包括比所述多个有源图案中的所述一个的顶表面低的顶表面、以及比所述多个有源图案中的所述一个的所述顶表面高的顶表面。
5.根据权利要求1所述的半导体器件，其中所述多个连接图案分别在所述第一方向上延伸并且重叠所述多个栅极结构的至少一部分。
6.根据权利要求1所述的半导体器件，其中所述多个布线图案分别在所述第一方向上延伸并且接触所述多个连接图案。
7.根据权利要求1所述的半导体器件，其中所述多个布线图案中的一个重叠所述多个接触图案中的一个。
8.根据权利要求1所述的半导体器件，
其中所述多个接触图案包括第一金属性材料，以及
其中所述多个连接图案包括第二金属性材料，所述第二金属性材料包括比所述第一金属性材料的电阻率低的电阻率。
9.根据权利要求8所述的半导体器件，
其中所述多个布线图案包括所述第二金属性材料，以及
其中所述半导体器件还包括在所述多个布线图案与所述多个连接图案之间的界面。
10.一种半导体器件，包括：
多个有源图案，所述多个有源图案在第一方向上延伸；
器件隔离层，其跨越所述多个有源图案并且在交叉所述第一方向的第二方向上延伸；
栅极结构，其与所述器件隔离层间隔开并且在所述第二方向上延伸以跨越所述多个有源图案；
多个源极/漏极杂质层，所述多个源极/漏极杂质层与所述栅极结构的相反侧相邻；
接触图案，其连接到所述多个源极/漏极杂质层中的在所述器件隔离层与所述栅极结构之间的一个；
连接图案，其连接到所述接触图案并且在所述第一方向上以第一距离与和所述器件隔离层对准的轴线间隔开；以及
布线图案，其连接到所述连接图案并且在所述第一方向上以第二距离与和所述器件隔离层对准的所述轴线间隔开，所述第二距离比所述第一距离长。
11.根据权利要求10所述的半导体器件，
其中所述器件隔离层包括比所述器件隔离层与所述栅极结构之间在所述第一方向上的距离短的在所述第一方向上的宽度，以及
其中所述栅极结构与所述器件隔离层相邻。
12.根据权利要求10所述的半导体器件，其中：
所述连接图案在所述第一方向上延伸并且重叠所述栅极结构；
所述器件隔离层在包括第一N阱区和第一P阱区的第一单元与包括第二N阱区和第二P阱区的第二单元之间的边界处；
所述连接图案包括在所述第一单元中的第一连接图案；
所述半导体器件还包括在所述第二单元中的第二连接图案；
所述轴线包括和所述器件隔离层的第一侧对准的第一轴线；以及
所述第二连接图案在所述第一方向上以所述第一距离与平行于所述第一轴线并且和所述器件隔离层的第二侧对准的第二轴线间隔开。
13.根据权利要求10所述的半导体器件，
其中所述布线图案接触所述连接图案的一部分，以及
其中所述连接图案与所述半导体器件的第一单元与第二单元之间的边界相邻。
14.根据权利要求10所述的半导体器件，
其中所述接触图案包括第一金属性材料，以及
其中所述连接图案和所述布线图案包括不同于所述第一金属性材料的第二金属性材料。
15.一种半导体器件，包括：
衬底，其包括含第一N阱区和第一P阱区的第一单元区、以及含第二N阱区和第二P阱区的第二单元区；
栅极结构，其在所述衬底的所述第一单元区上；
在所述衬底上分别与所述栅极结构的相反的第一侧和第二侧相邻的第一源极/漏极杂质区和第二源极/漏极杂质区；
第三源极/漏极杂质区，其在所述衬底的所述第二单元区上；
第一接触，其连接到所述第一源极/漏极杂质区并且包括第一金属性材料；
第一连接器，其连接到所述第一接触并且延伸以重叠所述栅极结构的至少一部分，
其中所述第一连接器包括不同于所述第一金属性材料的第二金属性材料；
第二接触，其连接到所述第三源极/漏极杂质区；
第二连接器，其连接到所述第二接触；
第一布线图案，其连接到所述第一连接器；以及
第二布线图案，其连接到所述第二连接器，
其中所述第一布线图案和所述第二布线图案以第一距离彼此间隔开，所述第一距离比所述第一连接器和所述第二连接器彼此间隔开的第二距离长。
16.根据权利要求15所述的半导体器件，还包括在所述衬底中的器件隔离区，
其中所述第一接触在所述器件隔离区与所述栅极结构之间，以及
其中所述器件隔离区在所述第一单元区与所述第二单元区之间的边界处。
17.根据权利要求15所述的半导体器件，
其中所述半导体器件还包括连接到所述第二源极/漏极杂质区的第三接触，以及
其中所述第一连接器将所述第一接触和所述第三接触彼此连接。
18.根据权利要求15所述的半导体器件，
其中所述第一布线图案包括所述第二金属性材料。
19.根据权利要求18所述的半导体器件，
其中所述第一布线图案接触所述第一连接器的第一部分，以及
其中所述第一连接器的第二部分不接触所述第一布线图案。
20.根据权利要求18所述的半导体器件，
其中所述第一连接器包括：
第一阻挡金属层；和
在所述第一阻挡金属层上的第一金属层，以及
其中所述第一布线图案包括：
接触所述第一金属层的第二阻挡金属层；和
在所述第二阻挡金属层上的第二金属层。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102620595B1 (ko) 2018-01-22 2024-01-03 삼성전자주식회사 소자분리막을 갖는 반도체 소자 및 그 제조 방법
KR20210018669A (ko) * 2019-08-08 2021-02-18 삼성전자주식회사 비아 및 배선을 포함하는 반도체 소자
KR20220032924A (ko) * 2020-09-08 2022-03-15 삼성전자주식회사 모스 트랜지스터들을 포함하는 집적 회로 소자
CN113594174B (zh) * 2021-08-10 2023-12-05 长江存储科技有限责任公司 三维存储器及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101221970A (zh) * 2006-12-26 2008-07-16 三星电子株式会社 具有在相邻单元之间共用的相变材料图案的相变存储器件和包括该相变存储器的电子产品
KR20100030015A (ko) * 2008-09-09 2010-03-18 주식회사 하이닉스반도체 반도체 소자의 제조방법
CN102148197A (zh) * 2010-02-09 2011-08-10 三星电子株式会社 半导体器件的制造方法
CN103779392A (zh) * 2012-10-18 2014-05-07 成一电子股份有限公司 晶体管布局装置
KR20160039530A (ko) * 2014-10-01 2016-04-11 삼성전자주식회사 시스템 온 칩
CN106057808A (zh) * 2015-04-14 2016-10-26 三星电子株式会社 半导体器件及制造其的方法

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW468273B (en) * 1997-04-10 2001-12-11 Hitachi Ltd Semiconductor integrated circuit device and method for manufacturing the same
JP2000243931A (ja) * 1998-12-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
JP2002164428A (ja) * 2000-11-29 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
JP4353393B2 (ja) * 2001-06-05 2009-10-28 株式会社ルネサステクノロジ 半導体集積回路装置
JP3790469B2 (ja) * 2001-12-21 2006-06-28 富士通株式会社 半導体装置
US6670642B2 (en) * 2002-01-22 2003-12-30 Renesas Technology Corporation. Semiconductor memory device using vertical-channel transistors
JP3779243B2 (ja) * 2002-07-31 2006-05-24 富士通株式会社 半導体装置及びその製造方法
CN100352036C (zh) * 2002-10-17 2007-11-28 株式会社瑞萨科技 半导体器件及其制造方法
KR100503519B1 (ko) * 2003-01-22 2005-07-22 삼성전자주식회사 반도체 장치 및 그 제조방법
JP2005026538A (ja) * 2003-07-04 2005-01-27 Renesas Technology Corp 半導体集積回路装置の製造方法
JP2008210893A (ja) * 2007-02-23 2008-09-11 Fujitsu Ltd 半導体装置とその製造方法
DE112007003638T5 (de) * 2007-09-10 2010-08-12 Fujitsu Ltd., Kawasaki Prozess zum Herstellen einer siliziumhaltigen Beschichtung, siliziumhaltige Beschichtung und Halbleitervorrichtung
JP5135002B2 (ja) * 2008-02-28 2013-01-30 ルネサスエレクトロニクス株式会社 半導体装置
KR101660491B1 (ko) * 2010-04-09 2016-09-27 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP5537657B2 (ja) * 2010-06-24 2014-07-02 富士通株式会社 配線構造の形成方法、半導体装置の製造方法、基板処理装置
JP5847549B2 (ja) * 2011-11-16 2016-01-27 ルネサスエレクトロニクス株式会社 半導体装置
US8625334B2 (en) 2011-12-16 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell
US9041115B2 (en) 2012-05-03 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for FinFETs
US8723268B2 (en) 2012-06-13 2014-05-13 Synopsys, Inc. N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
US9461143B2 (en) * 2012-09-19 2016-10-04 Intel Corporation Gate contact structure over active gate and method to fabricate same
KR20140099743A (ko) * 2013-02-04 2014-08-13 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9443851B2 (en) 2014-01-03 2016-09-13 Samsung Electronics Co., Ltd. Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same
US9553028B2 (en) 2014-03-19 2017-01-24 Globalfoundries Inc. Methods of forming reduced resistance local interconnect structures and the resulting devices
US9496179B2 (en) 2014-08-25 2016-11-15 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor devices
KR101679684B1 (ko) 2014-08-25 2016-11-29 삼성전자주식회사 반도체 소자의 제조방법
KR102193633B1 (ko) * 2014-12-30 2020-12-21 삼성전자주식회사 듀얼 포트 에스램 장치 및 그 제조 방법
US9425252B1 (en) 2015-01-30 2016-08-23 Globalfoundries Inc. Process for single diffusion break with simplified process
US9431396B2 (en) 2015-01-30 2016-08-30 Globalfoundries Inc. Single diffusion break with improved isolation and process window and reduced cost
KR102317651B1 (ko) * 2015-04-14 2021-10-27 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US20160336183A1 (en) 2015-05-14 2016-11-17 Globalfoundries Inc. Methods, apparatus and system for fabricating finfet devices using continuous active area design
US20170018623A1 (en) * 2015-07-17 2017-01-19 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR102358571B1 (ko) * 2015-07-29 2022-02-07 삼성전자주식회사 집적 회로 및 표준 셀 라이브러리
KR102399465B1 (ko) * 2015-10-23 2022-05-18 삼성전자주식회사 로직 반도체 소자
KR102413371B1 (ko) * 2015-11-25 2022-06-28 삼성전자주식회사 반도체 소자
US9679965B1 (en) * 2015-12-07 2017-06-13 Samsung Electronics Co., Ltd. Semiconductor device having a gate all around structure and a method for fabricating the same
US9543298B1 (en) 2016-03-11 2017-01-10 Globalfoundries Inc. Single diffusion break structure and cuts later method of making
US9536991B1 (en) 2016-03-11 2017-01-03 Globalfoundries Inc. Single diffusion break structure
US9786557B1 (en) * 2016-04-12 2017-10-10 International Business Machines Corporation Two-dimensional self-aligned super via integration on self-aligned gate contact
US9589845B1 (en) 2016-05-23 2017-03-07 International Business Machines Corporation Fin cut enabling single diffusion breaks
KR102524806B1 (ko) * 2016-08-11 2023-04-25 삼성전자주식회사 콘택 구조체를 포함하는 반도체 소자
CN109952653B (zh) * 2016-11-14 2022-05-31 东京毅力科创株式会社 形成用于纳米线fet器件的栅极间隔件的方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101221970A (zh) * 2006-12-26 2008-07-16 三星电子株式会社 具有在相邻单元之间共用的相变材料图案的相变存储器件和包括该相变存储器的电子产品
KR20100030015A (ko) * 2008-09-09 2010-03-18 주식회사 하이닉스반도체 반도체 소자의 제조방법
CN102148197A (zh) * 2010-02-09 2011-08-10 三星电子株式会社 半导体器件的制造方法
CN103779392A (zh) * 2012-10-18 2014-05-07 成一电子股份有限公司 晶体管布局装置
KR20160039530A (ko) * 2014-10-01 2016-04-11 삼성전자주식회사 시스템 온 칩
CN106057808A (zh) * 2015-04-14 2016-10-26 三星电子株式会社 半导体器件及制造其的方法

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