CN108847263B - 具有嵌入式内存的系统级封装内存模块 - Google Patents

具有嵌入式内存的系统级封装内存模块 Download PDF

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CN108847263B
CN108847263B CN201810354652.3A CN201810354652A CN108847263B CN 108847263 B CN108847263 B CN 108847263B CN 201810354652 A CN201810354652 A CN 201810354652A CN 108847263 B CN108847263 B CN 108847263B
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memory
memory circuit
circuit
package
substrate
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CN108847263A (zh
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甘万达
卢超群
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Etron Technology Inc
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Etron Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
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    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
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Abstract

本发明公开了一种具有嵌入式内存的系统级封装内存模块。所述系统级封装内存模块包含一非内存电路、一基板和一内存电路。所述非内存电路具有一第一部分和一第二部分。所述基板具有一窗口以及所述基板电连接所述非内存电路的第二部分。所述内存电路设置于所述基板的窗口且电连接所述非内存电路的第一部分，以及所述内存电路和所述基板之间没有直接的金属连接。因为所述系统级封装内存模块可被客制化以因应不同的内存电路和非内存电路，所以所述系统级封装内存模块具有优化的效能、效率以及成本的一组合。

Description

具有嵌入式内存的系统级封装内存模块
原申请案的申请日为2014年10月23日，申请号为201410573292.8，以及发明名称为“具有嵌入式内存的系统级封装内存模块”。
技术领域
本发明涉及一种具有嵌入式内存的系统级封装内存模块。
背景技术
一般说来，内存电路通常会基于特定工业标准(例如联合电子设备工程会议(Joint Electronic Device Engineering Council,JEDEC))而被设计成独立于应用逻辑电路的标准内存电路。也就是说基于特定工业标准，内存电路是被设计成适用于各种不同应用逻辑电路的标准内存电路。
在应用逻辑电路中，应用逻辑电路需要内存控制器以控制标准内存电路与应用逻辑电路之间的沟通。因为内存控制器必须和各种不同的标准内存电路沟通，所以在应用逻辑电路中的内存控制器倾向被设计具有次佳化的效能、效率以及成本，以因应各种不同的标准内存电路。
然而，现在业界倾向于提供内存电路的已知良好芯片(known good die)以方便和应用逻辑电路整合于系统级封装(System in Package,SIP)模块。因为应用逻辑电路仅需和内存电路的确认好芯片沟通，所以如果应用逻辑电路中的内存控制器还是被设计成具有次佳化的效能、效率以及成本，以因应各种不同的标准内存电路，则系统级封装模块将不会发挥最大效能。
发明内容
本发明的一实施例公开一种具有嵌入式内存的系统级封装内存模块。所述系统级封装内存模块包含一非内存电路、一内存控制器、一内存电路和一基板，其中所述非内存电路、所述内存控制器和所述内存电路是堆栈后共同封装于所述基板之上，所述内存电路与所述内存控制器是形成在同一片半导体芯片上，且所述内存电路和所述基板之间没有直接的金属连接。
本发明的另一实施例公开一种具有嵌入式内存的系统级封装内存模块。所述系统级封装内存模块包含一非内存电路、一基板和一内存电路。所述非内存电路具有一第一部分和一第二部分。所述基板具有一窗口以及所述基板电连接所述非内存电路的第二部分。所述内存电路设置于所述基板的窗口且电连接所述非内存电路的第一部分。所述内存电路和所述基板之间没有直接的金属连接，在所述内存电路和所述基板之间存在间隙，以及所述间隙被树脂填充。
本发明公开一种具有嵌入式内存的系统级封装内存模块。所述系统级封装内存模块是整合一内存电路(嵌入式动态随机存取内存)、一非内存电路(逻辑电路)和一基板于一系统级封装内，所以本发明可缩小所述系统级封装内存模块的面积。另外，因为本发明的系统级封装内存模块可被客制化以因应不同的内存电路(嵌入式动态随机存取内存)和非内存电路(逻辑电路)，所以本发明的系统级封装内存模块具有优化的效能、效率以及成本的一组合。
附图说明
图1是本发明的一第一实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图2是本发明的一第二实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图3是本发明的一第三实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图4A是本发明的一第四实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图4B是说明系统级封装内存模块的爆炸示意图。
图4C是本发明的一第五实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图5是本发明的一第六实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图6是本发明的一第七实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图7是本发明的一第八实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图8是本发明的一第九实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图9是本发明的一第十实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图10是本发明的一第十一实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图11是本发明的一第十二实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图12是本发明的一第十三实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图13A是本发明的一第十四实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
图13B是本发明的一第十五实施例公开一种具有嵌入式内存的系统级封装内存模块的示意图。
其中，附图标记说明如下：
100、200、300、400、500、600、700、800、 系统级封装内存模块
900、1000、1100、1200、1300、1400、450
102、202、302 高速缓存内存电路
104、204、304 内存控制器
106、206、306 动态随机存取内存电路
108、208、406、506、606、706、1006 基板
310 第一可重构总线
312 外部中央处理器
314 第二可重构总线
3042、9102 模式缓存器
3044、9104 配置电路
3046、9106 时钟发生器
30442、91042 输入/输出宽度控制器
30444、91044 输出单元
30446、91046 输入单元
402、502、602、704、804、904、1004、1106、 内存电路
1208、1304
404、504、604、702、802、902、1010、1104、 非内存电路
1204、1306
4022 第三电接点
4042 第一电接点
4044 第二电接点
4062 第四电接点
4064 第五电接点
4066、7062 窗口
508 引线键合
510、608 成型材料
6044、408、412 凸点结构
8022、9022 并行转串行总线可编程中介单元
8024、9024、9026 可重构总线
9108 并行/串行控制器
9028、8026 高速串行总线
1002、1008、1102 树脂
1202 第一散热器
1206 第二散热材料
1302 额外的内存
1308 电接点
C1-C4 核
DVFS 动态电压频率调整单元
eDRAM 嵌入式动态随机存取内存
ECC 错误校正码单元
L1、L2、L3 高速缓存内存
MMU 高速缓存管理单元
TSV、6042、410 穿硅通孔
具体实施方式
请参照图1，图1是本发明的一第一实施例公开一种具有嵌入式内存(embeddedmemory)的系统级封装(system-in-package,SIP)内存模块100的示意图。如图1所示，系统级封装内存模块100包含一高速缓存内存电路102，一内存控制器104，一动态随机存取内存(Dynamic Random Access Memory,DRAM)电路106，以及一基板108，其中动态随机存取内存电路106(在系统级封装内存模块100中是主存储器)是一动态随机存取内存(DynamicRandom Access Memory,DRAM)，或是多个组装或堆栈在一起的动态随机存取内存。另外，高速缓存内存电路102、内存控制器104和动态随机存取内存电路106是共同封装于基板108之上，且高速缓存内存电路102与内存控制器104是形成在同一片半导体芯片上，其中所述同一片半导体芯片是根据一互补金属氧化物半导体(complementary metal-oxide-semiconductor,CMOS)制程制作的硅芯片。高速缓存内存电路102可以是一静态随机存取内存(Static Random Access Memory,SRAM)或是具有比动态随机存取内存电路106的操作速度或带宽更高的动态随机存取记忆。例如，高速缓存内存电路102的带宽或操作速度是动态随机存取内存电路106的的三倍或以上。高速缓存内存电路102和动态随机存取内存电路106可分别设置于基板108之上，或互相堆栈之后在设置于基板108之上。基板108可以是一软性有机基板或是一常规印刷电路板(例如，球栅数组封装(Ball Grid Array,BGA)基板。
如图1所示，内存控制器104是高速缓存内存电路102的一部分。但在本发明的另一实施例中，内存控制器104是独立在高速缓存内存电路102之外。如图1所示，内存控制器104包含一高速缓存管理单元MMU、一动态电压频率调整单元DVFS以及一错误校正码单元ECC。根据系统级封装内存模块100的指令，高速缓存管理单元MMU不是控制读取自(或写入至)高速缓存内存电路102就是控制读取自(或写入至)动态随机存取内存电路106的输出数据(或输入数据)。错误校正码单元ECC可矫正储存在高速缓存内存电路102或动态随机存取内存电路106内的数据错误。动态电压频率调整单元DVFS可动态改变系统级封装内存模块100的操作电压、操作频率及总线宽度的一组合。
请参照图2，图2是本发明的一第二实施例公开一种具有嵌入式内存的系统级封装内存模块200的示意图。如图2所示，动态随机存取内存电路206(主存储器)包含多个堆栈在一起的动态随机存取内存，以及动态随机存取内存电路206是设置在高速缓存内存电路202之上且通过穿硅通孔(Through Silicon Via,TSV)电连接高速缓存内存电路202。如图2所示，高速缓存内存电路202包含内存控制器204且设置在基板208之上，其中高速缓存内存电路202的带宽或操作速度是动态随机存取内存电路206的三倍或以上，然而动态随机存取内存电路206的储存容量是高速缓存内存电路202的储存容量的三倍。另外，在存取动态随机存取内存电路206和高速缓存内存电路202同样次数的情况下，动态随机存取内存电路206的功耗是高速缓存内存电路202的功耗的三倍。另外，本发明并不受限于高速缓存内存电路202的带宽或操作速度是动态随机存取内存电路206的三倍或以上且动态随机存取内存电路206的储存容量是高速缓存内存电路202的储存容量的三倍或以上。
请参照图3，图3是本发明的一第三实施例公开一种具有嵌入式内存的系统级封装内存模块300的示意图。如图3所示，内存控制器304的动态电压频率调整单元DVFS可通过一介于内存控制器304和动态随机存取内存电路306之间的第一可重构总线(例如128、256或更多位宽度的总线)310存取动态随机存取内存电路306，以及转换第一可重构总线数据为另一第二可重构总线数据至一外部中央处理器(或其他逻辑电路)312。动态电压频率调整单元DVFS内的模式缓存器3042可在相对快的往返时间内重构(reconfigure)第一可重构总线310或第二可重构总线314所需的内存信道、粒度(granularity)、频率、数据电压摆幅和总线宽度的一组合。例如，当4个记忆深度是512M和总线宽度是32位的动态随机存取内存芯片堆栈在动态随机存取内存电路306时，动态随机存取内存电路306可根据模式缓存器3042内的内容，设定为具有记忆深度是1G和总线宽度是64位或是记忆深度是512M和总线宽度是128位的动态随机存取内存电路306。
如图3所示，动态电压频率调整单元DVFS另包含一配置电路3044和一时钟发生器3046。如图3所示，模式缓存器3042可通过外部中央处理器(或其他逻辑电路)312设定，以及配置电路3044可根据模式缓存器3042内的内容，控制与重构介于动态随机存取内存电路306与内存控制器304之间的第一可重构总线310。例如，当4个记忆深度是512M和总线宽度是32位的动态随机存取内存芯片堆栈在动态随机存取内存电路306时，第一可重构总线310的总线宽度可被设定为32位、64位或128位，以及其记忆深度可分别对应地设定为2G、1G或512M。
如图3所示，配置电路3044包含一输入/输出宽度控制器30442、一输出单元30444和一输入单元30446。输入/输出宽度控制器30442可存取模式缓存器3042内的内容以及配置第一可重构总线310或第二可重构总线314。因此，本发明可实现不同总线宽度的配置。例如，在本发明的一实施例中，第一可重构总线310的总线宽度被设定为M位以及在第一可重构总线310上的电压摆幅(介于逻辑电平“1”信号和逻辑电平“0”信号之间的电压差)被设定为1.8V，第二可重构总线314的总线宽度被设定为N位以及在第二可重构总线314上的电压摆幅被设定为1.2V，配置电路3044内的输出单元30444接收第一可重构总线310的M位数据，以及根据时钟发生器3046所产生的时钟信号，输出N位数据至第二可重构总线314。此时，输出单元30444也可将M位数据的电压摆幅从1.8V降低至1.2V(或更低)。因此，输出单元30444可通过第一可重构总线310从动态随机存取内存电路306(或高速缓存内存电路302)接收具有电压摆幅1.8V的M位数据，以及产生具有电压摆幅1.2V的N位数据并通过介于外部中央处理器312和内存控制器304之间的第二可重构总线314传送至外部中央处理器312。
另一方面，如图3所示，配置电路3044的输入单元30446是用以从外部中央处理器312通过第二可重构总线314接收具有1.2V电压摆幅的并行N位数据，转换具有1.2V电压摆幅的并行N位数据为具有1.8V电压摆幅的并行M位数据至第一可重构总线310，以及通过第一可重构总线310写入具有1.8V电压摆幅的并行M位数据至动态随机存取内存电路306(或高速缓存内存电路302)。
此时，第一可重构总线310或第二可重构总线314的操作频率根据模式缓存器3042的内容也是可变的，以及动态电压频率调整单元DVFS内的时钟发生器3046可控制第一可重构总线310或第二可重构总线314的参考频率。
请参照图4A-图4C，图4A是本发明的一第四实施例公开一种具有嵌入式内存的系统级封装内存模块400的示意图，图4B是说明系统级封装内存模块400的爆炸示意图，以及图4C是本发明的一第五实施例公开一种具有嵌入式内存的系统级封装内存模块450的示意图。如图4A所示，系统级封装内存模块400是有关于具有嵌入式动态随机存取内存的双芯片平板(Dual Die Flat,DDF)球栅数组封装(Ball Grid Array,BGA)，其中系统级封装内存模块400包含一内存电路402、一非内存电路404和一基板406。内存电路402可以是一已知良好芯片内存(known good die memory,KGDM)或是多个组装或堆栈在一起的已知良好芯片内存。非内存电路404可以是一逻辑电路，例如一中央处理器。基板406可以是一软性有机基板或是一常规印刷电路板，例如球栅数组封装(Ball Grid Array,BGA)基板。
非内存电路(或逻辑电路)404具有一中央部分和一周边部分。如图4B所示，非内存电路404的多个第一电接点(electrical contact)4042和多个第二电接点4044是分别设置在中央部分和周边部分，其中多个第一电接点4042和多个第二电接点4044中的每一电接点可以是锡球或铜柱。如图4B所示，内存电路402包含设置在其本身一边的多个第三电接点4022，以及基板406也包含设置在其本身一边的多个第四电接点4062和在其本身另一边的多个第五电接点4064。如图4B所示，因为多个第一电接点4042电连接于多个第三电接点4022，所以内存电路402可电连接于非内存电路404的中央部分，以及因为多个第二电接点4044电连接于多个第四电接点4062，所以基板406可电连接于非内存电路404的周边部分。因此，如图4A所示，内存电路402是设置在非内存电路404的中央部分之下以及基板406是设置在非内存电路404的周边部分之下。
如图4B所示，基板406另包含一中空的空间(或窗口)4066，其中内存电路402是设置在基板406的中空的空间以电连接非内存电路404。因此，基板406和内存电路402都是设置在非内存电路404的相同一边。如此，如图4A所示，内存电路402和基板406之间并不会有直接的金属连接。另外，系统级封装内存模块400可设置在一外部电路板(未绘示于图4B)之上且通过设置在基板406的多个第五电接点4064电连接所述外部电路板。
如图4C所示，系统级封装内存模块450的内存电路402是设置在非内存电路404之上并通过一面对面的凸点结构(face-to-face bumping structure)408电连接非内存电路404以及通过面对面的凸点结构(face-to-face bumping structure)408和穿硅通孔(TSV)410电连接基板406。系统级封装内存模块450的非内存电路404则是通过另一面对面的凸点结构412电连接基板406。
请参照图5，图5是本发明的一第六实施例公开一种具有嵌入式内存的系统级封装内存模块500的示意图。如图5所示，系统级封装内存模块500的非内存电路504的主动组件区(active device area)表面与基板506之间具有一引线键合(wire-bond)508，以及内存电路502(嵌入式动态随机存取内存)可通过面对面的凸点结构(face-to-face bumpingstructure)电连接非内存电路504(逻辑电路)。所述凸点结构是有关于焊接或凸点制程，其中所述焊接或凸点制程包含焊料凸点步骤，铜对铜凸点或其他类似的凸点制程步骤。另外，在内存电路502(嵌入式动态随机存取内存)和基板506的部分的上方可形成一成型材料510，其中成型材料510可覆盖内存电路502(嵌入式动态随机存取内存)和非内存电路504(逻辑电路)。另外，非内存电路504、一内存控制器和内存电路502是共同封装于基板506之上，且内存电路502与所述内存控制器是形成在同一片半导体芯片上。
请参照图6，图6是本发明的一第七实施例公开一种具有嵌入式内存的系统级封装内存模块600的示意图。如图6所示，非内存电路604(逻辑电路)具有穿硅通孔(TSV)6042，其中非内存电路604(逻辑电路)的主动组件区是通过凸点结构6044电连接基板606。图6所述的凸点结构6044包含焊料凸点，铜对铜凸点或其他类似的凸点制程所产生的凸点。内存电路602(嵌入式动态随机存取内存)可通过穿硅通孔6042和凸点结构6044电连接非内存电路604(逻辑电路)的背面(硅基板)。另外，在内存电路602(嵌入式动态随机存取内存)的上方和基板606的部分可形成一成型材料608，其中成型材料608可覆盖内存电路602(嵌入式动态随机存取内存)和非内存电路604(逻辑电路)。另外，在本发明的另一实施例中，内存电路602(嵌入式动态随机存取内存)的顶部或非内存电路604(逻辑电路)的部分可以是没有成型材料608覆盖的开放空间。另外，散热片或散热器可设置在内存电路602(嵌入式动态随机存取内存)的顶部或非内存电路604(逻辑电路)的部分的上方以使内存电路602(嵌入式动态随机存取内存)或非内存电路604(逻辑电路)在操作状态时散热更有效率防止过热发生。
请参照图7，图7是本发明的一第八实施例公开一种具有嵌入式内存的系统级封装内存模块700的示意图。如图7所示，系统级封装内存模块700的非内存电路702是一多核心中央处理器，例如英特尔的Haswell中央处理器(4核心中央处理器)。非内存电路702的4核C1-C4中的每一核可包含内部层级1高速缓存内存L1与层级2高速缓存内存L2，以及非内存电路702另包含一额外可被4核C1-C4中的每一核分享的内部层级3高速缓存内存L3(如图7所示)。系统级封装内存模块700的内存电路704可以是一嵌入式动态随机存取内存芯片或是多个堆栈在一起的嵌入式动态随机存取内存芯片，其中内存电路704可作为非内存电路702的一外部层级4高速缓存内存。如图7所示，基板706是一具有窗口7062的球栅数组封装基板，以及内存电路704是设置在窗口7062以电连接非内存电路702。在本发明的另一实施例中，非内存电路702的多核心(4核C1-C4)可具有多个计算功能，其中非内存电路702的多核心中的几个核心是作为一般目的的计算用途(例如中央处理器的核心等用途)以及非内存电路702的多核心中的另几个核心是作为绘图、显示或高带宽计算用途(例如绘图处理器的核心等用途)。内存电路704可被分割成一些工作信道，其中每一信道的固定数目的位是在给定的硬件配置下根据最后一级的高速缓存内存的工作负载定义。在本发明的另一实施例中，内存电路704包含多个内存数组，其中多个所述内存数组可根据非内存电路702内中央处理器核心或绘图处理器核心的每一核心的工作负载，被动态地分配到非内存电路702的多核心中的不同核心。例如有超过50％-80％的内存数组是根据来自不同的软件程序(也就是说应用程序)的工作负载被动态地分配至一或多个绘图处理器核心，其中一或多个中央处理器应所述根据较轻的工作负载需求占用少于50％-80％的内存数组。由于多个所述内存数组可根据非内存电路702内中央处理器核心或绘图处理器核心的每一核心的工作负载被动态地分配到不同核心，所以内存电路704的高速缓存机制可节省内存电路704的待机功耗和运算功耗以及延长常见电子装置(例如笔记本电脑、手持式计算装置、智能型手机、平板计算机或通信装置)内的电池寿命。为了在系统级封装内存模块700的制造过程中节省内存电路704的成本，内存电路704内的一或多个内存数组可被内存电路704内的一或多个缓存器关闭(disabled)，或可被内存电路704外的一或多个缓存器关闭(也就是说被另一电路内的一或多个缓存器关闭)。在本发明的另一实施例中，内存电路704包含一或多个内存数组，其中所述或多个所述内存数组是用于伴随数据高速缓存内存数组的「标记内存(Tagmemory)」用途。在本发明的另一实施例中，内存电路704包含一控制逻辑模块，其中所述控制逻辑模块是用于高速缓存(Cache)及/或标记内存(Tag memory)的控制。当内存电路704被中央处理器核心或绘图处理器核心存取(读取或写入)时，所述控制逻辑模块可安排高速缓存的选取/未选取程序。内存电路704另包含一或多个用以较高速度读取或写入程序的静态随机存取内存数组，例如一标记内存可用以提升伴随动态随机存取内存数组的高速缓存内存的读取/写入速度效能，或者可被用作控制缓存器以动态控制多个所述内存数组对中央处理器核心/绘图处理器核心的分配、操作电压准位或操作频率。内存电路704另包含一错误校正码单元电路模块，其中所述错误校正码单元电路模块是用以回复在读取/写入过程中的动态错误，或者可被用以回复在半导体的制程中所产生的缺陷位或数组。如此，内存电路704即可同时具有较高良率与较低成本。
请参照图8，图8是本发明的一第九实施例公开一种具有嵌入式内存的系统级封装内存模块800的示意图。如图8所示，系统级封装内存模块800包含一并行转串行总线可编程中介单元8022，其中并行转串行总线可编程中介单元8022可通过介于并行转串行总线可编程中介单元8022和内存电路804之间的可重构总线8024(例如128、256或更多位宽度的总线)存取内存电路804以及转换宽总线数据为高速串行总线数据。另外，并行转串行总线可编程中介单元8022可通过高速串行总线8026传送所述高速串行总线数据至非内存电路802。在并行转串行总线可编程中介单元8022内的模式缓存器可在相对快的往返时间内重构内存电路804所需内存信道、粒度(granularity)、功耗、数据宽度，所以内存电路804可被视为一「虚拟的外部高速缓存内存」。例如，当4个记忆深度是512M和总线宽度是32位的嵌入式动态随机存取内存芯片堆栈在内存电路804时，内存电路804(虚拟的外部高速缓存内存)可根据并行转串行总线可编程中介单元8022内的模式缓存器的内容，被设定为具有记忆深度是1G和总线宽度是64位或是记忆深度是512M和总线宽度是128位的虚拟的外部高速缓存内存。
请参照图9，图9是本发明的一第十实施例公开一种具有嵌入式内存的系统级封装内存模块900的示意图。如图9所示，并行转串行总线可编程中介单元9022包含一模式缓存器9102，一配置电路9104，一时钟发生器9106和一并行/串行控制器9108。模式缓存器9102可被非内存电路902(中央处理器)设定，以及配置电路9104可根据模式缓存器9102内的内容，控制与重构介于内存电路904与配置电路9104之间的可重构总线9024。例如，当内存电路904是4个记忆深度是512M和总线宽度是32位的嵌入式动态随机存取内存芯片堆栈在一起时，介于内存电路904与配置电路9104之间的可重构总线9024的总线宽度(bus width)可被设定为32位、64位或128位，以及其记忆深度(address width)可分别对应地设定为2G、1G或512M。
如图9所示，配置电路9104包含一输入/输出宽度控制器91042、一输出单元91044和一输入单元91046。输入/输出宽度控制器91042可存取模式缓存器9102内的内容以及配置介于内存电路904与配置电路9104之间的可重构总线9024。因此，本发明可实现介于内存电路904(虚拟的外部高速缓存内存)与非内存电路902之间的不同总线宽度的配置。例如，在本发明的一实施例中，可重构总线9024的总线宽度被设定为M位以及在可重构总线9024上的电压摆幅(介于逻辑电平“1”信号和逻辑电平“0”信号之间的电压差)被设定为1.8V，配置电路9104内的输出单元91044接收内存电路904(虚拟的外部高速缓存内存)的M位数据以及根据时钟发生器9106所产生的第一时钟信号，同时输出M位数据至并行/串行控制器9108。为了节能目的，输出单元91044可将M位数据的电压摆幅从1.8V降低至1.2V(或更低)以及产生具有电压摆幅1.2V的M位数据并通过介于并行/串行控制器9108与配置电路9104之间的一可重构总线9026传送至并行/串行控制器9108。并行/串行控制器9108接收具有电压摆幅1.2V的并行M位数据，根据产生自时钟发生器9106的第二时钟信号，转换具有电压摆幅1.2V的并行M位数据为符合高速串行总线通信协议(例如通用串行总线(UniversalSerial Bus,USB)3.0的通信协议或快速外围组件互连接口(Peripheral ComponentInterconnect Express,PCIe)的通信协议)的一组串行数据，以及通过高速串行总线9028传送所述组串行数据至非内存电路902(中央处理器)。
另一方面，非内存电路902(中央处理器)可传输一组高速串行数据(例如通用串行总线3.0的数据或快速外围组件互连接口的数据)至并行转串行总线可编程中介单元9022的并行/串行控制器9108，然后并行/串行控制器9108转换所述组高速串行数据为具有电压摆幅1.2V的并行M位数据。并行/串行控制器9108通过可重构总线9026传送具有电压摆幅1.2V的并行M位数据至输入单元91046，以及输入单元91046可增加并行M位数据的电压摆幅从1.2V至1.8V和通过介于并行转串行总线可编程中介单元9022和内存电路904(虚拟的外部高速缓存内存)之间的可重构总线9024传送具有电压摆幅1.8V的M位数据至内存电路904(虚拟的外部高速缓存内存)。
请参照图10，图10是本发明的一第十一实施例公开一种具有嵌入式内存的系统级封装内存模块1000的示意图。如图10所示，树脂(或其他封装材料)1002可嵌入内存电路1004和基板1006之间的空间。另外，树脂1008可设置在非内存电路1010的边缘以密封非内存电路1010的边缘。
请参照图11，图11是本发明的一第十二实施例公开一种具有嵌入式内存的系统级封装内存模块1100的示意图。如图11所示，树脂(或其他封装材料)1102可封住非内存电路1104和内存电路1106。
请参照图12，图12是本发明的一第十三实施例公开一种具有嵌入式内存的系统级封装内存模块1200的示意图。如图12所示，一第一散热器1202耦接在非内存电路1204以加速非内存电路1204的散热，以及一第二散热材料1206耦接在内存电路1208以加速内存电路1208的散热，其中第二散热材料1206是一导热膏。
请参照图13A，图13A是本发明的一第十四实施例公开一种具有嵌入式内存的系统级封装内存模块1300的示意图。如图13A所示，额外的内存1302覆盖具有嵌入式内存(embedded memory)的系统级封装(system-in-package)内存模块1400，其中图13A的结构称为层迭封装(Package On Package,POP)。如图13A所示，额外的内存1302是一常规动态随机存取内存或是堆栈的动态随机存取内存。在图13A中，内存电路1304是上述系统级封装内存模块1400内非内存电路1306的外部高速缓存内存，以及额外的内存1302可作为上述系统级封装内存模块1400内非内存电路1306的主存储器电路。另外，如图13A所示，额外的内存1302和系统级封装内存模块1400之间存在电接点1308。另外，如图13B所示，电接点1308贯穿系统级封装内存模块1400。
综上所述，本发明所公开的具有嵌入式内存的系统级封装内存模块是整合内存电路(嵌入式动态随机存取内存)、非内存电路(逻辑电路)和基板于系统级封装内，所以本发明可缩小系统级封装内存模块的面积。另外，因为本发明的系统级封装内存模块可被客制化以因应不同的内存电路(嵌入式动态随机存取内存)和非内存电路(逻辑电路)，所以本发明的系统级封装内存模块具有优化的效能、效率以及成本的一组合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

1.一种具有嵌入式内存的系统级封装内存模块，其特征在于，包含：
一非内存电路；
一内存控制器；
一内存电路；及
一基板，其中所述非内存电路、所述内存控制器和所述内存电路是堆栈后共同封装于所述基板之上，所述内存电路与所述内存控制器是形成在同一片半导体芯片上，且所述内存电路和所述基板之间没有直接的金属连接，其中所述基板另用以电连接设置在所述系统级封装内存模块外的外部电路板。
2.如权利要求1所述的系统级封装内存模块，其特征在于，所述非内存电路的主动组件区是通过一引线键合与所述基板电连接，以及所述内存电路是通过面对面的凸点结构电连接所述非内存电路。
3.如权利要求1所述的系统级封装内存模块，其特征在于，所述非内存电路的主动组件区是通过一面对面的凸点结构电连接所述基板，以及所述内存电路是通过一穿硅通孔和另一面对面的凸点结构电连接所述非内存电路。
4.一种具有嵌入式内存的系统级封装内存模块，其特征在于，包含：
一非内存电路，具有一第一部分和一第二部分；
一基板，具有一窗口以及所述基板电连接所述非内存电路的第二部分；及
一内存电路，设置于所述基板的窗口且电连接所述非内存电路的第一部分；
其中所述内存电路和所述基板之间没有直接的金属连接，在所述内存电路和所述基板之间存在间隙，所述基板另用以电连接设置在所述系统级封装内存模块外的外部电路板，以及所述间隙被树脂填充。
5.如权利要求4所述的系统级封装内存模块，其特征在于，所述内存电路是一动态随机存取内存或是多个组装或堆栈在一起的动态随机存取内存，所述非内存电路是一逻辑电路。
6.如权利要求4所述的系统级封装内存模块，其特征在于，另包含：
一内存控制器，用以根据所述系统级封装内存模块的指令，存取所述非内存电路或所述内存电路的数据，用以矫正储存在所述非内存电路或所述内存电路内的数据错误，以及用以动态改变所述系统级封装内存模块的操作电压、操作频率及总线宽度的一组合。
7.如权利要求4所述的系统级封装内存模块，其特征在于，所述非内存电路包含多个核心与一第一高速缓存内存，以及包含一额外可被该所述多个核心中的每一核心分享的内部高速缓存内存。
8.如权利要求4所述的系统级封装内存模块，其特征在于，另包含：
一并行转串行总线可编程中介单元；
一第一可重构总线，耦接于所述并行转串行总线可编程中介单元与所述内存电路之间，其中所述第一可重构总线是一并行总线；及
一第二可重构总线，耦接于所述并行转串行总线可编程中介单元与所述非内存电路之间，其中所述第二可重构总线是一串行总线；
其中所述第一可重构总线和所述第二可重构总线的总线宽度或记忆深度可被动态地改变。
9.如权利要求4所述的系统级封装内存模块，其特征在于，所述树脂另设置在所述非内存电路的边缘以密封所述非内存电路的边缘。
10.如权利要求4所述的系统级封装内存模块，其特征在于，另包含：
一树脂，用以封装住所述非内存电路和所述内存电路。
11.如权利要求4所述的系统级封装内存模块，其特征在于，另包含：
一第一散热器，耦接在所述非内存电路以加速所述非内存电路的散热；及
一第二散热材料，耦接在所述内存电路以加速所述内存电路的散热。
12.如权利要求11所述的系统级封装内存模块，其特征在于，所述第二散热材料是一导热膏。
13.如权利要求4所述的系统级封装内存模块，其特征在于，另包含：
一额外的内存，用以覆盖所述非内存电路、所述内存电路和所述基板，所述额外的内存和包覆所述非内存电路和所述内存电路的封装之间具有多个电接点，且所述额外的内存是一动态随机存取内存或是堆栈的动态随机存取内存。
14.如权利要求13所述的系统级封装内存模块，其特征在于，多个所述电接点贯穿包覆所述非内存电路和所述内存电路的封装。
15.一种具有嵌入式内存的系统级封装内存模块，其特征在于，包含：
一非内存电路，具有一第一部分和一第二部分；
仅一基板，具有一窗口以及所述基板电连接所述非内存电路的第二部分；
一内存电路，设置于所述基板的窗口且电连接所述非内存电路的第一部分；
一并行转串行总线可编程中介单元；
一第一可重构总线，耦接于所述并行转串行总线可编程中介单元与所述内存电路之间，其中所述第一可重构总线是一并行总线；及
一第二可重构总线，耦接于所述并行转串行总线可编程中介单元与所述非内存电路之间，其中所述第二可重构总线是一串行总线，且所述第一可重构总线和所述第二可重构总线的总线宽度或记忆深度可被动态地改变；
其中所述内存电路和所述基板之间没有直接的金属连接，在所述内存电路和所述基板之间存在间隙，以及所述间隙被树脂填充。
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