CN108700788B - 用于液晶显示器的高电容电容器的界面工程 - Google Patents

用于液晶显示器的高电容电容器的界面工程 Download PDF

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CN108700788B
CN108700788B CN201780014750.6A CN201780014750A CN108700788B CN 108700788 B CN108700788 B CN 108700788B CN 201780014750 A CN201780014750 A CN 201780014750A CN 108700788 B CN108700788 B CN 108700788B
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electrode
substrate
layer
dielectric layer
interface protection
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CN108700788A (zh
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张雪娜
任东吉
戴文清
尤哈维
元泰景
杨潇林
林宛瑜
蔡云初
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Applied Materials Inc
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Applied Materials Inc
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    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Abstract

本公开内容的实施方式大体上提供形成具有高电容和低泄漏的电容器的方法以及用于薄膜晶体管(TFT)应用的良好的界面控制。在一个实施方式中，一种薄膜晶体管结构包括形成在薄膜晶体管器件中的电容器。电容器进一步包括设置在基板上的公共电极、形成在公共电极上的介电层和形成在介电层上的像素电极。界面保护层形成在公共电极与介电层之间，或介电层与像素电极之间。由高k材料制成的栅极绝缘层也可用于薄膜晶体管结构。

Description

用于液晶显示器的高电容电容器的界面工程
技术领域
本公开内容的实施方式总体涉及形成具有高电容和低泄漏的像素电容器结构。尤其是，本公开内容的实施方式涉及用于形成具有高电容和低泄漏的像素电容器结构，以供液晶显示器(LCD)应用。
背景技术
显示装置已广泛地用于广泛范围的电子应用，诸如TV、监视器、移动电话、MP3播放器、电子书阅读器和个人数字助理(PDA)等等。显示装置一般被设计成通过向液晶施加电场来产生期望图像，液晶填充两个基板(例如，像素电极和公共电极)之间的间隙并且具有控制介电场的强度的各向异性介电常数。通过调整传输通过基板的光的量，可有效地控制光和图像强度、质量和功耗。
各种不同的显示装置，诸如有源矩阵液晶显示器(AMLCD)或有源矩阵有机发光二极管(AMOLED)，可以用作利用触摸屏面板的显示装置的光源。在 TFT器件的制造中，具有高电子迁移率、低泄漏电流和高击穿电压的电子器件将会允许更多的像素区域用于光传输和电路集成，从而产生更亮的显示、更高的总电效率、更快的响应时间和更高的显示分辨率。在一些器件中，介电层放置在像素电极与公共电极之间以形成可在TFT器件操作时存储电力电荷的电容器。所形成的电容器需要具有高电容以及低泄漏以提供TFT器件的期望的电性能。可以通过改变在像素电极与公共电极之间形成的介电层的介电常数和/ 或介电层的厚度来调整电容。例如，当用具有较高的介电常数的材料代替介电层时，电容器的电容也将增大。然而，介电层的材料的选择不仅影响电容器的电容，介电层的材料与电极(与像素电极或与公共电极)的不相容性也可能会造成膜结构剥落、不良的界面粘附性或界面材料扩散，这最终会引起器件故障和低的产品产量。
因此，需要用于形成具有高电容和低泄漏的电容器的改进方法以及用于制造产生改进的器件电性能的TFT器件的良好的界面控制。
发明内容
本公开内容的实施方式大体上提供形成具有高电容和低泄漏的电容器的方法以及在薄膜晶体管(TFT)应用的良好的界面控制。在一个实施方式中，一种薄膜晶体管结构包括形成在薄膜晶体管器件中的电容器。电容器进一步包括设置在基板上的公共电极、形成在公共电极上的介电层和形成在介电层上的像素电极。界面保护层形成在公共电极与介电层之间，或介电层与像素电极之间。
在另一实施方式中，一种在基板上形成电容器结构供薄膜晶体管应用的方法包括：在用以形成薄膜晶体管器件的基板上形成公共电极；在公共电极上形成介电层；和在介电层上形成像素电极。在公共电极与介电层之间或介电层与像素电极之间形成界面保护层。
在又一实施方式中，一种在基板上形成绝缘层以供薄膜晶体管应用的方法包括通过原子层沉积工艺或包括原子层沉积工艺和化学气相沉积工艺的混合工艺在基板上形成高k层，其中高k层是薄膜晶体管器件中的栅极绝缘层、钝化层、电容器、层间绝缘体、蚀刻停止层。
附图说明
以上简要概述的本公开内容的上述详述特征被达到和可以详细理解的方式，以及本公开内容的更特定描述可以通过参照实施方式来获得，其中实施方式绘示在附图中。
图1描绘根据本公开内容的一个实施方式的可用于沉积介电层的处理腔室的截面图；
图2描绘根据本公开内容的一个实施方式的可用于沉积金属层的处理腔室的截面图；
图3描绘形成TFT器件结构的一部分的方法的一个实施方式的工艺流程图；
图4是薄膜晶体管器件结构的一个示例的截面图；
图5A-5C描绘可用于图4的薄膜晶体管的膜结构的不同示例；
图6A-6C 描绘可用于图4的薄膜晶体管的膜结构的不同示例；和
图7描绘根据本公开内容的一个实施方式的可用于沉积高k材料的处理腔室的截面图。
为了促进理解，已经尽可能地使用相同的附图标号标示各图中共通的相同元件。考虑到，一个实施方式的元件和特征在没有进一步描述下可有益地并入在其他实施方式中。
然而，应当注意，随附图式仅绘示本公开内容的示例性实施方式，因而不应视为对本公开内容的范围的限制，因为本公开内容可允许其他等同有效的实施方式。
具体实施方式
本公开内容的实施方式一般地提供形成具有增强的电性能(诸如高电容和低泄漏)的电容器或用于显示装置的具有高介电常数的绝缘层的方法。在一个示例中，形成在显示装置中的电容器可以包括形成在像素电极与公共电极之间的介电层。介电层可以是具有大于8的介电常数的高k介电材料。在另一布置中，界面保护层可以形成在像素电极与介电层之间和/或公共电极与介电层之间。这种电容器结构可有效地增强晶体管和二极管器件的电性能，以及良好界面粘附控制。在另一示例中，具有高介电常数的任何绝缘层，诸如栅极绝缘层、蚀刻停止层或界面保护层，也可利用高介电常数材料来增强和改进电性能。
图1是等离子体增强化学气相沉积(PECVD)腔室(处理腔室)100的一个实施方式的示意横截面图，其中可以沉积介电层，诸如TFT器件结构中的绝缘层、栅极绝缘层、蚀刻停止层、钝化层、层间绝缘体、用于电容器的介电层或钝化层。一个合适的等离子体增强化学气相沉积腔室可购自位于加利福尼亚州圣克拉拉的应用材料公司(Applied Materials,Inc.,located in Santa Clara,CA)。可以预期，利用其他沉积腔室(包括来自其他制造商的那些)来实践本公开内容。
腔室100一般包括界定工艺容积106的壁142、底部104和盖112。气体分配板110和基板支撑组件130设置在工艺容积106中。工艺容积106通过穿过壁142形成的阀108进出，使得基板102可被传送进出腔室100。
基板支撑组件130包括用于在其上支撑基板102的基板接收表面132。杆134将基板支撑组件130耦接到升降系统136，升降系统使基板支撑组件130 在基板传送和处理位置之间升高和降低。阴影框架133在处理时可以任选地放置在基板102的周边上以防止在基板102的边缘上发生沉积。升降杆138可移动地设置穿过基板支撑组件130并且适于将基板102与基板接收表面132间隔开。基板支撑组件130还可包括加热和/或冷却元件139，用于将基板支撑组件 130维持在期望温度。基板支撑组件130还可包括接地条带131以提供围绕基板支撑组件130的周边的RF返回路径。
气体分配板110在其周边由悬架114而耦接到腔室100的盖112或壁142。气体分配板110还可由一个或多个中心支撑件116耦接到盖112以有助于防止下垂和/或控制气体分配板110的直度/曲率。气体分配板110可以具有不同大小的不同构造。在示例性实施方式中，气体分配板110具有四边形的平面形状。气体分配板110具有下游表面150，下游表面具有形成在其中的多个孔111，多个孔面向设置在基板支撑组件130上的基板102的上表面118。孔111可以具有不同形状、数量、密度、尺寸和在气体分配板110各处的不同分布。在一个实施方式中，孔111的直径可以被选择为在约0.01英寸与约1英寸之间。
气源120耦接到盖112，以提供气体通过盖112，并且然后通过形成在气体分配板110中的孔111，到达工艺容积106。真空泵109耦接到腔室100以将工艺容积106中的气体维持在期望压力下。
RF功率源122耦接到盖112和/或气体分配板110以提供RF功率，RF功率在气体分配板110与基板支撑组件130之间形成电场，使得等离子体可由气体分配板110和基板支撑组件130之间存在的气体产生。RF功率可以在各种 RF频率下施加。例如，RF功率可以在约0.3MHz与约200MHz之间的频率下施加。在一个实施方式中，RF功率在13.56MHz的频率下提供。
在一个实施方式中，气体分配板110的下游表面150的边缘可以是弯曲的，使得在气体分配板110与基板接收表面132的边缘和拐角之间并且因此在气体分配板110与基板102的上表面118之间限定间隔梯度。下游表面150的形状可以被选择为满足特定的工艺要求。例如，下游表面150的形状可以是凸形、平坦、凹形或其他合适的形状。因此，边缘到拐角的间隔梯度可以用来调节在基板边缘各处的膜性质均匀性，由此校正设置在基板的拐角中的膜的性质的不均匀性。另外，还可控制边缘到中心的间隔，使得可以在基板的边缘和中心之间控制膜性质分布均匀性。在一个实施方式中，可以使用气体分配板110的凹形的弯曲边缘，使得相较于气体分配板110的拐角来说，气体分配板110的边缘的中心部分与基板102的上表面118间隔更远。在另一实施方式中，可以使用气体分配板110的凸形的弯曲边缘，使得相较于气体分配板110的边缘来说，气体分配板110的拐角与基板102的上表面118间隔更远。
远程等离子体源124，诸如电感耦合的远程等离子体源，也可耦合耦接在气源与气体分配板110之间。在正在处理的基板之间，清洁气体可以在远程等离子体源124中被激励以远程地提供用于清洁腔室部件的等离子体。进入工艺容积106的清洁气体可以通过由电源122提供到气体分配板110的RF功率被进一步激发。合适的清洁气体包括但不限于NF3、F2和SF6。
在一个实施方式中，可在腔室100中处理的基板102可以具有10,000cm2或更大、例如25,000cm2或更大、例如约55,000cm2或更大的表面面积。应理解，在处理之后，可以切割基板以形成更小的其他器件。
在一个实施方式中，加热和/或冷却元件139可设定成提供约600摄氏度或更低(例如，在约100摄氏度与约500摄氏度之间，或在约200摄氏度与约 500摄氏度之间，诸如约300摄氏度和500摄氏度)的在沉积期间的基板支撑组件温度。
在沉积期间在设置在基板接收表面132上的基板102的上表面118与气体分配板110之间的标称间隔一般可以在400密耳(mil)与约1200密耳之间、诸如在400密耳与约800密耳之间变化，或是获得期望的沉积结果所需的其他距离。在其中气体分配板110具有凹形的下游表面的一个示例性实施方式中，气体分配板110的边缘的中心部分与基板接收表面132之间的间隔在约400密耳与约1400密耳之间，并且在气体分配板110的拐角与基板接收表面132之间的间隔在约300密耳与约1200密耳之间。
图2图示根据本发明的一个实施方式的适于形成界面保护层和/或金属电极(诸如像素电极或公共电极)的示例性反应溅射处理腔室200。处理腔室200 可以是具有多个处理腔室200的真空处理系统的一部分。可经调适以获益于本发明的工艺腔室的一个示例是可从位于加利福尼亚州圣克拉拉的应用材料公司获得的物理气相沉积(PVD)工艺腔室。可以预期，包括来自其他制造商的那些腔室在内的其他溅射工艺腔室也可适于实践本发明。
处理腔室200包括腔室主体208，腔室主体具有限定在其中的处理容积218 并且由盖组件204封闭。腔室主体208具有侧壁210和底部246。工艺腔室200 的腔室主体208和相关部件的尺寸不受限制并且一般成比例地大于要在其中处理的基板(诸如图1的基板102)的大小。由此，任何合适的基板尺寸都可在合适大小的工艺腔室中处理。合适的基板大小的示例包括具有约2000平方厘米或更大的平面表面积的基板。
腔室主体208可以由铝或其他合适的材料制成。基板进出端口230穿过腔室主体208的侧壁210形成，以促进基板102(即，太阳能电池板或平板显示器基板、塑料或柔性基板、半导体晶片或其他工件)进出工艺腔室200。进出端口 230可耦接到传送腔室和/或基板处理系统的其他腔室。
气源228耦接到腔室主体208以将工艺气体供应到处理容积218中。可由气源228提供的工艺气体的示例包括惰性气体、非反应性气体和反应性气体。在一个实施方式中，由气源228提供的工艺气体可包括但不限于氩(Ar)、氦 (He)、氮(N2)、氧(O2)和H2O等等。
泵吸端口250穿过腔室主体208的底部246形成。泵吸装置252耦接到工艺容积218以抽空并控制其中的压力。在一个实施方式中，工艺腔室200的压力水平可以维持在约1Torr或更低的压力下。
盖组件204一般包括靶220和耦接到靶或定位在其附近的接地屏蔽组件 226。靶220提供可在PVD工艺期间溅射并沉积到基板102的表面上的材料源。靶220或靶板可以由用作沉积物质的材料制成。高电压电源，诸如电源232，连接到靶220以促进来自靶220的溅射材料。在一个实施方式中，靶220可以由含金属的材料制成，例如钛(Ti)、钽(Ta)、镁(Mg)、银(Si)、铟(In)、锡(Sn)、氧化铟锡(ITO)、氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)、铝(Al)、钨(W)、金(Au)、钼(Mo)、汞(Hg)、铬(Cr)、金属、金属合金或其他合适的材料。在另一实施方式中，靶220可以由包括铟锡合金和类似物的材料制成。
靶220一般包括外围部分224和中心部分216。外围部分224设置在腔室 200的侧壁210上方。靶220的中心部分216可以具有略微朝向设置在基板支撑件238上的基板102的表面延伸的曲率表面。靶220和基板支撑件238之间的间隔维持在约50mm与约150mm之间。应注意，靶220的尺寸、形状、材料、配置和直径可针对特定工艺或基板要求而变化。在一个实施方式中，靶220可进一步包括背板，背板具有由期望溅射到基板表面上的材料粘合和/或制造的中心部分。靶220还可包括一起形成靶的多个材料片或材料段。
盖组件204可进一步包括安装在靶220上方的磁控管组件202，磁控管组件在处理期间增强材料从靶220的有效溅射。磁控管组件的示例包括线性磁控管、蛇形磁控管、螺旋磁控管、双指状磁控管、矩形磁化螺旋磁控管 (rectangularized spiral magnetron)等等。
盖组件204的接地屏蔽组件226包括接地框架206和接地屏蔽件212。接地屏蔽组件226还可包括其他腔室屏蔽构件、靶屏蔽构件、暗区屏蔽件和暗区屏蔽框架。接地屏蔽件212由接地框架206耦接到外围部分224，从而在工艺容积218中在靶220的中心部分216下方限定上部处理区域254。接地框架206 使接地屏蔽件212与靶220电绝缘，同时提供穿过侧壁210到工艺腔室200 的腔室主体208的接地路径。接地屏蔽件212约束在上部处理区域254内进行处理期间产生的等离子体，使得从靶的中心部分216撞出的靶源材料220主要沉积在基板表面而不是腔室侧壁210。在一个实施方式中，接地屏蔽件212可以由一个或多个部件形成。
延伸穿过腔室主体208的底部246的轴240将基板支撑件238耦接到升降机构244。升降机构244经配置以使基板支撑件238在下部传送位置与上部处理位置之间移动。波纹管242围绕轴240并耦接到基板支撑件238以在它们之间提供柔性密封，从而维持腔室处理容积218的真空完整性。
阴影框架222设置在基板支撑件238的外围区域上，并且经配置以将从靶 220溅射的源材料的沉积限制在基板表面的期望部分上。当基板支撑件238处于降低位置时，阴影框架222从腔室屏蔽件236的从腔室主体208的侧壁210 延伸的唇缘256悬挂在基板支撑件238上方。当基板支撑件238升高到上部位置以进行处理，设置在基板支撑件238上的基板102的外缘接触阴影框架222，使得阴影框架222被提升并与腔室屏蔽件236间隔开。在移动到下降位置的过程中或在此同时，升降杆(未示出)选择性地移动通过基板支撑件238以将基板102提升到基板支撑件238上方，以促进由传送机器人或其他合适的传送机构接取基板102。
控制器248耦接到处理腔室200和任选地处理腔室100。控制器248包括中央处理单元(CPU)260、存储器258和支持电路262。控制器248用于控制工艺序列，从而调节从气源228进入腔室200的气流并控制靶220的离子轰击。 CPU 260可以是可用于工业环境的任何形式的通用计算机处理器。软件例程可以存储在存储器258中，诸如：随机存取存储器、只读存储器、软盘或硬盘，或者其他形式的数字存储装置。支持电路262常规地耦接到CPU 260，并且可以包括高速缓存、时钟电路、输入/输出子系统、电源等等。软件例程在由CPU 260执行时，将CPU转变为专用计算机(控制器)248，从而控制处理腔室200，使得这些工艺是根据本发明执行。软件例程还可通过位于腔室200的远程位置的第二控制器(未示出)存储和/或执行。
在处理期间，靶220和基板支撑件238通过电源232相对于彼此偏置以维持从由气源228供应的工艺气体形成的等离子体。来自等离子体的离子加速朝向靶220并撞击到其上，使得靶材料被从靶220撞出。撞出的靶材料在基板 102上形成一层。在其中某些工艺气体供应到腔室200中的实施方式中，撞出的靶材料和存在于腔室200中的工艺气体反应以在基板102上形成复合膜。
首先参考图7，图7是可用于执行本文所述的沉积的ALD(原子层沉积)腔室700的示意性截面图。ALD沉积工艺可以用于形成介电层，诸如TFT器件结构中的绝缘层、栅极绝缘层、蚀刻停止层、层间绝缘体、用于电容器的介电层或钝化层，如本文所述。腔室700一般包括腔室主体702、盖组件704、基板支撑组件706和工艺配件750。盖组件704设置在腔室主体702上，并且基板支撑组件706至少部分地设置在腔室主体702内。腔室主体702包括狭缝阀口708，所述狭缝阀口形成在腔室主体的侧壁中，以提供通向处理腔室700的内部的通路。在一些实施方式中，腔室主体702包括与真空系统(例如，真空泵)流体连通的一个或多个孔。孔为腔室700内的气体提供出口。真空系统由工艺控制器控制以维持ALD腔室700内适于ALD工艺的压力。盖组件704 可以包括一个或多个差动泵和净化组件720。差动泵和净化组件720用波纹管 722安装到盖组件704。波纹管722允许泵和净化组件720相对于盖组件704 竖直地移动，同时仍维持密封以防止气体泄漏。当工艺配件750升高到处理位置中时，工艺配件750上的柔顺的第一密封件786和柔顺的第二密封件788 与差动泵和净化组件720接触。差动泵和净化组件720与真空系统(未示出)连接并维持在低压下。
如图7所示，盖组件704包括RF阴极710，RF阴极可以在腔室700内和/或在工艺配件750内产生反应物质的等离子体。RF阴极710可以例如通过电加热元件(未示出)加热和例如通过冷却流体的循环来冷却。可以使用能够将气体激活成活性物质并维持活性物质中的等离子体的任何电源。例如，可以使用基于RF或微波(MW)的功率放电技术。激活还可通过基于热的技术、气体分解技术、高强度光源(例如，UV能量)或暴露于x射线源产生。
基板支撑组件706可以至少部分地设置在腔室主体702内。基板支撑组件 706可以包括基板支撑构件或基座730以支撑基板732来在腔室主体内进行处理。基座730可以通过延伸穿过形成在腔室主体702的底表面中的一个或多个开口726的轴724或轴724耦接到基板升降机构(未示出)。基板升降机构可以通过波纹管728柔性地密封到腔室主体702以防止轴724四周发生真空泄漏。基板升降机构允许基座730在ALD腔室700内在下部机器人进入位置(如图所示)与处理位置、工艺配件传送位置和基板传送位置之间竖直地移动。在一些实施方式中，基板升降机构在比所述的位置更少的位置之间移动。
在一些实施方式中，可以使用真空吸盘(未示出)、静电吸盘(未示出)或机械夹具(未示出)将基板732固定到基座。基座730的温度可以在ALD腔室700 中的处理期间(通过例如工艺控制器)经控制以影响基板732和工艺配件750的温度，从而改进ALD处理的表现。基座730可以通过例如基座730内的电加热元件(未示出)加热。基座730的温度可以由例如腔室700中的高温计(未示出) 确定。
如图7所示，基座730可以包括穿过基座730的一个或多个孔隙(bore) 734以容纳一个或多个升降杆736。每个升降杆736被安装成使得它们可以在孔隙734内自由地滑动。支撑组件706可移动以使得当支撑组件706处于下部位置时，升降杆736的上表面可以位于基座730的基板支撑表面738上方。相反，当支撑组件706处于升高位置时，升降杆736的上表面位于基座730的上表面738下方。当接触腔室主体702时，升降杆736推靠在基板732的下表面上，从而提升基板离开基座730。相反，基座730可以将基板732从升降杆736 升起。
在一些实施方式中，基座730包括工艺配件绝缘按钮737，工艺配件绝缘按钮可以包括一个或多个柔顺的密封件739。工艺配件绝缘按钮737可以用于在基座730上承载工艺配件750。当基座将工艺配件850提升到处理位置中时，工艺配件绝缘按钮737中的一个或多个柔顺的密封件839就被压缩。
图3描绘用于形成适用于薄膜晶体管器件的电容器或绝缘层的工艺300 的一个实施方式的流程图。用于薄膜晶体管器件的绝缘层的合适的示例包括栅极绝缘层、界面层、用于形成电容器的介电层、蚀刻停止层，或钝化层(在需要绝缘材料的情况下)。在一个示例中，电容器可以包括介电层或形成在像素电极与公共电极之间的绝缘层。介电层或绝缘层可以通过可在如图1所述的工艺腔室100中实践的等离子体增强化学气相沉积(PECVD)工艺形成，或通过可在如图7所述的处理腔室700中实践的原子层沉积(ALD)工艺形成，或在其他合适的工艺腔室中形成。像素电极和公共电极可以通过可在如图2所述的处理腔室200中实践的物理气相沉积(PVD)工艺形成。
工艺300在操作302处以如下步骤开始：在工艺腔室(诸如图2中所示的工艺腔室200(PVD腔室))中提供基板102。基板102可以包括TFT器件，TFT 器件部分地形成在基板上以容易地在基板102上形成公共电极。在图4中描绘的示例中，基板102可以包括平坦化层418的平坦表面419，平坦表面已准备好让公共电极420形成在其上。公共电极420连同介电层424(或称为绝缘层) 和像素电极426(如圆圈460所示)可以一起形成TFT器件结构450中的电容器 427，将稍后就图5A-5C中的电容器427的结构在工艺300的不同的制造阶段的变化而详细地描述电容器。应注意，用于形成介电层424(或绝缘层)的材料也可用于形成在TFT器件结构450中需要绝缘材料的其他层。
在图4中描绘的示例中，形成在基板102上的TFT器件450包括低温多晶硅(LTPS)TFT器件。基板102可以具有先前形成在其上的膜、结构或层的不同组合，以促进在基板102上形成不同的器件结构或不同的膜堆叠。基板102 可以是玻璃基板、塑料基板、聚合物基板、金属基板、单切基板、卷对卷基板或适于在其上形成薄膜晶体管的其他合适的透明基板中的任一种。
LTPS TFT器件450是MOS器件，其构建有形成在具有或没有任选的绝缘层404设置在其上的光学上透明的基板402上的源极区409a、沟道区408 和漏极区409b。源极区409a、沟道区408和漏极区409b一般由初始沉积的非晶硅(a-Si)层形成，a-Si层典型地使稍后进行热处理或激光处理以形成多晶硅层。源极区409a、沟道区408和漏极区409b可以通过使光学上透明的基板402 上的区域图案化并对所沉积的初始a-Si层进行离子掺杂来形成，然后对其进行热处理或激光处理(例如，准分子激光器退火工艺)以形成多晶硅层。然后在所沉积的多晶硅层的顶部上沉积栅极绝缘层406，以将栅极电极414与沟道区 408、源极区409a和漏极区409b隔离。栅极电极414形成在栅极绝缘层406 的顶部上。栅极绝缘层406通常也被称为栅极氧化层。然后，穿过绝缘层制作层间绝缘体412和器件连接件以允许控制TFT器件。
在形成层间绝缘体412之后，然后在电连接到源极区409a和漏极区409b 的层间绝缘体412中沉积、形成源极-漏极金属电极层410a、410b并将其图案化。在使源极-漏极金属电极层410a、410b图案化之后，然后在源极-漏极金属电极层410a、410b上方形成平坦化层418以提供平坦表面419，稍后可以在平坦表面上形成公共电极420并使其图案化。平坦化层418可以由聚酰亚胺、苯并环丁烯系列树脂、旋涂玻璃(SOG)或丙烯酸酯制成。稍后使平坦化层418 图案化以形成通孔接触孔421，通孔接触孔允许公共电极420(例如，工艺300 的提供金属材料的开始步骤)连同介电层424和/或像素电极426一起按顺序地填充在其中。应注意，图4中所示的结构仅是TFT器件450的示例性实施方式。通孔接触孔421可以在需要时以任何配置由公共电极420、介电层424或像素电极426部分地或完全地填充。像素电极426和公共电极420连同在它们之间形成的介电层424一起组合地形成TFT器件450中的电容器427(例如， MIM(金属-绝缘-金属)结构)，如图4中描绘的示例所示。在形成像素电极426 之后，可以在电容器427的结构上形成其他绝缘层428，诸如有机层或液晶层，以进一步完成器件450的结构。
应注意，图3的工艺300描述了在基板102上形成包括公共电极420、介电层424和像素电极426的电容器427的工艺序列。
在操作304，执行物理气相沉积工艺以在基板102上形成公共电极420(例如，第一金属层)，如图5A所示。应注意，图5A-5C中所示的公共电极420、介电层424和像素电极426等效于图4中所示的公共电极420、介电层424和像素电极426。
在一个示例中，形成在基板102上的公共电极420由合适的金属材料制成，诸如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)、铝(Al)、钨(W)、铬 (Cr)、钽(Ta)、钛(Ti)、钼(Mo)、镁(Mg)、银(Ag)、金(Au)、铬(Cr)或以上的合金或以上的组合。在一个特定示例中，公共电极420是氧化铟锡锌(ITO)层。
应注意，如在操作306处所述，在于公共电极上形成介电层424之前，可以在需要时以任何形式或以任何方式使公共电极420图案化。
在操作306处，在基板102上形成公共电极420并任选地在需要时使其图案化之后，然后在基板102上形成介电层424，如图5A所示。通过将基板102 传送到沉积腔室(例如图1中描绘的等离子体增强化学气相沉积腔室100)以在基板102上执行化学气相沉积工艺，可以在基板102上形成介电层424。
在一个示例中，介电层424可以是由高k材料(例如，具有大于8的介电常数的介电材料)制成的单个层。高k材料层的合适的示例包括二氧化铪 (HfO2)、氮氧化铪(HfON)、二氧化锆(ZrO2)、氮氧化锆(ZrON)、氧化铝(Al2O3)、氮氧化铝(AlON)、氧化铪硅(HfSiO2)、氧化铪铝(HfAlO)、硅氧化锆(ZrSiO2)、二氧化钽(Ta2O5)、氧化铝、Y2O3、La2O3、氧化钛(TiO2)、铝掺杂的二氧化铪、铋锶钛(BST)和铂锆钛(PZT)等等。应注意，介电层424可以通过CVD工艺、ALD工艺或任何合适的沉积工艺制造。在其中介电层424经配置为高k材料的示例中，介电层424的高k材料可以在ALD腔室(诸如图7中所示的处理腔室700)中通过ALD工艺制造。
利用形成为介电层424的高k材料，可以在电容器427的结构中形成高介电常数，并且因此，在电容器的电容随着形成在电容器中的介电层的介电常数的增大而增大时，就可以获得高电容。由介电层424提供的高电容可以改进 TFT器件450的电性能，同时减少不期望的电流泄漏和隧穿效应。因此，在利用高k材料作为电容器427中的介电层424的情况下，相较使用常规的氮化硅层或氧化硅层作为电容器中的介电层来说，具有高k材料介电层424的电容器 427的电容可以被增强和改进。
在一些示例中，形成在基板102上的介电层424可以是具有多个层的复合结构的形式，如图5B所示。在一个实施方式中，介电层424可以包括夹在顶部界面保护层506与底部界面保护层502之间的块体介电材料504。顶部界面保护层506可以与稍后在其上形成的像素电极426接触，而底部界面保护层 502可形成为与公共电极420接触。在此特定示例中，块体介电材料504可以由氮化硅材料(SiN)或高k材料制造，而顶部界面保护层506和底部界面保护层502可以是含硅介电材料，诸如氧化硅(SiO2)、氮氧化硅(SiON)、碳氧化硅 (SiOC)、碳化硅(SiC)和类似物。在一个示例中，当块体介电材料504是氮化硅材料(SiN)时，顶部界面保护层506和底部界面保护层502可以是氮氧化硅 (SiON)材料。在另一示例中，当块体介电材料504是高k材料时，顶部界面保护层506和底部界面保护层502可以是氧化硅材料(SiO2)或氮氧化硅(SiON)，就像如图5A中描绘的介电层424。
在一个示例中，顶部界面保护层506和底部界面保护层502可以通过CVD 沉积工艺形成。在另一示例中，当块体介电材料504是氮化硅材料(SiN)时，顶部界面保护层506可以通过含氧气体(诸如O2、O3或H2O)在块体介电材料 504上进行氧化、氧离子注入或氧表面处理来形成，从而将来自块体介电材料 504的氮化硅的表面氧化成氮氧化硅层。
据信，在像素电极426与公共电极420之间形成的顶部界面保护层506 和底部界面保护层502，可有助于将块体介电材料504桥接到顶部界面保护层 506和/或底部界面保护层502，以便增强电容器427的结构的粘附性而不产生膜剥离的问题。此外，顶部界面保护层506和底部界面保护层502还可用作热稳定界面结构，以便减少从金属像素电极426和金属公共电极420的泄漏。
顶部界面保护层506和/或底部界面保护层502可以形成在形成块体介电材料504(氮化硅材料或高k材料)的相同工艺腔室中。或者，顶部界面保护层 506和/或底部界面保护层502可以在需要时形成在任何合适的腔室中。
在操作308处，在基板102上形成介电层424之后，然后在介电层424 上形成像素电极426(例如，第二金属层)。类似于用于如操作304处所形成公共电极420的工艺，像素电极426由任何合适的金属材料制成，诸如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)、铝(Al)、钨(W)、铬(Cr)、钽(Ta)、钛(Ti)、钼(Mo)、镁(Mg)、银(Ag)、金(Au)、铬(Cr)或以上的合金，或者它们的组合。像素电极426还可通过在等离子体沉积腔室(诸如图2中描绘的工艺腔室200)中执行的物理气相沉积工艺(PVD)形成。
在一个实施方式中，像素电极426可以是由本段中上面讨论的金属材料形成的单个层的形式，如图5A-5B所示。或者，像素电极426可以是具有多种材料的复合结构的形式，例如第一金属电极508，第一金属电极上形成有第二金属电极510，如图5C所示。
在一个示例中，第一电极508和第二电极510可以是由选自以下的金属材料：氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)、铝(Al)、钨(W)、铬(Cr)、钽(Ta)、钛(Ti)、钼(Mo)、镁(Mg)、银(Ag)、金(Au)、铬(Cr)、银纳米油墨、碳纳米管(CNT)、银纳米油墨、石墨烯或以上的合金。在一个特定示例中，第一电极508是ITO层，并且第二电极510可以是选自Ta、Ti、Al、Mg、 Mo、W、Ag、Mg或以上的合金的金属层。在另一示例中，相比之下，第一电极508可以是Ta、Ti、Al、Mg、Mo、W、Ag、Mg或以上的合金的金属层，并且第二电极510可以是ITO层。
在特定示例中，第二电极510可以被图案化为形成在第一电极508上的网格或栅格电极的形式。在另一示例中，像素电极426和/或公共电极420在需要时也可以是网格或栅格电极的形式。
类似地，高k材料(例如，具有大于8的介电常数的介电材料)也可用于在 TFT器件450的其他位置或地方形成绝缘材料。例如，高-k材料也可用于形成任选的绝缘层404、栅极绝缘层406或层间绝缘体412，如图4中的圆圈452 所示。如上所述，高k材料层的合适的示例包括二氧化铪(HfO2)、氮氧化铪 (HfON)、二氧化锆(ZrO2)、氮氧化锆(ZrON)、氧化铝(Al2O3)、氮氧化铝(AlON)、氧化铪硅(HfSiO2)、氧化铪铝(HfAlO)、硅氧化锆(ZrSiO2)、二氧化钽(Ta2O5)、氧化铝、Y2O3、La2O3、氧化钛(TiO2)、铝掺杂的二氧化铪、铋锶钛(BST)和铂锆钛(PZT)等等。
图6A-6C描绘了任选的绝缘层404、栅极绝缘层406和层间绝缘体412的不同的膜堆叠布置或配置，如图4中的圆圈452所示。如上所述，在需要时，任选的绝缘层404、栅极绝缘层406和层间绝缘体412中的任一个(或全部)可以是高k材料，例如具有大于8的介电常数的介电材料，如图6A所示。任选的绝缘层404、栅极绝缘层406或层间绝缘体412的高k材料可以通过在ALD 腔室(诸如图7中所示的工艺腔室700)中执行的ALD工艺、在PECVD(诸如图 1中描绘的工艺腔室100)中执行的CVD工艺、或在制造工艺期间在CVD和 ALD工艺腔室中以任何顺序和任何时间执行的CVD-ALD混合工艺形成。
或者，栅极绝缘层406也可以是复合结构的形式，其中形成有多于一个层。在图6B中描绘的示例中，栅极绝缘层406类似于图5B和5C中描绘的介电层 424，其中形成有总共三个层602、604、606。更特定地，如上所述，栅极绝缘层406可以包括夹在顶部界面保护层606与底部界面保护层602之间的块体栅极绝缘层604。顶部界面保护层606可以与稍后形成在其上的层间绝缘体412 接触，同时底部界面保护层602可形成为与任选的绝缘层404接触。在此特定示例中，块体栅极绝缘层604可以由高k材料制造，而顶部界面保护层606 和底部界面保护层602可以是含硅介电材料，诸如氮化硅、氧化硅(SiO2)、氮氧化硅(SiON)、碳氧化硅(SiOC)、碳化硅(SiC)和类似物。在一个示例中，当块体栅极绝缘层606是高k材料时，顶部界面保护层606和底部界面保护层602 可以是氮氧化硅(SiON)或氮化硅(SiN)材料，就像如图5B或5C中描绘的介电层424。
或者，在图6C中描绘的另一示例中，层间绝缘体412也可以构造为在其中形成的多于一个层。在图6C中描绘的示例中，层间绝缘体412类似于图6C 中描绘的栅极绝缘层406，其中形成有总共三个层602、608、606。更特定地，如上所述，栅极层间绝缘体412可以包括夹在顶部界面保护层606与底部界面保护层602之间的块体层间绝缘体608。顶部界面保护层606可以与稍后形成在其上的平坦化层418(如图4所示)接触，而底部界面保护层602可形成为与栅极绝缘层406接触。在此特定示例中，块体层间绝缘体608可以由高k材料制造，而顶部界面保护层606和底部界面保护层602可以是含硅介电材料，诸如氮化硅、氧化硅(SiO2)、氮氧化硅(SiON)、碳氧化硅(SiOC)、碳化硅(SiC)和类似物。在一个示例中，当块体层间绝缘体608是高k材料时，顶部界面保护层606和底部界面保护层602可以是氮氧化硅(SiON)或氮化硅(SiN)材料，就像如图5B或5C中描绘的介电层424，或图6B中描绘的栅极绝缘层406。
因此，本文所述的方法有利地通过控制栅极绝缘层、器件中的绝缘材料、像素电极、公共电极连同形成在像素电极与公共电极之间的介电层的材料和结构提高了TFT器件结构的电子稳定性、电性能、高电容、低泄漏和良好的膜堆叠整合，以作为TFT器件结构中的高电性能电容器。
虽然前述内容针对的是本公开内容的实施方式，但是也可在不脱离本公开内容的基本范围的情况下设计本公开内容的其他和进一步实施方式，并且本公开内容的范围是由随附的权利要求书确定。

Claims (10)

1.一种薄膜晶体管结构，包括：
栅极电极，设置成覆于基板上方；和
电容器，形成在薄膜晶体管器件中，所述电容器进一步包括：
公共电极，设置在所述栅极电极上；
介电层，形成在所述公共电极上，其中所述介电层包括夹在顶部界面保护层与底部界面保护层之间的块体绝缘材料；和
像素电极，形成在所述介电层上，其中所述顶部界面保护层形成为与所述像素电极接触，且所述底部界面保护层形成为与所述公共电极接触，
其中所述介电层包括氮化硅，所述介电层具有大于8的介电常数，并且
其中所述顶部界面保护层和所述底部界面保护层包括氮氧化硅。
2.如权利要求1所述的结构，进一步包括：
栅极电极，形成在平坦化层下方，所述平坦化层设置在所述公共电极与所述基板之间。
3.如权利要求1所述的结构，其中所述公共电极和所述像素电极由选自由以下组成的群组的材料制成：氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)、银纳米油墨、碳纳米管(CNT)、石墨烯、铝(Al)、钨(W)、铬(Cr)、钽(Ta)、钛(Ti)、钼(Mo)、镁(Mg)、银(Ag)、金(Au)、铬(Cr)或以上的合金。
4.如权利要求1所述的结构，其中所述公共电极或所述像素电极是网格电极或栅格电极。
5.如权利要求1所述的结构，其中所述像素电极包括第一电极和设置在所述第一电极上的第二电极。
6.如权利要求5所述的结构，其中所述第二电极是网格电极或栅格电极。
7.一种在基板上形成电容器结构以供薄膜晶体管应用的方法，包括：
形成覆于所述基板上方而设置的栅极电极；
在用于形成薄膜晶体管器件的基板上形成公共电极；
在所述公共电极上形成介电层，其中所述介电层包括夹在顶部界面保护层与底部界面保护层之间的块体绝缘材料；和
在所述介电层上形成像素电极，其中在所述公共电极与所述介电层之间或所述介电层与所述像素电极之间形成界面保护层，其中所述顶部界面保护层形成为与所述像素电极接触，且所述底部界面保护层形成为与所述公共电极接触，
其中所述介电层包括氮化硅，所述介电层具有大于8的介电常数，并且
其中所述顶部界面保护层和所述底部界面保护层包括氮氧化硅。
8.如权利要求7所述的方法，其中所述像素电极是网格电极或栅格电极。
9.如权利要求7所述的方法，其中所述公共电极和所述像素电极由选自由以下组成的群组的材料制成：氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)、铝(Al)、钨(W)、铬(Cr)、钽(Ta)、钛(Ti)、钼(Mo)、镁(Mg)、银(Ag)、金(Au)、银纳米油墨、碳纳米管(CNT)、石墨烯或以上的合金。
10.如权利要求7所述的方法，其中所述像素电极包括第一电极和设置在所述第一电极上的第二电极，其中所述第二电极是网格电极或栅格电极。
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