CN108649043A - 一种提高硅原子的悬挂键键合的方法 - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000013078 crystal Substances 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000001301 oxygen Substances 0.000 claims abstract description 17
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 239000011241 protective layer Substances 0.000 claims abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 8
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- 239000000725 suspension Substances 0.000 claims 1
- -1 oxonium ion Chemical class 0.000 abstract description 13
- 239000007789 gas Substances 0.000 abstract description 10
- 230000001590 oxidative effect Effects 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 7
- 239000010703 silicon Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000007787 solid Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012806 monitoring device Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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Abstract
本发明公开了一种提高硅原子的悬挂键键合的方法,其属于半导体领域的技术,包括:步骤S1,对一晶圆表面进行氧化,形成一氧化硅层,所述氧化硅层的上表面具有悬挂键;步骤S2,于所述氧化硅层的上表面设置一介质层;步骤S3,在预设的第一温度下对所述介质层的表面进行富氧化处理;步骤S4,于所述介质层的上表面设置一保护层;步骤S5,对所述晶圆进行退火处理。该技术方案的有益效果是:本发明通过在保护层表面通以氧化气体,氧化气体中的氧离子穿透介质层到达晶圆表面,再经过高温退火处理后,使得晶体表面的硅原子不饱和键和氧离子键合,从而提高了晶圆表面的硅原子悬挂键的键合。
Description
技术领域
本发明涉及的是一种半导体领域的技术,具体是一种提高硅原子的悬挂键键合的方法。
背景技术
自上世纪60年代末期,美国贝尔实验室提出固态成像器件概念后,固体图像传感器便得到了迅速发展,成为传感技术中的一个重要分支。它是个人计算机多媒体不可缺少的外设,也是监控设备中的核心器件。
近年来,由于集成电路设计技术和工艺水平的提高,CMOS图像传感器(CMOS ImageSensor,CIS)因其固有的诸如像元内放大、列并行结构,集成度高、采用单电源和低电压供电、成本低和技术门槛低等特点得到更广泛地应用。同时,低成本、单芯片、功耗低和设计简单等优点使CIS在保安监视系统、可视电话、可拍照手机、玩具、汽车和医疗电子等低端像素产品领域中大出风头。
CMOS图像传感器,是一种典型的固体成像传感器。CMOS图像传感器通常由像敏单元阵列、行驱动器、列驱动器、时序控制逻辑、AD转换器、数据总线输出接口、控制接口等几部分组成,这几部分通常都被集成在同一块硅片上。其工作过程一般可分为复位、光电转换、积分、读出几部分。
CIS晶圆上的白色像素(White Pixel,WP)的数量是指在无光照条件下CIS器件输出的DN(Digital Number,DN)值大于64的像素数量,它是评估CIS器件性能的一个重要指标,直接反应器件成像质量。因此,提高CIS器件WP性能,即降低白色像素点数量是CIS器件制造工艺的一个长期目标。
悬挂键是化学键。一般晶体因晶格在表面处突然终止,在表面的最外层的每个原子将有一个未配对的电子,即有一个未饱和的键,这个键称为悬挂键。
制备CIS过程中,在高K介质层之下的硅界面处硅原子与氧原子键合形成二氧化硅层。然而,在现有的CIS制程工艺中,硅界面的硅原子的悬挂键形成键合的原子来源较少且缺乏键合动力,造成硅界面间悬挂键的键合程度较低,导致器件白色像素较多,降低了整个CIS的性能。
发明内容
本发明针对现有技术存在的上述不足,提出一种提高硅原子的悬挂键键合的方法,通过在保护层表面通以氧化气体,氧化气体中的氧离子穿透介质层到达晶圆表面,再经过高温退火处理后,使得晶体表面的硅原子不饱和键和氧离子键合,从而提高了晶圆表面的硅原子悬挂键的键合。
本发明是通过以下技术方案实现的:
本发明涉及一种提高硅原子的悬挂键键合的方法,其中,包括以下步骤:
步骤S1,对一晶圆表面进行氧化,形成一氧化硅层,所述氧化硅层的上表面具有悬挂键;
步骤S2,于所述氧化硅层的上表面设置一介质层;
步骤S3,在预设的第一温度下对所述介质层的表面进行富氧化处理;
步骤S4,于所述介质层的上表面设置一保护层;
步骤S5,对所述晶圆进行退火处理。
优选的,该提高硅原子的悬挂键键合的方法,其中,所述退火处理的温度范围为250~1400℃。
优选的,该提高硅原子的悬挂键键合的方法,其中,所述介质层为高K介质层。
优选的,该提高硅原子的悬挂键键合的方法,其中,所述高K介质层为五氧化二钽。
优选的,该提高硅原子的悬挂键键合的方法,其中,所述保护层为二氧化硅。
优选的,该提高硅原子的悬挂键键合的方法,其中,所述第一温度的范围为25~1400℃。
优选的,该提高硅原子的悬挂键键合的方法,其中,在所述步骤S3中,所述富氧化处理为向所述介质层的表面通以氧气。
优选的,该提高硅原子的悬挂键键合的方法,其中,在所述步骤S3中,所述富氧化处理为向所述介质层的表面通以臭氧。
优选的,该提高硅原子的悬挂键键合的方法,其中,在所述步骤S3中,所述富氧化处理为对所述介质层的表面进行灰化。
优选的,该提高硅原子的悬挂键键合的方法,其中,所述保护层通过化学气相沉积淀积于所述介质层表面。
上述技术方案的有益效果是:
本发明通过在保护层表面通以氧化气体,氧化气体中的氧离子穿透介质层到达晶圆表面,再经过高温退火处理后,使得晶体表面的硅原子不饱和键和氧离子键合,从而提高了晶圆表面的硅原子悬挂键的键合。
附图说明
图1为本发明的较佳的实施例中,一种提高硅原子的悬挂键键合的方法流程示意图;
图2为本发明的较佳的实施例中,淀积保护层后的晶圆结构示意图;
图3为本发明的较佳的实施例中,悬挂键键合示意图;
图中:1晶圆、2氧化硅层、3介质层、4保护层、5悬挂键、6氧离子。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
需要说明的是,在不冲突的情况下,本发明中的实施例及实施例中的特征可以相互组合。
下面结合附图和具体实施例对本发明作进一步说明,但不作为本发明的限定。
本实施例涉及一种提高硅原子的悬挂键键合的方法,通过在保护层表面通以氧化气体,氧化气体中的氧离子穿透介质层到达晶圆表面,再经过高温退火处理后,使得晶体表面的硅原子不饱和键和氧离子6键合,从而提高了晶圆表面的硅原子悬挂键5的键合。
如图1所示,本实施例中的提高硅原子的悬挂键5键合的方法包括以下步骤:
步骤S1,对一晶圆1表面进行氧化,形成一氧化硅层2,氧化硅层2的上表面具有悬挂键5;
步骤S2,于所述氧化硅层2的上表面设置一介质层3;
步骤S3,在预设的第一温度下,对介质层3的表面进行富氧化处理;
步骤S4,于所述介质层3的上表面设置一保护层4;
步骤S5,对整个晶圆1进行退火处理。
CIS中的MOS管的栅极制造过程中,首先需要在晶圆1表面设置一层薄的氧化硅层2。该氧化硅层2可以通过氧化的方式获得,也可以通过化学气相沉积工艺在晶圆表面进行淀积。
而后,在该氧化硅层2的上表面通过化学气象沉积工艺沉积介质层3。
如图2所示,在介质层3的表面设置保护层4,用于在后续的退火工艺中保护其下部的介质层3。
所述退火处理的温度范围为250~1400℃。
所述介质层3为高K介质层3。
较佳的实施例中,高K介质层3为五氧化二钽。
较佳的实施例中,保护层4为二氧化硅。
较佳的实施例中,第一温度的范围为25~1400℃。
较佳的实施例中,在所述步骤S3中,所述富氧化处理为向所述介质层3的表面通以氧气。
较佳的实施例中,在所述步骤S3中,所述富氧化处理为向所述介质层3的表面通以臭氧。
较佳的实施例中,在所述步骤S3中,所述富氧化处理为对所述介质层3的表面进行灰化。
如图3所示,在预设的第一温度下,向所述介质层3的表面进行富氧化处理过程中,介质层3的表面产生游离的氧离子6。在退火过程中,吸附的氧离子6加速扩散至氧化硅层2,与硅原子的悬挂键5进行键合,从而得到整体提高了氧化硅层2的硅原子的悬挂键5的键合。
CIS晶圆1经过本发明中的方法处理之后,CIS中的白像素数量与现有的工艺相比减少了15~20%。
本发明的提高硅原子的悬挂键键合的方法,与现有技术相比:
本发明通过在保护层表面通以氧化气体,氧化气体中的氧离子穿透介质层到达晶圆表面,再经过高温退火处理后,使得晶体表面的硅原子不饱和键和氧离子键合,从而提高了晶圆表面的硅原子悬挂键的键合。
以上所述仅为本发明较佳的实施例,并非因此限制本发明的实施方式及保护范围,对于本领域技术人员而言,应当能够意识到凡运用本发明说明书及图示内容所作出的等同替换和显而易见的变化所得到的方案,均应当包含在本发明的保护范围内。
Claims (10)
1.一种提高硅原子的悬挂键键合的方法,其特征在于,
包括以下步骤:
步骤S1,对一晶圆表面进行氧化,形成一氧化硅层,所述氧化硅层的上表面具有悬挂键;
步骤S2,于所述氧化硅层的上表面设置一介质层;
步骤S3,在预设的第一温度下对所述介质层的表面进行富氧化处理;
步骤S4,于所述介质层的上表面设置一保护层;
步骤S5,对所述晶圆进行退火处理。
2.根据权利要求1所述的提高硅原子的悬挂键键合的方法,其特征在于,所述退火处理的温度范围为250~1400℃。
3.根据权利要求1所述的提高硅原子的悬挂键键合的方法,其特征在于,所述介质层为高K介质层。
4.根据权利要求3所述的提高硅原子的悬挂键键合的方法,其特征在于,所述高K介质层为五氧化二钽。
5.根据权利要求1所述的提高硅原子的悬挂键键合的方法,其特征在于,所述保护层为二氧化硅。
6.根据权利要求1所述的提高硅原子的悬挂键键合的方法,其特征在于,所述第一温度的范围为25~1400℃。
7.根据权利要求1所述的提高硅原子的悬挂键键合的方法,其特征在于,在所述步骤S3中,所述富氧化处理为向所述介质层的表面通以氧气。
8.根据权利要求1所述的提高硅原子的悬挂键键合的方法,其特征在于,在所述步骤S3中,所述富氧化处理为向所述介质层的表面通以臭氧。
9.根据权利要求1所述的提高硅原子的悬挂键键合的方法,其特征在于,在所述步骤S3中,所述富氧化处理为对所述介质层的表面进行灰化。
10.根据权利要求1所述的提高硅原子的悬挂键键合的方法,其特征在于,所述保护层通过化学气相沉积淀积于所述介质层表面。
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