CN108630554A - 用联动导电连接组件以形成封装半导体装置的方法及结构 - Google Patents
用联动导电连接组件以形成封装半导体装置的方法及结构 Download PDFInfo
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- CN108630554A CN108630554A CN201710618460.4A CN201710618460A CN108630554A CN 108630554 A CN108630554 A CN 108630554A CN 201710618460 A CN201710618460 A CN 201710618460A CN 108630554 A CN108630554 A CN 108630554A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 73
- 238000005538 encapsulation Methods 0.000 title claims abstract description 22
- 238000000926 separation method Methods 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims description 17
- 238000009713 electroplating Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 37
- 238000005516 engineering process Methods 0.000 description 15
- 235000013339 cereals Nutrition 0.000 description 14
- 238000012545 processing Methods 0.000 description 14
- 229910000679 solder Inorganic materials 0.000 description 13
- 230000008569 process Effects 0.000 description 9
- 239000004020 conductor Substances 0.000 description 7
- 239000006071 cream Substances 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000010276 construction Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000003491 array Methods 0.000 description 4
- 238000005452 bending Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 229910000967 As alloy Inorganic materials 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- -1 acryl Chemical group 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003344 environmental pollutant Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000009740 moulding (composite fabrication) Methods 0.000 description 2
- 231100000719 pollutant Toxicity 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 235000008429 bread Nutrition 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 239000013070 direct material Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000013071 indirect material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/38—Structure, shape, material or disposition of the strap connectors prior to the connecting process of a plurality of strap connectors
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- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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Abstract
用联动导电连接组件以形成封装半导体装置的方法及结构。一种用于形成经封装的半导体装置的方法,其包含提供第一导电框架结构。所述方法包含耦合第二导电框架结构至所述第一导电框架结构以提供第一子组件,其中所述第二导电框架结构包含多个互连导电连接结构。所述方法包含藉由囊封层来囊封所述第一子组件以提供囊封子组件。所述方法包含移除所述第一导电框架结构的经结合的导电部分以形成置于所述囊封子组件的侧边表面上的多个导电侧翼表面。所述方法包含形成导电层于所述导电侧翼表面上。所述方法包含分离所述囊封子组件以提供所述经封装的半导体装置,每个经封装的半导体装置具有由所述导电层所覆盖的所述导电侧翼表面的部分。
Description
技术领域
本发明是关于电子元件,特别是关于半导体封装、其结构以及形成半导体封装的方法。
背景技术
在过去,经封装的功率半导体装置使用各种制造技术以沉积导电材料于导电引线框架的露出部。在离散功率半导体装置中,例如离散场效电晶体(FET)半导体装置或二极体半导体装置,制造业者使用矩阵引线框架,其通常包含晶粒附接垫的阵列,每个晶粒附接垫具有相邻配置的多个引线但是所述多个引线与所述晶粒附接垫隔离。半导体晶粒被附接至所述晶粒附接垫并且使用离散的、独立的或分离的连接结构(例如导线接合互连或夹具)电性地连接至所述引线。此子组件接着被囊封以提供模制封装本体给每个半导体晶粒。接着,所述囊封子组件被放置在电镀设备中并且导电材料被电镀到所述导电引线框架的露出的表面上。在所述电镀过程中,电流通过导电引线,其减少用以形成薄连续金属镀膜于所述导电引线框架的露出的表面上溶解的金属阳离子。
过去的方法有一个问题是,为了使电流通过整个导电引线框架,来自引线框架的相邻部分的某些引线必须结合在一起。在所述电镀制程之后,所述个别封装的半导体装置接着使用切割制程而被分隔开。所述切割制程分离所述结合的引线从而提供不具有电镀材料的引线面或侧翼(flank)表面。此留下不想要被露出的引线框架材料,其通常是铜。所述露出来的铜不与焊料附着,其产生较弱的焊料结合并且对于经组装的电子构件的可靠性有不利的影响。
试图去解决此问题,制造业者在所述结合的引线中凿孔洞、在所述结合的引线中产生半蚀刻区域或在所述结合的引线中使用侧边沟槽以提供覆盖有所述电镀材料的某些侧边表面或侧翼表面。虽然这些方案使得引线面的侧边或侧翼表面具有大约20%到60%之间的可附着表面覆盖率,然而这些方案无法提供100%的覆盖率,并且因此还是产生劣质焊料结合。再者,这些方案无法提供所述组装电路板层级(assembly board level)所需的足够坚固的焊料结合保护以满足严格的汽车规格,其需要100%可附着的侧覆盖率。
因此,还是期望能有一种提供经封装的半导体装置的方法和结构,其改善所述引线框架的侧边和侧翼表面的所述可附着表面覆盖率。并且也期望所述结构和方法可容易地并入制造流程中并且具有成本效益。
发明内容
除了其他特征外,本发明包含一种使用导电框架结构来制造经封装的半导体的方法,所述导电框架结构具有多个(即至少两个)一起联动的导电连接结构。所述联动的导电连接结构被用来传导电流到在另一导电框架结构上的导电构件,所述另一导电框架结构具有露出的导电侧翼表面有助于改善所述露出的导电侧翼表面中具有可焊材料的覆盖率。除了其他情况之外,所述方法以及所形成的结构提供经封装的半导体装置,其被建构以提供达到100%可附接侧翼表面。也就是,所述方法和结构提供实质上覆盖有可焊材料露出的侧边或导电侧翼表面,其有助于改善用于附接至下一层级的组件(例如印刷电路板)的可湿式附接(wettable)表面。所述方法和结构提供借助于相较于先前方案的较坚固的焊料接合的用于改善的可靠度。所述方法和结构适用于具有露出的侧翼或侧边表面的经封装的半导体装置以及其他电子装置,所述侧翼或侧边表面经建构用于随后沉积可焊材料,但是所述方法和结构不限于在所述经封装的半导体装置的两个相对侧上具有侧翼表面的功率半导体装置。
特别是在一个实施例中,一种用于形成经封装的半导体装置的方法包含提供第一导电框架结构。所述方法包含耦合第二导电框架结构到所述第一导电框架结构以提供第一子组件,其中所述第二导电框架结构包含多个互连导电连接结构。所述方法包含藉由囊封层来囊封所述第一子组件以提供囊封子组件。所述方法包含移除所述第一导电框架结构的经结合的导电部分以形成配置在所述囊封子组件的侧边表面上的多个导电侧翼表面。所述方法包含形成导电层在所述导电侧翼表面上。所述方法包含分离所述囊封子组件以提供所述经封装的半导体装置,每个经封装的半导体装置具有藉由所述导电层所覆盖的所述导电侧翼表面的部分。
在另一实施例中,一种制造经封装的电子装置的方法包含:提供第一导电框架结构,其包含具有第一导电构件的第一子结构;具有第二导电构件的第二子结构,其中所述第一导电构件是邻接所述第二导电构件以提供经结合的导电结构来连接所述第一子结构到所述第二子结构;第一电子晶粒被耦合至所述第一子结构;以及第二电子晶粒被耦合至所述第二子结构。所述方法包含:提供第二导电框架结构,其包含第一导电连接结构以及第二导电连接结构,其中所述第一导电连接结构是实际上互连至所述第二导电连接结构;附接所述第一导电连接结构至所述第一电子晶粒和所述第一导电构件;以及附接所述第二导电连接结构至至少所述第二电子晶粒以形成第一子组件。所述方法包含藉由囊封层来囊封所述第一子组件的部分以形成囊封子组件,其中所述第一导电框架结构的至少部分被曝露于所述囊封子组件的外侧。所述方法包含移除所有的所述经结合的导电结构以形成第一导电构件的曝露侧边表面以及第二导电构件的曝露侧边表面。所述方法包含形成导电层于所述第一导电框架结构的所述曝露表面上、于所述第一导电构件的曝露侧边表面上以及于所述第二导电构件的曝露侧边表面上。所述方法包含分离所述囊封子组件以提供第一封装电子装置和第二封装电子装置,所述第一封装电子装置具有藉由所述导电层所覆盖的所述第一导电构件的曝露侧边表面,所述第二封装电子装置具有藉由所述导电层所覆盖的所述第二导电构件的曝露侧边表面。
在进一步的实施例中,经封装的半导体装置包含晶粒附接垫、邻近所述晶粒附接垫配置的多个引线,每个引线具有引线底表面和引线末端表面。半导体晶粒被连接至所述晶粒附接垫并且导电夹具被附接至所述半导体晶粒和所述多个引线,其中所述导电夹具包含至少一个联结杆。封装本体囊封所述半导体晶粒、所述导电夹具、所述多个引线的部分、所述至少一个联结杆部分的至少部分以及所述晶粒附接垫的至少部分,其中每个引线末端表面曝露于所述封装本体的侧边表面上,并且其中所述至少一个联结杆的末端表面曝露于所述封装本体的所述外侧。导电层被配置在每个引线末端表面上但是没有被配置在所述至少一个联结杆的所述末端表面上。
附图说明
图1图示根据本发明的实施例的经封装的半导体装置的横截面视图以及局部透视图,其中所述横截面图沿着图3A的参考线1-1截取;
图2图示图1的所述经封装的半导体装置的部分的局部横截面视图;
图3A图示图1的所述经封装的半导体装置的俯视图,其中所述封装本体的部分被图示为局部透明;
图3B图示图3A的所述经封装的半导体装置的局部放大侧视图;
图4图示根据本发明的实施例的导电框架结构的俯视图,所述导电框架结构具有被附接至晶粒附接垫的电子晶粒;
图5图示根据本发明的实施例的导电框架结构的俯视图,所述导电框架结构具有互连导电连接结构;
图6图示图5的所述导电框架结构被配置以覆盖图4的所述导电框架结构的俯视图,其提供根据本发明的实施例的子组件;
图7图示图6的所述子组件沿着参考线7-7所得的横截面视图;
图8图示图6的所述子组件沿着参考线8-8所得的横截面视图;
图9图示根据本发明的实施例的进一步处理之后的图8的所述子组件的横截面视图;以及
图10图示根据本发明的实施例的额外处理之后的图9的所述子组件的横截面视图。
为了说明的简化及清楚起见,在图式中的元件并不一定是按照比例绘制的,并且在不同图中的相同的元件符号是表示相同的元件。此外,为了说明的简化起见,众所周知的步骤及元件的说明及细节被省略。如同在此所用的,术语"及/或"是包含相关被表列的项目中的一或多个的任一及所有的组合。此外,在此所用的术语只是为了描述特定实施例的目的而已,因而并不意图限制本揭露内容。如同在此所用的,除非上下文有清楚相反的指出,否则单数形亦意图包含复数形。进一步将会理解到的是,当术语"包括及/或包含"用在此说明书时,其指明所述特点、数量、步骤、操作、元件及/或构件的存在,但是并不排除一或多个其它特点、数量、步骤、操作、元件、构件及/或其群组的存在或是添加。将会了解到的是,尽管术语"第一、第二、等等"可能在此被使用来描述各种的构件、元件、区域、层及/或区段,但是这些构件、元件、区域、层及/或区段不应该受限于这些术语。这些术语只是被用来区别构件、元件、区域、层及/或区段的彼此而已。因此,例如在以下论述的一第一构件、一第一元件、一第一区域、一第一层及/或一第一区段可被称为一第二构件、一第二元件、一第二区域、一第二层及/或一第二区段,而不脱离本揭露内容的教示。对于"一个实施例"或是"一实施例"的参照是表示与所述实施例相关地叙述的一特定的特点、结构或特征是内含在本发明的至少一实施例中。因此,措辞"在一个实施例中"或是"在一实施例中"在遍及此说明书的各处中的出现并不一定都是参照到相同的实施例,但是在某些情形中其可能是参照到相同的实施例。再者,在一或多个实施例中,所述特定的特点、结构或是特征可以用对于本领域的技术人员而言将会是明显的任何适当的方式来加以组合。此外,术语"当"是表示某一动作是至少在起始的动作的一持续期间的某个部分之内发生的。字词"大约"、"大致"或是"实质"的使用是表示一元件的一值预期是接近一状态值或位置。然而,如同在此项技术中众所周知的,总是有防碍值或是位置不是刚好所述的较小的变异。除非另有指明,否则如同在此所用的字"在…之上"或是"在…上"是包含所指明的元件可以是直接或间接的实体接触所在的方位、设置或关系。进一步理解的是,在以下所描绘及叙述的实施例适当地可以具有在缺乏未明确地在此揭露的任何元件之下的实施例且/或加以实施。
具体实施方式
以下配合图式及本发明的较佳实施例,进一步阐述本发明为达成预定发明目的所采取的技术手段。
图1图示经封装的电子装置10的横截面视图和局部透视图,例如根据第一实施例的经封装的半导体装置10,其中所述横截面视图是沿着图3A的参考线1-1所取得的。根据所述实施例,经封装的半导体装置10包含晶粒附接垫11、晶粒垫11或支持垫11以及被配置与晶粒附接垫11相邻但是分隔开的引线12。在一个实施例中,电子晶片16或电子晶粒16,例如半导体装置16或半导体晶粒16是使用晶粒附接材料17而被连接或是附接至晶粒附接垫11。在某些实施例中,半导体装置16是功率半导体装置,例如功率场效电晶体(FET)结构、二极体结构或整流器结构。已了解的是,电子晶片16可为任何型态的电子装置。举例来说,晶粒附接材料17可为焊料膏、导电环氧树脂、导电黏着剂、导电膜、非导电环氧树脂、非导电黏着剂、非导电膜或所属技术领域中的技术人员所知道的其他适合的附接材料。在某些实施例中,非导电指的是电性绝缘并且要知道的是这些材料可能依然具有热传导性。
经封装的半导体装置10进一步包含导电连接结构19,其附接至半导体装置16的主要表面并且进一步连接一或多个引线12。在一较佳实施例中,导电连接结构19是导电夹式互连结构,其附接至引线12,一般来说如图3A所示。在其他的实施例中,导电连接结构19附接至单一引线12。在某些实施例中,导电连接结构19主要是由铜所组成,但是其他导电材料亦可被使用。如图1和3A所示,导电连接结构19包含晶粒附接部分191,其利用晶粒附接材料18而连接到半导体装置16,所述晶粒附接材料18可为焊料膏、导电环氧树脂、导电黏着剂、导电膜或所属技术领域中的技术人员所知道的其他适合的附接材料。导电连接结构19进一步包含接合部192,其以一角度向外延伸或延伸背离晶粒附接部分191以放置接合部192于一适当位置中而利用附接层23附接至引线12。举例来说,附接层23可为焊料膏、导电环氧树脂、导电黏着剂、导电膜或所属技术领域中的技术人员所知道的其他适合的附接材料。根据所述实施例,导电连接结构19经建构以提供电性互连至引线12用于传输电讯号往返于为已完成封装形式的半导体装置16;以及当为子组件形式时,在经封装的半导体装置16的制造过程中提供用于电镀目的的电性互连。
经封装的半导体装置10进一步包含封装本体36,其覆盖或是囊封导电连接结构19、半导体晶粒16、引线12的至少部分以及晶粒附接垫11的至少部分,而在某些实施例中,留下引线12的下或底表面122、引线12曝露于经封装的半导体装置10的外侧的导电侧边表面121(亦可称为导电侧翼表面121),如图1所示。在某些实施例中,封装本体36可为基于聚合物的复合材料,例如具有填充物的环氧树脂、具有填充物的环氧压克力或具有适当填充物的聚合物。封装本体36包含非导电且环保的材料,其保护半导体晶粒16免于受到外部元件和污染物的影响。封装主体36可以利用膏印刷、压缩模制、转移模制、双料射出成型(over-molding)、液体密封剂模制、真空叠层、其它适当的敷料器、或具有此项技术中的技能者已知的其它制程来加以形成。在某些实施例中,封装主体36是环氧树脂模制化合物("EMC"),并且可以利用转移或注入模制技术来加以形成。
根据所述实施例,导电侧边表面121或导电侧翼表面121是经由封装本体36的侧边表面360而曝露,并且进一步由导电层26(诸如可焊层26)所覆盖。举例来说,导电层26包含锡并且较佳地是根据所述实施例使用电镀技术而形成。在某些实施例中,导电层26进一步被配置在引线12的下表面122上以及晶粒附接垫11的底或下表面110上,一般来说如图1所示。
如下文中将详细描述的,在经封装的半导体装置10与其他封装半导体装置的一起制作过程中,例如子组件形式下,导电连接结构19是与其他导电连接结构(例如其他导电连接结构19)互连或联动在一起,其根据本实施例能够使导电层26被配置在引线12的所有导电侧翼表面121上。特别是,所述互连导电连接结构19能够使电流流经引线12以促进电镀过程中导电层26的形成以提供相较于现有结构或制程所述导电层26的增加的覆盖率。根据所述实施例,基本上所有的导电侧翼表面121都由导电层26所覆盖。特别是,在某些实施例中,每个导电侧翼表面121中有大于60%的表面是由导电层26所覆盖。在某些实施例中,每个导电侧翼表面121中有大于75%的表面是由导电层26所覆盖。在较佳的实施例中,每个导电侧翼表面121是大约100%或全部都由导电层26所覆盖。
图2图示经封装的半导体装置10的部分的局部横截面视图。参照图2,经封装的半导体10的部分是被图示为附接至下一层级的组件200,例如印刷电路板200,所述印刷电路板具有配置邻近于第一表面203的导电迹线201。根据所述实施例,引线12的导电侧翼表面121实质上是由导电层26所覆盖,其促进对于焊料附接材料24有大约100%的可湿式附接侧翼。相较于现有的方法无法在侧翼表面上提供大于60%的可焊材料的覆盖率,根据本发明实施例,其改善所述焊料结合强度以及组装构件的可靠度。
图3A图示经封装的半导体装置10的俯视图,其中封装本体36的部分被图示为局部透明以看到所述装置的内部部分。根据所述实施例,导电连接结构19进一步包含一个或多个联结杆194,例如其从导电连接结构19的晶粒附接部分191延伸朝向封装本体36的侧边表面361和362。在一较佳实施例中,导电连接结构19包含至少两个联结杆194分别在导电连接结构19的相对侧边196和197,一般如图3A所示。在一个实施例中,联结杆194经建构以互连、物理性连接或一起联动导电连接结构19与根据所述实施例的其他导电连接结构(例如其他导电连接结构19)。在一个实施例中,导电连接结构116(例如导线接合)电性地连接在半导体装置16上的其他垫部分到引线12,一般如图3A所示。
图3B是经封装的半导体装置10的局部放大侧视图,其描绘封装本体36的侧边表面362的一部分,其中联结杆194的远端表面195是经由封装本体36所曝露。根据所述实施例,远端表面195是缺乏导电材料26,因为联结杆194是在导电层26形成之后才被分离或单一化。
现在参考图4-10,将描述一种用于形成含有经封装的半导体装置10的封装电子装置或封装半导体装置的方法。图4图示根据第一实施例的具有附接到晶粒附接垫11的电子晶粒16(例如半导体晶粒)的导电框架结构40的俯视图。在制造的早先步骤中,导电框架结构40设有多个子结构41、42、43和44或是子框架结构41、42、43和44。在一个实施例中,导电框架结构40可被提供为NxM阵列的子结构,包含如图4中所示的2x2阵列。在某些实施例中,每个子结构可包含附接至导电框架51或框架51的晶粒附接垫11,框架51是与晶粒附接垫11分隔开并且围绕晶粒附接垫11。在某些实施例中,每个框架51可具有方形并且晶粒附接垫11可藉由一个或多个联结杆53及/或引线部511而被附接至框架51。引线12是被配置为与晶粒附接垫11分隔开但是邻近于晶粒附接垫11并且引线12可在距晶粒附接垫11远端的末端处被附接至框架51,一般如图4所示。
在某些实施例中,导电框架结构40包含被配置在导电框架结构40的一个侧边上的主要部分48或分接头部分48,其可进一步包含一个或多个孔洞49。在某些实施例中,在子结构中的对应于晶粒附接垫11的引线12仅被配置在晶粒附接垫11的一个侧边。在其他的实施例中,引线12可被配置在晶粒附接垫11的超过一个侧边上。一般如图4所示,子结构41的引线12具有远端末端,其被结合至在子结构42中自晶粒附接垫11向外延伸的引线部分511的远端末端。在某些实施例中,这些远端末端被结合之处被称为经结合的导电部分56。在某些实施例中,每个经结合的导电部分56包含介于引线12和引线部分511的所述远端末端之间的框架51的至少部分。可理解的是,经结合的导电部分56亦可以包含在邻近子结构中直接附接至晶粒附接垫11与引线12邻接的部分、可包含来自邻近子结构与引线12邻接的部分以及可包含其组合。一般来说,经结合的导电部分56是导电框架结构40的一些部分,这些部分将会被分离、单一化或在后续制程中被移除,从而曝露导电侧翼表面、导电侧边表面或所述引线的导电远端末端表面、引线部分、晶粒附接垫或在分离制程之后所曝露的导电部分。
根据所述实施例,框架结构40包含导电材料。在一个实施例中,导电框架结构40主要是由铜所组成并且为大约100μm到508μm的厚度。在其他的实施例中,框架结构40主要可由Fe-Ni(例如合金42)或是所属技术领域中的技术人员所知道的其他金属材料。导电框架结构40可使用遮罩及蚀刻技术、冲压(stamping)技术、弯曲或成形(bending or forming)技术、电镀技术、沉积技术、加工及/或前述的组合来加以形成或制造。如前文所述,每个电子晶粒16(例如半导体晶粒16)可使用晶粒附接材料17而被连接至晶粒附接垫11,一般如图1所示。在某些实施例中,每个电子晶粒16的垫部分是藉由导电连接结构116(例如导线接合结构)而被电性地连接至引线12。应理解的是,导电连接结构166可被形成在制造的后段步骤中,例如是在导电框架结构60被附接之后。
图5图示根据一实施例的具有互连导电连接结构19的导电框架结构60的俯视图,其可在制造步骤中被提供。根据所述实施例,导电框架结构60可被提供为NxM阵列,其相似于含有一般如图5所示2x2阵列的导电框架结构40。举例来说,导电框架结构60可经建构以包含多个子结构61、62、63及64或子框架结构61、62、63及64。根据所述实施例,在每个子结构61、62、63及64中的导电连接结构19是物理性且电性地互连或联动在一起,使得所述互连导电连接结构19可被用来在后续的电镀制程中提供电流至在导电框架结构40中的导电构件。在某些实施例中,所述导电连接结构19的每一个是被互连至导电框架71或框架71,框架71是与导电连接结构19分隔开并且围绕每个导电连接结构19,一般如图5所示。在某些实施例中,联结杆194被使用以将导电连接结构19与框架71互连在一起。在一较佳实施例中,每个导电连接结构19包含分别在导电连接结构19的相对侧边196和197上的至少两个联结杆194,一般如图5所示。在一较佳实施例中,联结杆194被定位在导电框架结构60之中以垂直于在导电框架结构40中的引线12。换句话说,联结杆194被定位使得当导电框架结构60附接至导电框架40时,联结杆194位于每个子组件的缺乏导电侧翼表面的侧边上,而所述侧边随后会被电镀。此构造避免当经结合的导电部分56被移除时,联结杆194被过早单一化。
在某些实施例中,导电框架结构60包含配置在导电框架结构60的一个侧边上的主要部分68或分接头部分68,其可进一步包含一个或多个孔洞69。如下文中将详细描述的,主要部分68经建构以物理性接触或电性连接至导电框架结构40的主要部分48以允许电流在电镀制程中流经导电框架结构40和包含导电互连结构19的导电框架结构60两者。
根据所述实施例,框架结构60包含导电材料。在一个实施例中,导电框架结构60主要是由铜所组成并且为大约100μm到508μm的厚度。在其他的实施例中,框架结构60主要可由Fe-Ni(例如合金42)或是所属技术领域中的技术人员所知道的其他金属材料。导电框架结构60可使用遮罩及蚀刻技术、冲压(stamping)技术、弯曲或成形(bending or forming)技术、电镀技术、沉积技术、加工及/或前述的组合来加以形成或制造。
图6图示导电框架结构60被配置而上覆于导电框架结构40以提供根据一实施例的子组件80的俯视图。在一个实施例中,在额外的步骤中,导电框架结构60和导电框架40被连接在一起,例如包含藉由附接导电连接结构19到半导体晶粒16以及到引线12而附接在一起。如前文所述的,每个导电连接结构19可利用晶粒附接材料18而附接至半导体晶粒16(图1所示),晶粒附接材料18可为焊料膏、导电环氧树脂、导电黏着剂、导电膜或是所属技术领域中的技术人员所知道的其他适合的附接材料。此外,每个导电连接结构19可利用附接层23而被附接至引线12(如图1所示),附接层23可为焊料膏、导电环氧树脂、导电黏着剂、导电膜或是所属技术领域中的技术人员所知道的其他适合的附接材料。在某些实施例中,额外的附接层418(如图7所示)可被用来附接导电框架结构60的其他部分到导电框架40,例如包含将主要部分68附接主要部分48,将此两个部分物理性接触在一起。所述额外的附接层418(图7所示)可为相似于晶粒附接材料18的材料。在此步骤中,根据所述实施例来提供子组件80。也可参考图6的部分401,根据本发明所述部分401后续将被移除,其进一步藉由图10而一起被描述。
图7图示图6的所述子组件80沿着参考线7-7所得的横截面视图,并且图8图示图6的所述子组件80沿着参考线8-8所得的横截面视图。如图7中所示,导电框架结构60的主要部分68例如藉由附接层418物理性接触导电框架结构40的主要部分48。根据所述实施例,此接触可被用于后续接触所述子组件至电镀设备的条状指部,条状指部将所述子组件悬挂于电镀液中。根据所述实施例,导电连接结构19是藉由联结杆194和框架71而被互连在一起或是联动在一起,并且进一步被互连至主要部分68。再者,此结构促进在所述电镀制程中电流传输至引线12以形成导电层26于引线12的所述导电侧翼表面121(图示为虚线)上。
图9图示在进一步制程之后的图8的子组件80的横截面视图。在一个实施例中,囊封步骤被用于形成一个或多个囊封封装本体36而覆盖子组件80的至少部分以提供囊封子组件90。在某些实施例中,封装本体36可为基于聚合物的化合物材料,例如具有填充物的环氧树脂、具有填充物的环氧压克力或具有适当填充物的聚合物。封装本体36包含非导电且环保的材料,其保护半导体晶粒16免于受到外部元件和污染物的影响。封装主体36可以利用膏印刷、压缩模制、转移模制、双料射出成型(over-molding)、液体密封剂模制、真空叠层、其它适当的敷料器或具有此项技术中的技能者已知的其它制程来加以形成。在某些实施例中,封装主体36是环氧树脂模制化合物("EMC"),并且可以利用转移或注入模制技术来加以形成。
图10图示在根据所述实施例的额外制程之后的囊封子组件90的横截面视图。根据所述实施例,囊封子组件90的部分(例如,部分401)被移除包含从导电框架结构40移除经结合的导电部分56。在一较佳实施例中,经结合的导电部分56全部被移除从而完全曝露引线12和引线部分511的所述末端表面(即,导电侧翼表面121)。在某些实施例中,局部切割制程被用以移除导电框架结构40的部分,其包含经结合的导电部分56。在某些实施例中,囊封层360的部分也被移除。其它制程可用于去除部分401,包括例如遮罩和蚀刻技术、烧蚀技术、雷射技术和本领域技术人员已知的其它技术。
在随后的步骤中,导电层26沿着导电框架结构40的曝露表面而配置,所述曝露表面包含例如晶粒附接垫11、引线12和引线部分511的曝露表面。在一较佳实施例中,囊封子组件被放入电镀槽或是电镀溶液中并且电流流经导电框架结构40和导电框架结构60以电镀导电层26于导电框架结构40的曝露表面上。根据所述实施例,互连导电连接结构19经建构以促进电性连接至引线12,从而电镀导电层26于引线12的曝露的导电侧翼表面121上,相较于现有制程和结构提供小于60%的覆盖率,所述实施例提供这些表面高达约100%的覆盖率。导电层26可为可焊材料,例如基于锡的焊料或是所述技术领域中的技术人员所知的其他可焊材料。在一个实施例中,导电层26可为雾锡(matte tin)材料,其具有厚度约300到800为英寸(大约7.6微米到大约23微米)。在一个实施例中,条状指部被附接至囊封子组件90的主要部分48和68以用于放置于所述电镀槽或是电镀溶液中。
在某些实施例中,在导电层26形成之后,囊封子组件90沿着例如分离区域403而被单一化或分离以提供多个经封装的半导体装置,例如经封装的半导体装置10。在某些实施例中,切割制程被用以单一化囊封子组件90,但是所属技术领域中的技术人员已知的其他分离制程亦可被使用。
在某些实施例中,一个或多个晶粒附接垫11、引线12、导电连接结构19、以及联结杆194、框架51、联结杆53、引线部分511、经结合的导电部分56、主要部分48、联结杆194、框架71、主要部分68及/或其部分是导电构件的非限制范例。
根据上文所述,所属技术领域中的技术人员可以根据一个实施例而判定耦合所述第二导电框架结构包含将所述第一导电框架结构的一部分物理性地接触所述第二导电框架结构。
在另外的实施例中,移除经结合的导电部分包含局部地切割所述囊封子组件以完全地移除所述经结合的导电部分。在另外的实施例中,形成所述导电层包含以大约100%覆盖所述导电侧翼表面来形成可焊材料。
根据上文所述,所属技术领域中的技术人员可以根据另一个实施例而判定移除所有的所述经结合的导电结构包含切割穿过所述经结合的导电结构。
在进一步的实施例中,形成所述导电层包含大约100%覆盖所述第一导电构件的曝露侧边表面;以及大约100%覆盖所述第二导电构件的曝露侧边表面。在另外的实施例中,形成所述导电层包含形成含有可焊材料的导电层。在另外的实施例中,
根据上文所述,显而易见的是,本发明揭露一种用于制造具有改善以可焊材料覆盖导电侧翼表面的覆盖率的经封装的半导体装置的新颖方法及结构。在其他特征中还有具有互连导电连接结构的导电框架结构,其被连接到在第二导电框架结构中的引线结构。所述导电框架结构促进电性连接至导电构件(例如引线),从而提供在所述导电侧翼表面上的改善的可焊材料覆盖率。当所述经封装的半导体装置被附接至下一层级的组件(例如印刷电路板)时,所述方法和结构提供达到100%的可湿式附接侧翼覆盖率。相较于现有结构和方法,本发明提供较坚固的焊料结合并且改善可靠度。所述方法和结构提供具有成本效益的解决方案以改善可湿式附接侧翼覆盖率并且可兼容于现有的组装方法中。
尽管本发明的目的是利用特定的较佳实施例以及范例实施例来加以描述,但是先前的图式以及其说明仅描绘所述典型的实施例而已,并且因此并不被视为其范畴的限制。显而易见的是,许多替代及变化对于本领域的技术人员而言都将会是明显的。
如同在以下的请求项所反映的,本发明的特点可以是在于少于单一先前所揭露的实施例的所有特点。因此,在以下所陈述的请求项是藉此明确地被纳入图式的此详细说明中,其中每一个请求项本身都独立作为本发明的一个别的实施例。再者,尽管在此所述的某些实施例是包含内含在其它实施例中的一些特点、而未包含其它特点,但是不同实施例的特点的组合也是有意要落在本发明的范畴内,并且有意形成如同本领域的技术人员将会理解的不同实施例。
Claims (10)
1.一种形成经封装的半导体装置的方法,包含:
提供第一导电框架结构;
耦合第二导电框架结构至所述第一导电框架结构以提供第一子组件,其中所述第二导电框架结构包含多个互连导电连接结构;
藉由囊封层来囊封所述第一子组件以提供囊封子组件;
移除所述第一导电框架结构的经结合的导电部分以形成配置在所述囊封子组件的侧边表面上的多个导电侧翼表面;
形成导电层在所述导电侧翼表面上;以及
分离所述囊封子组件以提供所述经封装的半导体装置,每个所述经封装的半导体装置具有藉由所述导电层所覆盖的所述导电侧翼表面的部分。
2.根据权利要求1所述的方法,其特征在于:
形成所述导电层包含使用所述多个互连导电连接结构来传递电流经过所述第一导电框架结构的部分以电镀所述导电层于所述导电侧翼表面上;
分离包含提供每个所述经封装的半导体装置具有曝露于所述囊封层的外侧的所述第二导电框架结构的远端末端部分;以及
所述远端末端部分是缺乏所述导电层。
3.根据权利要求1所述的方法,其特征在于:
提供所述第一导电框架结构包含提供:
第一晶粒附接垫;
与所述第一晶粒附接垫分隔开的第二晶粒附接垫;
配置于邻近所述第一晶粒附接垫的第一引线;以及
配置于邻近所述第二晶粒附接垫的第二引线,其中所述第一引线邻接到所述第二引线和所述第二晶粒附接垫中的一个以提供所述经结合的导电部分中的一个;
附接至所述第一晶粒附接垫的第一半导体晶粒;
附接至所述第二晶粒附接垫的第二半导体晶粒;
耦合所述第二导电框架结构包含:
附接第一导电连接结构至所述第一半导体晶粒和所述第一引线;以及
附接第二导电连接结构至所述第二半导体晶粒,其中所述第一导电连接结构是物理性地互连至所述第二导电连接结构;
囊封包含留下曝露于所述囊封子组件的外侧的所述第一导电框架结构的至少部分;以及
移除包含移除所述经结合的导电部分的一个以曝露所述第一引线的侧翼表面。
4.根据权利要求3所述的方法,其特征在于:
附接所述第一导电连接结构包含附接第一夹具结构;
附接所述第二导电连接结构包含附接第二夹具结构;
附接所述第二夹具结构进一步包含附接所述第二夹具结构至所述第二引线;以及
移除包含移除所述经结合的导电部分的全部。
5.根据权利要求3所述的方法,其特征在于:
提供所述第一导电框架结构包含提供物理性地连接至所述第二晶粒附接垫的所述第一引线,使得一个所述经结合的导电部分是介于所述第一引线和所述第二晶粒附接垫之间;以及
形成所述导电层包含:
形成所述导电层于所述第一晶粒附接垫和所述第二晶粒附接垫的底表面上;以及
形成所述导电层于所述第一引线和所述第二引线的底表面上。
6.一种制造经封装的电子装置的方法,其特征在于,包含:
提供第一导电框架结构包含:
具有第一导电构件的第一子结构;
具有第二导电构件的第二子结构,其中所述第一导电构件邻接至所述第二导电构件以提供连接所述第一子结构至所述第二子结构的经结合的导电结构;
耦合至所述第一子结构的第一电子晶粒;以及
耦合至所述第二子结构的第二电子晶粒;
提供第二导电框架结构包含:
第一导电连接结构;以及
第二导电连接结构,其中所述第一导电连接结构是物理性地互连至所述第二导电连接结构;
附接所述第一导电连接结构到所述第一电子晶粒和所述第一导电构件以及附接所述第二导电连接结构到至少所述第二电子晶粒以形成第一子组件;
藉由囊封层来囊封所述第一子组件的部分以形成囊封子组件,其中所述第一导电框架结构的至少部分被曝露于所述囊封子组件的外侧;
移除所有的所述经结合的导电结构以形成所述第一导电构件的曝露侧边表面和所述第二导电构件的曝露侧边表面;
形成导电层于所述第一导电框架结构的曝露表面上、于所述第一导电构件的所述曝露侧边表面上以及于所述第二导电构件的所述曝露侧边表面上;以及
分离所述囊封子组件以提供具有藉由所述导电层所覆盖的所述第一导电构件的所述曝露侧边表面的第一封装电子装置以及具有藉由所述导电层所覆盖的所述第二导电构件的所述曝露侧边表面的第二封装电子装置。
7.根据权利要求6所述的方法,其特征在于,其中形成所述导电层包含:
放置所述囊封子组件于电镀溶液之中;以及
将电流流经所述第一导电框架结构和所述第二导电框架结构以电镀所述导电层于所述第一导电框架结构的所述曝露表面上、于所述第一导电构件的所述曝露侧边表面上以及于所述第二导电构件的所述曝露侧边表面上。
8.根据权利要求6所述的方法,其特征在于:
提供所述第一导电框架结构包含:
提供所述第一导电构件包含引线;
提供所述第二导电构件包含晶粒附接垫;
提供所述第二导电框架结构包含:
提供第一夹具结构与第二夹具联动在一起;以及
提供所述第一夹具结构物理性地互连至所述第二导电框架结构于具有联结杆的至少两个侧边上;
附接所述第一导电连接结构包含使所述第一导电框架结构的部分物理性接触所述第二导电框架结构;以及
分离包含提供所述第一封装电子装置和所述第二封装电子装置的每一个具有曝露于所述囊封层的外侧的所述第二导电框架结构的远端末端部分,其缺乏所述导电层。
9.根据权利要求6所述的方法,其特征在于,其中形成所述导电层包含:
形成所述导电层于所述第一导电构件的下表面上;以及
形成所述导电层于所述第二导电构件的下表面上。
10.一种经封装的半导体装置,其特征在于,包含:
晶粒附接垫;
多个引线,其配置邻近于所述晶粒附接垫,每个引线具有引线底表面和引线末端表面;
半导体晶粒,其耦合至所述晶粒附接垫;
导电夹具,其附接至所述半导体晶粒和所述多个引线,其中所述导电夹具包含至少一个联结杆;
封装本体,其囊封所述半导体晶粒、所述导电夹具、所述多个引线的部分、所述至少一个联结杆的至少部分以及所述晶粒附接垫的至少部分,其中每个引线末端表面被曝露于所述封装本体的侧边表面上,且其中所述至少一个联结杆的末端表面被曝露于所述封装本体的外侧;以及
导电层,其配置于所述每个引线末端表面上但是没有配置于所述至少一个联结杆的所述末端表面上。
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US10199312B1 (en) | 2017-09-09 | 2019-02-05 | Amkor Technology, Inc. | Method of forming a packaged semiconductor device having enhanced wettable flank and structure |
US11069601B2 (en) * | 2018-02-27 | 2021-07-20 | Stmicroelectronics, Inc. | Leadless semiconductor package with wettable flanks |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004319996A (ja) * | 2003-04-02 | 2004-11-11 | Yamaha Corp | 半導体パッケージ、その製造方法、および、これに使用するリードフレーム |
US20090212405A1 (en) * | 2008-02-26 | 2009-08-27 | Yong Liu | Stacked die molded leadless package |
CN102789994A (zh) * | 2011-05-18 | 2012-11-21 | 飞思卡尔半导体公司 | 侧面可浸润半导体器件 |
CN207338306U (zh) * | 2017-03-15 | 2018-05-08 | 艾马克科技公司 | 用联动导电连接组件的经封装的半导体装置结构及子组件 |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2379330A (en) * | 2001-08-29 | 2003-03-05 | Motorola Inc | Package for electronic components and method for forming a package for electronic components |
WO2003038448A1 (en) * | 2001-10-26 | 2003-05-08 | Potter Michael D | An accelerometer and methods thereof |
US6608366B1 (en) * | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
US7064978B2 (en) * | 2002-07-05 | 2006-06-20 | Aplus Flash Technology, Inc. | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout |
US7059190B2 (en) * | 2003-10-08 | 2006-06-13 | Denso Corporation | Semiconductor dynamic sensor having variable capacitor formed on laminated substrate |
TWI272683B (en) | 2004-05-24 | 2007-02-01 | Sanyo Electric Co | Semiconductor device and manufacturing method thereof |
US7038308B2 (en) * | 2004-08-17 | 2006-05-02 | Delphi Technologies, Inc. | Multi-path bar bond connector for an integrated circuit assembly |
JP4468115B2 (ja) * | 2004-08-30 | 2010-05-26 | 株式会社ルネサステクノロジ | 半導体装置 |
US7238999B2 (en) * | 2005-01-21 | 2007-07-03 | Honeywell International Inc. | High performance MEMS packaging architecture |
DE102005057401B4 (de) * | 2005-11-30 | 2009-10-08 | Infineon Technologies Ag | Halbleiterbauteil und Verfahren zu dessen Herstellung |
US20090057852A1 (en) * | 2007-08-27 | 2009-03-05 | Madrid Ruben P | Thermally enhanced thin semiconductor package |
US7482664B2 (en) * | 2006-01-09 | 2009-01-27 | Microsoft Corporation | Out-of-plane electrostatic actuator |
US7663211B2 (en) * | 2006-05-19 | 2010-02-16 | Fairchild Semiconductor Corporation | Dual side cooling integrated power device package and module with a clip attached to a leadframe in the package and the module and methods of manufacture |
US7180019B1 (en) * | 2006-06-26 | 2007-02-20 | Temic Automotive Of North America, Inc. | Capacitive accelerometer or acceleration switch |
US7768105B2 (en) * | 2007-01-24 | 2010-08-03 | Fairchild Semiconductor Corporation | Pre-molded clip structure |
US7880280B2 (en) * | 2007-02-16 | 2011-02-01 | Infineon Technologies Ag | Electronic component and method for manufacturing an electronic component |
SG158048A1 (en) * | 2008-06-20 | 2010-01-29 | United Test & Assembly Ct Ltd | Copper on organic solderability preservative (osp) interconnect and enhanced wire bonding process |
US8187902B2 (en) * | 2008-07-09 | 2012-05-29 | The Charles Stark Draper Laboratory, Inc. | High performance sensors and methods for forming the same |
US8637953B2 (en) * | 2008-07-14 | 2014-01-28 | International Business Machines Corporation | Wafer scale membrane for three-dimensional integrated circuit device fabrication |
US8354740B2 (en) * | 2008-12-01 | 2013-01-15 | Alpha & Omega Semiconductor, Inc. | Top-side cooled semiconductor package with stacked interconnection plates and method |
US8124449B2 (en) * | 2008-12-02 | 2012-02-28 | Infineon Technologies Ag | Device including a semiconductor chip and metal foils |
US9899349B2 (en) * | 2009-01-29 | 2018-02-20 | Semiconductor Components Industries, Llc | Semiconductor packages and related methods |
US8071427B2 (en) * | 2009-01-29 | 2011-12-06 | Semiconductor Components Industries, Llc | Method for manufacturing a semiconductor component and structure therefor |
US8722537B2 (en) * | 2009-03-19 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-sacrificial layer and method |
JP4865829B2 (ja) * | 2009-03-31 | 2012-02-01 | シャープ株式会社 | 半導体装置およびその製造方法 |
US7736931B1 (en) * | 2009-07-20 | 2010-06-15 | Rosemount Aerospace Inc. | Wafer process flow for a high performance MEMS accelerometer |
US8470186B2 (en) * | 2010-11-24 | 2013-06-25 | HGST Netherlands B.V. | Perpendicular write head with wrap around shield and conformal side gap |
CA2792551A1 (en) * | 2011-01-17 | 2012-07-26 | Sumitomo Electric Industries, Ltd. | Method for manufacturing silicon carbide semiconductor device |
CN102593108B (zh) * | 2011-01-18 | 2014-08-20 | 台达电子工业股份有限公司 | 功率半导体封装结构及其制造方法 |
JP5706251B2 (ja) * | 2011-06-30 | 2015-04-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
FR2977885A1 (fr) * | 2011-07-12 | 2013-01-18 | Commissariat Energie Atomique | Procede de realisation d'une structure a electrode enterree par report direct et structure ainsi obtenue |
US8841758B2 (en) * | 2012-06-29 | 2014-09-23 | Freescale Semiconductor, Inc. | Semiconductor device package and method of manufacture |
US9620439B2 (en) | 2013-03-09 | 2017-04-11 | Adventive Ipbank | Low-profile footed power package |
CN107924901A (zh) | 2015-05-04 | 2018-04-17 | 创研腾科技有限公司 | 薄型底脚功率封装 |
US10930581B2 (en) * | 2016-05-19 | 2021-02-23 | Stmicroelectronics S.R.L. | Semiconductor package with wettable flank |
US10199312B1 (en) * | 2017-09-09 | 2019-02-05 | Amkor Technology, Inc. | Method of forming a packaged semiconductor device having enhanced wettable flank and structure |
-
2017
- 2017-03-15 US US15/460,032 patent/US10121742B2/en active Active
- 2017-06-14 TW TW106119789A patent/TWI746574B/zh active
- 2017-07-13 KR KR1020170088910A patent/KR102400444B1/ko active IP Right Grant
- 2017-07-26 CN CN201720913871.1U patent/CN207338306U/zh active Active
- 2017-07-26 CN CN201710618460.4A patent/CN108630554A/zh active Pending
-
2018
- 2018-07-30 US US16/049,735 patent/US10833008B2/en active Active
-
2020
- 2020-09-29 US US17/035,999 patent/US20210013142A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004319996A (ja) * | 2003-04-02 | 2004-11-11 | Yamaha Corp | 半導体パッケージ、その製造方法、および、これに使用するリードフレーム |
US20090212405A1 (en) * | 2008-02-26 | 2009-08-27 | Yong Liu | Stacked die molded leadless package |
CN102789994A (zh) * | 2011-05-18 | 2012-11-21 | 飞思卡尔半导体公司 | 侧面可浸润半导体器件 |
CN207338306U (zh) * | 2017-03-15 | 2018-05-08 | 艾马克科技公司 | 用联动导电连接组件的经封装的半导体装置结构及子组件 |
Also Published As
Publication number | Publication date |
---|---|
KR102400444B1 (ko) | 2022-05-20 |
CN207338306U (zh) | 2018-05-08 |
US10833008B2 (en) | 2020-11-10 |
US20180350735A1 (en) | 2018-12-06 |
US20210013142A1 (en) | 2021-01-14 |
TW201836104A (zh) | 2018-10-01 |
TWI746574B (zh) | 2021-11-21 |
KR20180105550A (ko) | 2018-09-28 |
US10121742B2 (en) | 2018-11-06 |
US20180269147A1 (en) | 2018-09-20 |
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