CN103681577B - 树脂密封型半导体装置及其制造方法 - Google Patents

树脂密封型半导体装置及其制造方法 Download PDF

Info

Publication number
CN103681577B
CN103681577B CN201310436876.6A CN201310436876A CN103681577B CN 103681577 B CN103681577 B CN 103681577B CN 201310436876 A CN201310436876 A CN 201310436876A CN 103681577 B CN103681577 B CN 103681577B
Authority
CN
China
Prior art keywords
pin
lead portion
semiconductor device
die pad
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201310436876.6A
Other languages
English (en)
Other versions
CN103681577A (zh
Inventor
木村纪幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN103681577A publication Critical patent/CN103681577A/zh
Application granted granted Critical
Publication of CN103681577B publication Critical patent/CN103681577B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48105Connecting bonding areas at different heights
    • H01L2224/48106Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858Bonding techniques
    • H01L2224/85801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

本发明提供一种树脂密封型半导体装置,该装置包括搭载于芯片垫部上的半导体元件、其前端部与芯片垫部对置配置的多个引脚部、将半导体元件的电极与引脚部连接的金属细线、将它们部分地密封的密封树脂和从密封树脂露出的芯片垫部的底面部、引脚部的底面部、外侧面部及上侧端部,在露出的引脚部的底面部及上侧端部施加镀敷层。

Description

树脂密封型半导体装置及其制造方法
技术领域
本发明涉及被称为QFN或DFN的无引脚型的树脂密封型半导体装置及其制造方法,特别地,提高引脚端子部的安装可靠性。
背景技术
近年来,为了应对电子设备的小型化,要求半导体部件的高密度安装,与此相伴的是,半导体部件的小型化、薄型化不断取得进展。与BGA和CSP封装件相比肩,作为使用引脚框架的小型封装件,DFN和QFN型的半导体装置得到实际应用。
图7(a)是现有的DFN封装件的背面图,图7(b)是其A-A线截面图。DFN封装件由密封树脂16将引脚部13和搭载于芯片垫部12的半导体元件11密封,使多个引脚部13和芯片垫部12从其背面露出。多个引脚部13在封装件背面沿着平行的2条直线排列,它们形成外部引脚。另外,多个引脚部13在密封树脂16内经由金属细线14而与半导体元件11的表面电极电连接。
DFN封装件,由于未使多个引脚部13从密封树脂16向外部突出,因而具有能够减小安装到安装基板的面积这一优点。另外,通过使芯片垫部12从密封树脂16露出,能够使内部的发热效率良好地向外部扩散。但是,在DFN封装件中,还存在将芯片垫部12密封于密封树脂16内的构造。QFN封装件是在封装件背面使外部引脚沿4个方向露出的构成。
图8是从上方观看树脂密封后的框架时的俯视图。图9是图8所图示的框架的切断后的B-B截面图。采用如下的方法:如图8和图9所示,在利用密封树脂16将搭载于框架框的各芯片垫部12的半导体元件11密封之后,沿着切断线,由划片装置的旋转刀片将密封树脂16和引脚部13同时切断,如图10所示,单片化成各个半导体装置(例如,参照专利文献1)。
专利文献1:日本特表2002-519848号公报(第7图)。
发明内容
这种树脂密封型半导体装置,在树脂密封后,利用旋转刀片将引脚部13的切断部位切断而从框架分离,得到各个半导体装置。然而,由于将引脚部13从框架切断而形成,因而在引脚部13的切断部的端面不存在镀敷层17,因而在使用焊料18将半导体装置接合于印刷基板等安装基板20时,在引脚部13的从密封树脂部露出的侧面部分,未形成焊料18所导致的焊料焊脚,有安装强度变弱且安装可靠性下降之虞。
如果参照附图而说明,作为图10所示的圆内的放大图,在图11中示出半导体装置的引脚部13,在引脚被切断的引脚部13的从密封树脂16露出的引脚部13的端面部,不存在形成于其他引脚部13的外部表面的镀敷层17。因此,如作为放大的安装状态的示意截面图的图12所示,在利用焊料18等接合剂将半导体装置安装于安装基板20时,在引脚部13的端面部分未形成焊料焊脚,安装强度下降。
本发明解决上述课题, 提供能够提高DFN或QFN类型的树脂密封型半导体装置的基板安装的强度及提高安装可靠性的半导体装置及其制造方法。
为了解决上述课题,使用如以下这样的方案。
首先,为一种树脂密封型半导体装置,是利用密封树脂将搭载于芯片垫部上的半导体元件、其前端部与所述芯片垫部对置配置的多个引脚部、将所述半导体元件的电极与所述引脚部连接的金属细线和将所述芯片垫部、半导体元件及所述引脚部部分地密封的树脂密封型半导体装置,其特征在于,所述芯片垫部的底面部和所述引脚部的底面部、外侧面部及上侧端部从所述密封树脂露出,在所述露出的引脚底面部和引脚上侧端部具有镀敷层。
另外,为一种树脂密封型半导体装置,其特征在于,具有所述镀敷层的引脚上侧端部以圆弧形状形成。
另外,为一种树脂密封型半导体装置,其特征在于,所述引脚底面部的镀敷层和所述引脚上侧端部的镀敷层由铅、铋、锡、铜、银、钯、金的任一个的金属层或2个以上的合金层构成。
另外,为一种树脂密封型半导体装置,其特征在于,在具有所述镀敷层的引脚上侧端部与密封树脂之间设有空间部。
另外,使用一种树脂密封型半导体装置的制造方法,其特征在于,由下列工序构成:以芯片垫部和其前端部对置配置的多个引脚部作为1个单元,准备具有多个该单元的框架或电铸基板的工序;将半导体元件搭载于所述框架或所述电铸基板的各芯片垫部,并由金属细线将所述引脚部与所述半导体元件表面的电极电连接的工序;在由密封树脂将所述芯片垫部、所述半导体元件以及所述引脚部密封时,将芯片垫部的底面部和引脚部的底面部露出的工序;对所述树脂密封后的框架或电铸基板的各单元的边界部分的引脚部的切断部位,从密封树脂的上表面侧利用旋转刀片来进行引脚预切割,留下一部分引脚部而在所述切断部位形成凹部的工序;对所述凹部的表面进行湿法蚀刻而形成引脚上侧端部的工序;将所述湿法蚀刻后的框架或电铸基板浸入镀敷液而在所述引脚底面部和所述引脚上侧端部形成镀敷层的工序;以及对所述切断部位的凹部利用旋转刀片或切断冲头来切断所述凹部残余引脚部而进行完全引脚切割,从框架分离树脂密封型半导体装置的工序。
发明的效果
通过使用上述手段,从而在将本发明的树脂密封型半导体装置焊接于印刷基板等安装基板的焊盘部时,由于焊料焊脚形成直至设于引脚部的引脚上侧端部19b的镀敷层,因而安装强度提高,能够提高安装可靠性。而且,在基板安装时,在引脚端面部形成有形状良好的焊料焊脚,由此,能够提高安装后的接合部的外观检查时的识别精度,降低识别不良。
附图说明
图1是搭载有本发明的一个实施例的半导体元件的框架的俯视图;
图2是示出本发明的一个实施方式的树脂密封型半导体装置的制造方法的俯视图(a)、截面图(b)~(d);
图3是示出与图2接续的本发明的一个实施方式的树脂密封型半导体装置的制造方法的截面图(e)~(h);
图4是示出本发明的一个实施方式的树脂密封型半导体装置的截面图;
图5是示出本发明的一个实施方式的树脂密封型半导体装置的截面图(引脚部的放大图);
图6是示出本发明的一个实施方式的树脂密封型半导体装置的截面图(安装状态的放大图);
图7是示出现有的树脂密封型半导体装置的图;
图8是示出现有的树脂密封型半导体装置的制造方法的框架俯视图;
图9是示出现有的树脂密封型半导体装置的制造方法的截面图;
图10是现有的树脂密封型半导体装置的截面图;
图11是示出现有的树脂密封型半导体装置的截面图(引脚部的放大图);
图12是示出现有的树脂密封型半导体装置的截面图(安装状态的放大图)。
具体实施方式
以下,参照附图,同时,对本发明的树脂密封型半导体装置及其制造方法的一个实施方式进行说明。首先,对本实施例的框架进行说明。
图1是搭载有本实施例的半导体元件的框架的俯视图,图2(a)是半导体元件搭载前的框架俯视图,图2(b)~图3(h)是示出半导体装置的制造方法的截面图。本实施例的半导体装置如图1所示,框架由铜(Cu)材构成,以搭载于芯片垫部12上的半导体元件11和其前端部与芯片垫部12对置配置的多个引脚部13作为1个单元,成为具有多个该单元的构成。图中的虚线表示在搭载半导体元件11而构成树脂密封型半导体装置的情况下由密封树脂16密封的区域,另外,由单点划线表示的部分表示在搭载半导体元件11之后进行树脂密封而构成树脂密封型半导体装置后、分离成各个半导体装置的切断线。
接着,对本实施例的树脂密封型半导体装置进行说明。图4是示出使用图1所示的框架的树脂密封型半导体装置的图,是图1所示的B-B截面图。
如图4所示,在框架的芯片垫部12上搭载有半导体元件11,该半导体元件11上的电极和引脚部13由金属细线14电连接。而且,芯片垫部12上的半导体元件11、引脚部13的外围由密封树脂16密封。而且,该引脚部13从密封树脂16的底面露出,引脚底面部19a构成外部端子。在DFN或QFN中,引脚底面部和密封树脂的底面大致成为相同的面。另外,成为引脚的前端的引脚外侧面部19c从密封树脂16的侧面露出。引脚外侧面部19c由于切断的方法而导致,不仅有时实质上成为与密封树脂16的侧面相同的面,而且有时还从密封树脂16的侧面稍微突出。而且,在本实施例的树脂密封型半导体装置中,在引脚外侧面部19c上设有连续的引脚上侧端部19b。由于引脚上侧端部19b其截面形成为圆弧形状,因而在引脚上侧端部19b与密封树脂16之间设有不存在密封树脂16的空间部。因此,引脚部13成为随着接近作为其前端的引脚外侧面部19c而厚度变薄的形状,密封树脂隔着空间部而存在于引脚上侧端部的垂直上方。此外,如果从密封树脂侧观看,则空间部成为作为密封树脂的垂直下方的在密封树脂与引脚上侧端部之间不存在引脚部的金属的区域。
引脚底面部19a和引脚上侧端部19b具有镀敷层17,镀敷层17由铅、铋、锡、铜、银、钯、金的任一金属或多个金属的合金构成,通过电解镀敷法或非电解镀敷法形成。
图5是将图4所示的引脚部13放大(○包围部)的放大图,图示出引脚部13、引脚底面部19a、引脚上侧端部19b、引脚外侧面部19c以及镀敷层17。
如图6所示,在利用焊料18将本实施例的树脂密封型半导体装置接合于印刷基板等安装基板20的焊盘部21时,由于在设于引脚部13的引脚上侧端部19b具有镀敷层17,因而在引脚部13的侧面部分形成有焊料焊脚,因而安装强度提高,能够提高安装可靠性。
接着,对本实施方式的树脂密封型半导体装置的制造方法进行说明。
如图2(a)所示,以在框架内载置半导体元件的矩形状的芯片垫部12和前端部与该芯片垫部12对置配置的多个引脚部13作为1个单元,准备具有多个该单元的由铜材构成的引脚框架。在引脚框架的底面侧,贴附有密封片15,该密封片15成为用于进行保护以使密封树脂不绕至引脚部13的底面而使引脚部13的底面露出的功能部件。
如图2(b)所示,由银膏等粘接剂(未图示)分别将半导体元件11芯片接合于引脚框架的各单元的芯片垫部12上,随后,如图2(c)所示,通过引线接合法而由金属细线14将半导体元件11上的电极垫(未图示)与引脚部13电连接。
接着,如图2(d)所示,通过传递模制法、利用由环氧系树脂构成的密封树脂16,作为引脚框架的外围而将芯片垫部12、半导体元件11、引脚部13的上表面区域与金属细线14的连接区域密封。
接着,如图3(e)所示,将密合于引脚框架的引脚部13的底面的密封片15除掉。在该状态下,芯片垫部12和引脚部13从密封树脂16露出。针对树脂密封后的引脚框架的引脚部13的切断部位,从密封树脂16侧通过划片法而利用旋转刀片,作为第1切断而进行预引脚切割,在切断部位形成凹部。该预引脚切割切割引脚部13的厚度的5%~80%。
接着如图3(f)所示,未被切割的残余引脚部,从密封树脂16面侧通过各向同性的湿法蚀刻而蚀刻成圆弧状的形状,形成作为湿法蚀刻部22的一部分的引脚上侧端部19b。
接着如图3(g)所示,针对引脚框架的引脚部13,在通过湿法蚀刻而形成为圆弧状的引脚部13的底面部19a、上侧端部19b以及芯片垫部12底面部形成镀敷层17。在此,通过电解镀敷法而形成锡100%组成的镀敷层。除了利用电解镀敷的方法以外,镀敷层17的形成也可以使用非电解镀敷。
在上述说明中,在图3(e)中进行密封片15的除去,但也可以在图3(f)的湿法蚀刻之后、即在镀敷层17形成之前进行。
接着如图3(h)所示,针对形成有镀敷层17的引脚部13的切断部位的凹部,从密封树脂16侧利用旋转刀片,作为第2引脚切割而进行完全切割,从引脚框架将树脂密封型半导体装置分离。此时,形成引脚外侧面部19c。在该工序中,由于残余的引脚部13的厚度变薄,因而能够无阻力地进行刀片切断。另外在本实施例中,利用旋转刀片作为第2引脚切割而进行完全切割,从引脚框架将树脂密封型半导体装置分离,但也可以使用利用模具冲头的切断法来分离。由此,能够防止引脚框架的引脚材料所导致的飞边(毛刺)的产生。
此外,在预引脚切割和完全引脚切割中使用的旋转刀片的宽度、形状也可以适当变更,将在完全引脚切割中使用的旋转刀片的宽度设定为比在预引脚切割中使用的旋转刀片的宽度更小。在这种情况下,作为引脚部13的前端的引脚外侧面部19c比密封树脂16的侧面稍微更突出至外侧。
以上,在本发明的树脂密封型半导体装置及其制造方法中,树脂密封型半导体装置在由焊料18将半导体装置接合于印刷基板等安装基板20的焊盘部21时,由于在设于引脚部13的引脚上侧端部19b具有镀敷层17,因而在引脚部13的侧面部分形成有焊料焊脚,因而安装强度提高,能够提高安装可靠性。而且,在基板安装时,在引脚端面部形成有形状良好的焊料焊脚,由此,能够提高安装后的接合部的外观检查时的识别精度,降低识别不良。
附图标记说明
11 半导体元件
12 芯片垫部
13 引脚部
14 金属细线
15 密封片
16 密封树脂
17 镀敷层
18 焊料
19a 引脚底面部
19b 引脚上侧端部
19c 引脚外侧面部
20 安装基板
21 焊盘部
22 湿法蚀刻部。

Claims (8)

1.一种树脂密封型半导体装置,具有:
芯片垫部;
半导体元件,搭载于所述芯片垫部上;
多个引脚部,与所述芯片垫部对置配置;
金属细线,将所述半导体元件的多个电极与所述多个引脚部连接;以及
密封树脂,以所述多个引脚部部分地露出的方式将所述芯片垫部、所述半导体元件以及所述多个引脚部密封,
所述树脂密封型半导体装置的特征在于,
所述多个引脚部具备从所述密封树脂露出的作为底面的引脚底面部、作为前端的引脚外侧面部以及作为上表面的一部分的引脚上侧端部,
所述引脚底面部位于与所述密封树脂的底面相同的面内,
所述引脚底面部和所述引脚上侧端部具有镀敷层,
所述密封树脂隔着所述密封树脂之下的空间部而存在于所述引脚上侧端部的垂直上方。
2.如权利要求1所述的树脂密封型半导体装置,其特征在于,具有所述镀敷层的引脚上侧端部的截面以圆弧形状形成。
3.如权利要求1所述的树脂密封型半导体装置,其特征在于,所述引脚底面部的镀敷层和所述引脚上侧端部的镀敷层由铅、铋、锡、铜、银、钯、金的任一个的金属层或2个以上的合金层构成。
4.如权利要求1所述的树脂密封型半导体装置,其特征在于,所述多个引脚部在所述密封树脂之下,随着接近所述引脚外侧面部而厚度变薄。
5.如权利要求1所述的树脂密封型半导体装置,其特征在于,所述芯片垫部的底面部从所述密封树脂露出。
6.如权利要求1所述的树脂密封型半导体装置,其特征在于,所述引脚外侧面部比所述密封树脂的侧面更突出至外侧。
7.一种树脂密封型半导体装置的制造方法,其特征在于,由下列工序构成:
以芯片垫部和与所述芯片垫部对置配置的多个引脚部作为1个单元,准备具有多个该单元的框架或电铸基板的工序;
将半导体元件搭载于所述框架或电铸基板的所述芯片垫部的各个,并由金属细线将所述引脚部和所述半导体元件表面的电极连接的工序;
以所述多个引脚部的底面部露出的方式,利用密封树脂对所述芯片垫部、所述半导体元件以及所述引脚部进行树脂密封的工序;
在被树脂密封的所述框架或电铸基板的各单元的边界部分的所述引脚部的切断部位,从所述密封树脂的上表面侧利用旋转刀片来进行引脚预切割,留下所述引脚部的一部分而在所述切断部位形成凹部的工序;
对所述凹部的表面进行湿法蚀刻而将引脚上侧端部形成直至成为所述密封树脂之下的区域的工序;
将湿法蚀刻之后的所述框架或电铸基板浸入镀敷液而在所述引脚底面部和所述引脚上侧端部形成镀敷层的工序;以及
在所述切断部位利用旋转刀片或切断冲头来切断形成有所述镀敷层的所述引脚部的剩余的部分而进行完全引脚切割、分离成各个的工序。
8.如权利要求7所述的树脂密封型半导体装置的制造方法,其特征在于,对所述芯片垫部、所述半导体元件以及所述引脚部进行树脂密封的工序包括将所述芯片垫部的底面部露出。
CN201310436876.6A 2012-09-24 2013-09-24 树脂密封型半导体装置及其制造方法 Expired - Fee Related CN103681577B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012209887A JP5959386B2 (ja) 2012-09-24 2012-09-24 樹脂封止型半導体装置およびその製造方法
JP2012-209887 2012-09-24

Publications (2)

Publication Number Publication Date
CN103681577A CN103681577A (zh) 2014-03-26
CN103681577B true CN103681577B (zh) 2017-10-20

Family

ID=50318671

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310436876.6A Expired - Fee Related CN103681577B (zh) 2012-09-24 2013-09-24 树脂密封型半导体装置及其制造方法

Country Status (5)

Country Link
US (2) US8994160B2 (zh)
JP (1) JP5959386B2 (zh)
KR (1) KR102054385B1 (zh)
CN (1) CN103681577B (zh)
TW (1) TWI587457B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163766B2 (en) * 2016-11-21 2018-12-25 Semiconductor Components Industries, Llc Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
US10199311B2 (en) 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
US9899349B2 (en) 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
JP6030970B2 (ja) 2013-02-12 2016-11-24 エスアイアイ・セミコンダクタ株式会社 樹脂封止型半導体装置およびその製造方法
JP2017079215A (ja) * 2014-02-27 2017-04-27 パナソニックIpマネジメント株式会社 樹脂封止型半導体装置、およびその製造方法、ならびにその実装体
US9837368B2 (en) * 2014-03-04 2017-12-05 Maxim Integrated Products, Inc. Enhanced board level reliability for wafer level packages
CN205282448U (zh) * 2015-05-28 2016-06-01 意法半导体股份有限公司 表面安装类型半导体器件
CN107534027B (zh) * 2015-06-15 2021-08-17 索尼公司 半导体装置、电子设备和制造方法
ITUB20155696A1 (it) * 2015-11-18 2017-05-18 St Microelectronics Srl Dispositivo a semiconduttore, corrispondenti procedimenti di produzione ed uso e corrispondente apparecchiatura
JP6577857B2 (ja) 2015-12-21 2019-09-18 ルネサスエレクトロニクス株式会社 半導体装置
JP6663294B2 (ja) * 2016-04-30 2020-03-11 新日本無線株式会社 半導体装置の製造方法
US10930581B2 (en) * 2016-05-19 2021-02-23 Stmicroelectronics S.R.L. Semiconductor package with wettable flank
CN107919339B (zh) * 2016-10-11 2022-08-09 恩智浦美国有限公司 具有高密度引线阵列的半导体装置及引线框架
JP6800745B2 (ja) * 2016-12-28 2020-12-16 株式会社ディスコ 半導体パッケージの製造方法
US10079198B1 (en) * 2017-05-31 2018-09-18 Stmicroelectronics, Inc. QFN pre-molded leadframe having a solder wettable sidewall on each lead
JP7037368B2 (ja) * 2018-01-09 2022-03-16 ローム株式会社 半導体装置および半導体装置の製造方法
JP7144157B2 (ja) * 2018-03-08 2022-09-29 エイブリック株式会社 半導体装置およびその製造方法
CN110265305B (zh) * 2019-05-17 2024-04-12 珠海市万州光电科技有限公司 一种贴片式红外支架及其生产工艺、红外接收头
US20230098907A1 (en) * 2021-09-30 2023-03-30 Texas Instruments Incorporated Package geometries to enable visual inspection of solder fillets

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
CN1381886A (zh) * 2001-04-13 2002-11-27 雅马哈株式会社 半导体器件和封装及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0730042A (ja) * 1993-07-13 1995-01-31 Sony Corp 半導体装置用リードフレーム、それを用いた半導体装置及びその製造方法
US6608366B1 (en) * 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
JP3915794B2 (ja) * 2003-04-02 2007-05-16 ヤマハ株式会社 半導体パッケージ、その製造方法、および、これに使用するリードフレーム
US7195953B2 (en) * 2003-04-02 2007-03-27 Yamaha Corporation Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein
JP3789443B2 (ja) * 2003-09-01 2006-06-21 Necエレクトロニクス株式会社 樹脂封止型半導体装置
JP2005191240A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
US8067823B2 (en) * 2004-11-15 2011-11-29 Stats Chippac, Ltd. Chip scale package having flip chip interconnect on die paddle
US7880313B2 (en) * 2004-11-17 2011-02-01 Chippac, Inc. Semiconductor flip chip package having substantially non-collapsible spacer
JP2006165411A (ja) * 2004-12-10 2006-06-22 New Japan Radio Co Ltd 半導体装置およびその製造方法
US7608484B2 (en) * 2006-10-31 2009-10-27 Texas Instruments Incorporated Non-pull back pad package with an additional solder standoff
JP5343334B2 (ja) * 2007-07-17 2013-11-13 株式会社デンソー 溶接構造体およびその製造方法
JP2010067768A (ja) * 2008-09-10 2010-03-25 Fuji Electric Systems Co Ltd 半導体パッケージの製造方法および半導体パッケージ
JP2011077278A (ja) * 2009-09-30 2011-04-14 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US8501539B2 (en) * 2009-11-12 2013-08-06 Freescale Semiconductor, Inc. Semiconductor device package
JP5525335B2 (ja) * 2010-05-31 2014-06-18 株式会社日立製作所 焼結銀ペースト材料及び半導体チップ接合方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
CN1381886A (zh) * 2001-04-13 2002-11-27 雅马哈株式会社 半导体器件和封装及其制造方法

Also Published As

Publication number Publication date
US8994160B2 (en) 2015-03-31
JP5959386B2 (ja) 2016-08-02
US20140084435A1 (en) 2014-03-27
US20150147848A1 (en) 2015-05-28
JP2014067750A (ja) 2014-04-17
KR102054385B1 (ko) 2020-01-22
TW201423917A (zh) 2014-06-16
KR20140040026A (ko) 2014-04-02
CN103681577A (zh) 2014-03-26
US9136247B2 (en) 2015-09-15
TWI587457B (zh) 2017-06-11

Similar Documents

Publication Publication Date Title
CN103681577B (zh) 树脂密封型半导体装置及其制造方法
CN104685615B (zh) 半导体器件的制造方法及半导体器件
KR102082941B1 (ko) 수지 봉지형 반도체 장치 및 그 제조 방법
US9583449B2 (en) Semiconductor package
US20200365494A1 (en) Leadless semiconductor packages, leadframes therefor, and methods of making
KR101286874B1 (ko) 반도체 장치 및 그 제조 방법
CN104465544B (zh) 半导体装置及其制造方法
CN107170716B (zh) 半导体封装件及半导体封装件的制造方法
US8133759B2 (en) Leadframe
US20140361444A1 (en) Semiconductor device with overlapped lead terminals
JP6770853B2 (ja) リードフレーム及び電子部品装置とそれらの製造方法
US8076181B1 (en) Lead plating technique for singulated IC packages
TW200818458A (en) Stackable packages for three-dimensional packaging of semiconductor dice
JP2005191240A (ja) 半導体装置及びその製造方法
US9363901B2 (en) Making a plurality of integrated circuit packages
JP2003174131A (ja) 樹脂封止型半導体装置及びその製造方法
US20210265214A1 (en) Methods and apparatus for an improved integrated circuit package
CN107017221B (zh) 集成电路组合件
JP2019145625A (ja) 半導体装置
TW201025463A (en) Manufacturing process of a leadless semiconductor package process and its structure
JP2003297997A (ja) リードフレーム及び同リードフレームを用いた半導体装置並びにその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20160304

Address after: Chiba County, Japan

Applicant after: DynaFine Semiconductor Co.,Ltd.

Address before: Chiba, Chiba, Japan

Applicant before: Seiko Instruments Inc.

GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Chiba County, Japan

Patentee after: ABLIC Inc.

Address before: Chiba County, Japan

Patentee before: DynaFine Semiconductor Co.,Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171020