CN108574006A - 具有t形栅极电极的场效应晶体管 - Google Patents

具有t形栅极电极的场效应晶体管 Download PDF

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Publication number
CN108574006A
CN108574006A CN201810207859.8A CN201810207859A CN108574006A CN 108574006 A CN108574006 A CN 108574006A CN 201810207859 A CN201810207859 A CN 201810207859A CN 108574006 A CN108574006 A CN 108574006A
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dielectric layer
gate electrode
opening
section
dielectric
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CN108574006B (zh
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史蒂芬·M·宣克
亚文·Ｊ·乔瑟夫
约翰·J·艾利斯蒙纳翰
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GlobalFoundries US Inc
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GlobalFoundries Inc
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Abstract

本发明涉及具有T形栅极电极的场效应晶体管，揭露场效应晶体管的装置结构以及形成场效应晶体管的装置结构的方法。形成第一介电层，以及在该第一介电层上形成第二介电层。形成垂直延伸穿过该第一及第二介电层的开口。在形成该第一开口以后，通过选择性蚀刻工艺相对该第一介电层横向凹入该第二介电层，以相对垂直延伸穿过该第一介电层的该开口的一部分，加宽垂直延伸穿过该第二介电层的该开口的一部分。在横向凹入该第二介电层以后，形成栅极电极，该栅极电极包括位于垂直延伸穿过该第一介电层的该开口的该部分中的窄段以及位于垂直延伸穿过该第二介电层的该开口的该部分中的宽段。

Description

具有T形栅极电极的场效应晶体管
技术领域
本发明涉及半导体装置制造及集成电路，尤其涉及场效应晶体管的装置结构以及形成场效应晶体管的装置结构的方法。
背景技术
互补金属氧化物半导体(complementary-metal-oxide-semiconductor；CMOS)工艺(process)可用以构建p型场效应晶体管(p-type field-effect transistor；pFET)与n型场效应晶体管(n-type field-effect transistor；nFET)的组合，该些晶体管经耦接以实施逻辑门(logic gate)及其它类型的集成电路，例如开关。场效应晶体管通常包括本体区、定义于该本体区中的源极及漏极，以及与该本体区中的沟道关联的栅极电极。当向该栅极电极施加超过指定阈值电压的控制电压时，在该源极与漏极之间的该沟道中的反型或耗尽层中发生载子流动(carrier flow)，从而产生装置输出电流。
绝缘体上硅(silicon-on-insulator；SOI)衬底在CMOS工艺中可能是有利的。与利用块体硅晶圆构建的场效应晶体管相比，绝缘体上硅衬底允许场效应晶体管以显着较高的速度操作，改进电性隔离并降低电性损失。依据该SOI衬底的装置层的厚度，场效应晶体管可以部分耗尽模式操作，其中，当向栅极电极施加典型的控制电压时，位于本体区内的沟道中的耗尽层不完全延伸至埋置氧化物层。
需要改进的场效应晶体管的装置结构以及形成场效应晶体管的装置结构的方法。
发明内容
在本发明的一个实施例中，一种方法包括形成第一介电层以及位于该第一介电层上的第二介电层。形成垂直延伸穿过该第一及第二介电层的开口。在形成该开口以后，通过选择性蚀刻工艺相对该开口内部的该第一介电层横向凹入该第二介电层，以相对垂直延伸穿过该第一介电层的该开口的一部分，加宽垂直延伸穿过该第二介电层的该开口的一部分。在横向凹入该第二介电层以后，形成栅极电极，该栅极电极包括位于垂直延伸穿过该第一介电层的该开口的该部分中的窄段(narrow section)及位于垂直延伸穿过该第二介电层的该开口的该部分中的宽段(wide section)。
在本发明的一个实施例中，一种结构包括：包括延伸至衬底的顶部表面的开口的介电层，以及位于该开口内部及该衬底的该顶部表面上的栅极介电质。该结构还包括栅极电极，该栅极电极包括宽段及窄段，该窄段垂直位于该宽段与该栅极介电层之间，且该窄段位于该介电层中的该第一开口内部。
附图说明
包含于并构成本说明书的一部分的附图说明本发明的各种实施例，并与上面所作的本发明的概括说明以及下面所作的实施例的详细说明一起用以解释本发明的实施例。
图1至图8显示依据本发明的实施例处于工艺方法的连续阶段中的装置结构的剖视图。
图9显示依据本发明的实施例的装置结构的剖视图。
具体实施方式
请参照图1并依据本发明的实施例，以绝缘体上硅(SOI)衬底为代表形式的衬底10包括装置层12，采用由硅的氧化物(例如，SiO2)组成的埋置氧化物(buried oxide；BOX)层14的形式的埋置介电层，以及操作晶圆(handle wafer)16。装置层12及BOX层14终止于操作晶圆16的边缘。装置层12通过中间的BOX层14与操作晶圆16隔开且可远薄于操作晶圆16。装置层12通过BOX层14与操作晶圆16电性隔离。装置层12与操作晶圆16可由单晶半导体材料例如硅组成。BOX层14具有沿界面与装置层12直接接触的顶部表面以及沿另一个界面与操作晶圆16直接接触的底部表面，且这些表面通过BOX层14的厚度隔开。操作晶圆16可经轻掺杂以具有例如p型导电性。
沟槽隔离区18形成于装置层12中，并将装置层12划分为本体区15、17。通过沉积介电材料来填充沟槽并利用例如化学机械抛光(chemical-mechanical polishing；CMP)平坦化该介电材料可形成沟槽隔离区18。构成沟槽隔离区18的该介电材料可为电性绝缘体，例如通过化学气相沉积(chemical vapor deposition；CVD)沉积的硅的氧化物(例如，二氧化硅(SiO2))。
在衬底10的顶部表面11(包括装置层12及沟槽隔离区18的顶部表面)上形成屏蔽氧化物层20。在装置层12中所定义的本体区15中形成阱(well)期间，屏蔽氧化物层20保护位于衬底10的顶部表面11的装置层12。在一个实施例中，该阱可为p阱，通过在给定的注入条件下注入选自周期表的第III族的p型掺杂物(例如，硼)离子使装置层12的组成半导体材料具有p型导电性来形成该P阱。
请参照图2，其中类似的附图标记表示图1中类似的特征且在下一制造阶段，在屏蔽氧化物层20上顺序形成介电层22、24、26作为堆叠。以屏蔽氧化物层20为中间层，介电层22形成于衬底10的顶部表面11上，介电层24形成于介电层22的顶部表面上，以及介电层26形成于介电层24的顶部表面上。介电层22、26可由相同的电性绝缘体组成，例如通过CVD沉积的二氧化硅(SiO2)。介电层24可由具有与介电层22及介电层26不同的蚀刻选择性的电性绝缘体组成。在介电层22、26由二氧化硅组成的一个实施例中，介电层24可由通过CVD所沉积的氮化硅(Si3N4)组成。
通过使用光刻及一个或多个蚀刻工艺图案化介电层22、24、26及屏蔽氧化物层20，以定义开口28、30。开口28与装置层12的本体区15对齐，且开口30与装置层12的本体区17对齐。在一个实施例中，可同时形成开口28、30。延伸穿过介电层26的开口28、30的一部分可沿朝向介电层24的方向向内收窄并与延伸穿过层22、24的开口的部分相比加宽。通过调节用以蚀刻穿过介电层26的该蚀刻工艺的横向及垂直分量可设置该收窄。
请参照图3，其中类似的附图标记表示图2中类似的特征且在下一制造阶段，通过停止于操作晶圆16的材料上的一个或多个蚀刻工艺使开口30沿深度垂直延伸穿过装置层12并穿过BOX层14至操作晶圆16。可施加蚀刻掩膜(未显示)，当沿深度延伸开口30时，该蚀刻掩膜覆盖开口28。
接着，通过蚀刻工艺相对介电层22及介电层24横向凹入介电层24，以形成垂直位于介电层22上方并垂直位于介电层26下方的腔体25。在腔体25的位置，与保留初始宽度的延伸穿过介电层22的开口28的部分相比，延伸穿过介电层24的开口28的一部分通过形成腔体25而被加宽。沿介电层24的厚度，腔体25相对开口28的垂直中心线对称地设置。若介电层22、26由二氧化硅组成且介电层24由氮化硅组成，则可选择用于相对二氧化硅选择性地等向性蚀刻氮化硅的湿式或干式蚀刻工艺的蚀刻化学。例如，合适的蚀刻化学可为用以相对二氧化硅选择性湿化学蚀刻氮化硅的热磷酸(hot phosphoric acid)。
横向凹入介电层24的该蚀刻工艺也相对装置层12及BOX层14的材料选择性移除介电层24的材料。本文中所使用的关于材料移除工艺(例如，蚀刻)的术语“选择性”表示目标材料的材料移除速率(也就是，蚀刻速率)高于暴露于该材料移除工艺的至少另一种材料的材料移除速率(也就是，蚀刻速率)。在通过开口28暴露的装置层12以及毗邻开口30的侧壁的装置层12的半导体材料上可形成可选的保护层(未显示)。
请参照图4，其中类似的附图标记表示图3中类似的特征且在下一制造阶段，在开口28内部的装置层12的顶部表面上形成栅极介电层32。栅极介电层32可由介电材料例如二氧化硅(SiO2)构成，其可通过氧化装置层12的顶部表面生长。薄介电材料层可同时形成于位于开口30的底部的操作晶圆16上，且可在掩蔽开口28的情况下通过蚀刻移除。
用半导体材料填充开口28以定义T形栅极电极35，以及用半导体材料填充开口30以定义至操作晶圆16的接触31。在一个实施例中，用同一半导体材料沉积层的部分同时填充开口28与开口30。在一个实施例中，该半导体材料可包括多晶硅半导体材料例如未掺杂多晶硅(也就是，多晶硅)、或者非晶半导体材料例如非晶硅，其通过CVD沉积并通过例如CMP相对介电层26的顶部表面平坦化。位于介电层26中的开口28、30的该收窄部分可提升沿开口28、30的深度填充的能力。相对介电层26凹入所沉积的半导体材料，并在凹入以后，通过湿化学蚀刻工艺(例如，缓冲氢氟酸)可剥离介电层26。
填充开口28以形成栅极电极35的该半导体材料顺应开口28的组合形状及几何。尤其，与沿介电层22的厚度位于开口28中的该半导体材料的窄段36相比，沿介电层24的厚度位于开口28中的该半导体材料的宽段34较宽。窄段36垂直位于宽段34与栅极介电层32之间，且宽段34的增加宽度起因于先前相对介电层22及26横向凹入介电层24而形成腔体25。
该半导体材料的段34、36共同形成场效应晶体管的T形栅极电极35。宽段34的宽度w1大于窄段36的宽度w2。在一个实施例中，栅极电极35的宽段34可为20纳米至100纳米厚，且栅极电极35的宽段34的宽度可为0.15微米至0.09微米。在一个实施例中，栅极电极35的窄段36可为20纳米至100纳米厚，且栅极电极35的窄段36的宽度可小于0.09微米。
位于开口30内部的该半导体材料顺应开口30的组合形状及几何，并定义可在装置层12的顶部表面访问的至操作晶圆16的接触31。尤其，接触31包括由该组成半导体材料构成的宽段38以及垂直位于宽段38与操作晶圆16之间的由该组成半导体材料构成的窄段40。宽段38位于沿介电层24的厚度位于开口30中，且窄段40沿介电层22、装置层12及BOX层14的厚度位于开口30中。宽段38的增加宽度起因于先前相对介电层22及26横向凹入介电层24。
请参照图5，其中类似的附图标记表示图4中类似的特征且在下一制造阶段，通过蚀刻工艺移除介电层24，例如用热磷酸以相对二氧化硅及多晶硅选择性湿化学蚀刻氮化硅。在该栅极电极的宽段34中、该操作晶圆接触的宽段38中，以及邻近栅极电极35的窄段36的浅深度处的装置层12中通过离子注入分别形成掺杂区42、44、46。在一个实施例中，该注入可以有效使该半导体材料具有n型导电性的浓度提供选自周期表的第V族的n型掺杂物离子(例如，砷(As)或磷(P))。
在该栅极电极的窄段36下方的浅深度处的装置层12中通过离子注入形成掺杂区48。在一个实施例中，该注入可以有效使装置层12的组成半导体材料具有p型导电性的浓度提供选自周期表的第III族的p型掺杂物离子(例如，硼)。
在各种情况下，该离子可自合适的源气体生成并用离子注入工具通过所选注入条件(例如，离子种类、剂量、动能、倾斜角度)注入。与栅极电极35的窄段36相邻的装置层12中的掺杂区46可代表后续形成的源/漏区的延伸区。位于栅极电极35的窄段36下方的装置层12中的掺杂区48可代表与后续形成的源/漏区关联的环状区(halo)。该注入条件可经选择以在装置层12中的所需位置设置掺杂区46及掺杂区48。与掺杂区48相比，掺杂区46位于装置层12中的浅深度。
运用栅极电极35的宽段34及栅极电极35的窄段36的双厚度的双重穿栅极注入用以自对准延伸区及环状区注入至沟道区。各次注入的能量可经调整以被栅极电极35的宽段34及栅极电极35的窄段36的其中一者或两者阻挡。在经选择以穿过栅极电极35的宽段34及栅极电极35的窄段36并停止于装置层12的本体区15中的注入条件(例如，动能)下通过注入形成掺杂区48。在经选择以穿过栅极电极35的宽段34而不穿过栅极电极35的窄段36并停止于装置层12的本体区15中的注入条件(例如，动能)下通过注入形成于装置层12中的掺杂区46。用以形成掺杂区48的该注入的离子动能可高于用以形成掺杂区46的该注入的离子动能。掺杂区48被埋置于装置层12的本体区15的顶部下方的上段下方，以减小电场，从而降低漏电流并改进低噪声(noise)放大器应用的增益。
请参照图6，其中类似的附图标记表示图1中类似的特征且在下一制造阶段，在所述注入之后接着通过包括湿化学蚀刻或反应离子蚀刻(RIE)的回蚀刻工艺可凹入介电层22的顶部表面23。介电层22仅该回蚀刻工艺部分地移除，以降低其厚度。介电层22的该凹入形成位于栅极电极35的宽段34与介电层22的顶部表面23之间的开放空间，以及垂直位于操作晶圆接触31的宽段38与介电层22的顶部表面23之间的开放空间。位于栅极电极35的宽段34下方的该开放空间与栅极电极35的窄段36相邻。介电层22的顶部表面23垂直位于栅极电极35的宽段34与衬底10的顶部表面11之间。
通过沉积例如氮化硅(Si3N4)的共形层并用非等向性蚀刻工艺(例如RIE蚀刻)自水平表面优先移除该共形层的介电材料并停止于介电层22的材料上来形成间隙壁(spacer)52、54。间隙壁52形成于栅极电极35的宽段34的侧边并垂直延伸至介电层22的顶部表面。至少部分由于在形成间隙壁52之前凹入介电层22，在垂直位于栅极电极35的宽段34与介电层22的该顶部表面之间的该开放空间中形成气隙间隙壁56。栅极电极35的窄段36与间隙壁52为气隙间隙壁提供横向边界。类似地，通过在宽段38的侧壁添加间隙壁54，形成与操作晶圆接触31的宽段38相关的气隙间隙壁58。
请参照图7，其中类似的附图标记表示图6中类似的特征且在下一制造阶段，通过包括湿化学蚀刻或RIE的蚀刻工艺可自间隙壁52、54的足印(footprint)外部的区域移除介电层22。通过反向掺杂本体区15，在栅极电极35的宽段34及相邻间隙壁52的投影足印外部的装置层12中形成源区60及漏区62。通过向装置层12的该半导体材料中注入合适的掺杂物例如用于n型导电性的第V族掺杂物如砷(As)或磷(P)，可以自对准方式形成源区60及漏区62。该自对准起因于由栅极电极35的宽段34及相邻间隙壁52提供的掩蔽。源区60与漏区62通过位于栅极电极35下方的本体区15中的沟道区隔开。构成源区60及漏区62的半导体材料经掺杂以具有与本体区15中所包含的半导体材料的导电类型相反的导电类型。当形成源区60及漏区62时，也可掺杂栅极电极35及操作晶圆接触31的相应宽段34、38。
在经选择既不穿过栅极电极35的宽段34也不穿过栅极电极35的窄段36但停止于装置层12的本体区15中的注入条件(例如，动能)下通过注入在装置层12中形成源区60及漏区62。用以形成源区60及漏区62的该注入的离子动能可低于用以形成掺杂区48的该注入的离子动能，并且也可低于用以形成掺杂区46的该注入的离子动能。
请参照图8，其中类似的附图标记表示图7中类似的特征且在下一制造阶段，接着执行硅化、中间工艺(middle-of-line；MOL)工艺，以及后端工艺(back-end-of-line；BEOL)工艺。尤其，在源区60、漏区62以及栅极电极35的宽段34上的部分中形成硅化物层64。类似地，在操作晶圆接触31的宽段38上形成一段硅化物层64。硅化物层64可通过硅化工艺(也就是，自对准硅化)形成，其包括一个或多个退火步骤，以使硅化物形成金属(例如钛(Ti)、钴(Co)或镍(Ni))的沉积层与装置层12、该栅极电极的宽段34，以及该操作晶圆接触的宽段38的半导体材料反应，从而在其相应顶部表面形成硅化物相(silicide phase)。在该代表性实施例中，该栅极电极的宽段34沿其厚度被部分硅化，以形成例如硅化多晶硅/多晶硅堆叠。
在一个替代实施例中，可完全硅化栅极电极35的宽段34，以沿宽段34的整个高度形成硅化多晶硅，其与栅极电极35的窄段36堆叠。该完全硅化宽段34改进栅极电阻(Rgate)而不降低增益，且可将该装置的噪声系数与该装置增益解耦。窄段36可由半导体材料(例如，硅)组成。在一个替代实施例中，窄段36可沿其高度的一部分被部分硅化，以向宽段34的完全硅化多晶硅添加硅化多晶硅/多晶硅组合。
由于段34、36形成于开口28(该开口沿介电层24的厚度比沿介电层22的厚度具有较大宽度)中的方式，栅极电极35的宽段34的宽度独立于窄段36的宽度。栅极电极35的宽段34的宽度也独立于栅极电极35的段36的总高度或厚度，从而允许优化寄生电阻及电容。宽段34的厚度等于其中形成腔体25的介电层24的厚度。可用同一半导体材料沉积层形成栅极电极35与操作晶圆接触31，从而可降低生产成本。
T形栅极电极35的宽段34与栅极电极35的窄段36自对准，这起因于在开口28中形成这些段34、36，其中，通过相对介电层22对称横向蚀刻来凹入介电层24。栅极电极35的段34、36的自对准可改进各种注入的叠加并通过消除掩膜来降低生产成本。
该T形栅极电极位于栅极介电层32、源区60、漏区62及本体区15中的沟道区上方，并通过在有形的、多宽度空间中沉积其组成半导体材料而不使用蚀刻工艺来形成。T形栅极电极35与栅极介电层32自对准，因为在开口28的底部形成栅极介电层32以及后续在开口28中形成栅极电极35的段34、36。通过由该栅极电极掩蔽本体区15，源区60及漏区62相对T形栅极电极35自对准，因此，位于本体区15中的该沟道区同样与栅极电极35自对准。
与栅极电极35的窄段36的侧壁相邻的气隙间隙壁56可用以降低电容并且可进一步改进噪声系数。气隙间隙壁56可改进截止频率(fT)，以至少部分补偿栅极电极35的宽段34的引入。
请参照图9，其中类似的附图标记表示图8中类似的特征且依据本发明的实施例，栅极电极35的窄段36可包括多种材料。尤其，栅极电极35的窄段36可包括连续沉积的多个层70、72、74。层70及74可由半导体材料(例如，多晶硅)组成，且层72可由金属栅极材料(例如，钨(W)或另一种金属)组成，层72位于层70与层74之间以形成多晶硅/金属/多晶硅堆叠，且其中，宽段34可为多晶硅，其经部分或全部硅化以进一步促进该堆叠。在层72中添加该金属栅极材料可用以进一步降低Rgate及噪声系数。同样，操作晶圆接触31的窄段40可由相同的一组层70、72、74形成。
如上所述的方法用于集成电路芯片的制造中。制造者可以原始晶圆形式(例如作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配所得的集成电路芯片。在后一种情况中，该芯片设于单芯片封装件中(例如塑料承载件，其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件，其具有单面或双面互连或嵌埋互连)。在任何情况下，可将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为中间产品或最终产品的部分。例如，本文中所述的实施例中的该场效应晶体管及/或操作晶圆接触可用于开关、低噪声放大器或逻辑电路中。
本文中引用术语例如“垂直”、“水平”、“横向”等作为示例来建立参考框架，并非限制。术语例如“水平”及“横向”是指与半导体衬底的顶部表面平行的平面中的方向，而不论其实际的三维空间取向。术语例如“垂直”及“正交”是指垂直于该“水平”及“横向”方向的方向。术语例如“上方”及“下方”表示元件或结构相对彼此以及/或者相对该半导体衬底的顶部表面的定位，而不是相对标高。
与另一个元件“连接”或“耦接”的特征可与该另一个元件直接连接或耦接，或者可存在一个或多个中间元件。如果不存在中间元件，则特征可与另一个元件“直接连接”或“直接耦接”。如存在至少一个中间元件，则特征可与另一个元件“非直接连接”或“非直接耦接”。
对本发明的各种实施例所作的说明是出于说明目的，而非意图详尽无遗或限于所揭露的实施例。许多修改及变更对于本领域的普通技术人员将显而易见，而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进，或者使本领域的普通技术人员能够理解本文中所揭露的实施例。

Claims (20)

1.一种方法，包括：
形成第一介电层；
在该第一介电层上形成第二介电层；
形成垂直延伸穿过该第一介电层及该第二介电层的第一开口；
在形成该第一开口以后，通过选择性蚀刻工艺相对该第一介电层横向凹入该第二介电层，以相对垂直延伸穿过该第一介电层的该第一开口的第二部分，加宽垂直延伸穿过该第二介电层的该第一开口的第一部分；以及
在横向凹入该第二介电层以后，形成包括位于该第一开口的该第一部分中的宽段及位于该第一开口的该第二部分中的窄段的栅极电极。
2.如权利要求1所述的方法，还包括：
在形成该栅极电极之前，在通过该第一介电层中的该第一开口的该第一部分所暴露的衬底的区域上形成栅极介电层，
其中，该栅极电极的该窄段与该栅极介电层接触。
3.如权利要求2所述的方法，其中，于形成时，该栅极电极的该窄段与该栅极介电层通过该第一开口自对准，以及，于形成时，该栅极电极的该宽段与该栅极电极的该窄段自对准。
4.如权利要求1所述的方法，还包括：
硅化该栅极电极的该宽段。
5.如权利要求4所述的方法，其中，完全硅化该栅极电极的该宽段，且还包括：
硅化与该栅极电极的该宽段相邻的该栅极电极的该窄段的一部分。
6.如权利要求4所述的方法，其中，该栅极电极的该窄段包括多个层，且该多个层的至少其中之一由金属组成。
7.如权利要求1所述的方法，其中，该第一介电层形成于绝缘体上硅衬底的装置层上，且还包括：
形成垂直延伸穿过该第一介电层及该第二介电层的第二开口；
使该第二开口延伸穿过该装置层及该绝缘体上硅衬底的埋置氧化物层至该绝缘体上硅衬底的操作晶圆；以及
在该第二开口中形成至该操作晶圆的接触。
8.如权利要求7所述的方法，其中，该第一开口与该第二开口同时形成于该第一介电层及该第二介电层中。
9.如权利要求7所述的方法，其中，该接触与该栅极电极由半导体材料层同时形成，且还包括：
在使该第二开口延伸穿过该装置层及该埋置氧化物层至该操作晶圆以后，沉积该半导体材料层，从而同时填充该第一开口以形成该栅极电极及该第二开口以形成该接触。
10.如权利要求7所述的方法，还包括：
在形成该第二开口以后，通过该选择性蚀刻工艺相对该第一介电层横向凹入该第二介电层，以相对垂直延伸穿过该第一介电层的该第二开口的第二部分，加宽垂直延伸穿过该第二介电层的该第二开口的第一部分，
其中，该接触包括位于该第二开口的该第一部分中的宽段及位于该第二的该第二部分中的窄段。
11.如权利要求1所述的方法，还包括：
自该第一介电层移除该第二介电层；以及
在移除该第二介电层以后，相对该栅极电极的该宽段凹入该第一介电层的顶部表面，
其中，该栅极电极的该宽段与该第一介电层的该顶部表面垂直隔开。
12.如权利要求11所述的方法，还包括：
在凹入该第一介电层的该顶部表面以后，形成自该栅极电极的该宽度延伸至该第一介电层的该顶部表面的介电间隙壁，
其中，气隙间隙壁被横向限制于该介电间隙壁与该栅极电极的该窄段之间，且该气隙间隙壁被垂直限制于该第一介电层的该顶部表面与该栅极电极的该宽段之间。
13.如权利要求1所述的方法，其中，通过独立于用以相对该第一介电层横向凹入该第二介电层的该蚀刻工艺的蚀刻工艺形成该第一开口。
14.如权利要求1所述的方法，其中，该栅极电极的该窄段位于由半导体材料组成的本体区上，且还包括：
在经选择以使离子穿过该栅极电极的该宽段并穿过该栅极电极的该窄段进入该本体区的注入条件下，通过第一注入在该本体区中形成第一掺杂区；以及
在经选择以使离子穿过该栅极电极的该宽段进入该本体区而不穿过该栅极电极的该窄段进入该本体区的注入条件下，通过第二注入在该本体区中形成第二掺杂区。
15.如权利要求1所述的方法，还包括：
在形成该第一开口之前，在该第二介电层的顶部表面上形成第三介电层，
其中，当横向凹入该第二介电层时，在该第一介电层与该第二介电层之间形成腔体，该栅极电极的该窄段形成于该第一开口中，且该栅极电极的该宽段位于该第一开口中及该腔体中。
16.一种利用衬底所形成的结构，该结构包括：
位于该衬底上的介电层，该介电层包括延伸至该衬底的顶部表面的第一开口；
栅极介电层，位于该第一开口内部及该衬底的该顶部表面上；以及
包括宽段及窄段的栅极电极，该窄段垂直位于该宽段与该栅极介电层之间，且该窄段位于该介电层中的该第一开口内部。
17.如权利要求16所述的结构，其中，该介电层形成于绝缘体上硅衬底的装置层上，该介电层包括延伸至该衬底的该顶部表面的第二开口，且还包括：
接触，延伸穿过该介电层中的该第二开口、该装置层，以及该绝缘体上硅衬底的埋置氧化物层至该绝缘体上硅衬底的操作晶圆，该接触包括宽段及窄段，该窄段垂直位于该宽段与该栅极介电层该操作晶圆之间，且该窄段部分地位于该介电层中的该第一开口内部。
18.如权利要求16所述的结构，其中，该介电层包括位于该栅极电极的该宽段与该衬底的该顶部表面之间的顶部表面。
19.如权利要求18所述的结构，还包括：
介电间隙壁，自该栅极电极的该宽段延伸至该介电层的该顶部表面；以及
气隙间隙壁，被横向限制于该介电间隙壁与该栅极电极的该窄段之间，该气隙间隙壁被垂直限制于该介电层的该顶部表面与该栅极电极的该宽段之间。
20.如权利要求16所述的结构，其中，该栅极电极的该宽段具有厚度，且该栅极电极的该宽段沿该厚度由硅化物组成。
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