TW201901754A - 具有ｔ型閘極電極的場效電晶體 - Google Patents

具有ｔ型閘極電極的場效電晶體 Download PDF

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TW201901754A
TW201901754A TW107101408A TW107101408A TW201901754A TW 201901754 A TW201901754 A TW 201901754A TW 107101408 A TW107101408 A TW 107101408A TW 107101408 A TW107101408 A TW 107101408A TW 201901754 A TW201901754 A TW 201901754A
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dielectric layer
gate electrode
opening
segment
layer
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TW107101408A
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TWI694498B (zh
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史蒂芬Ｍ 宣克
亞文Ｊ 喬瑟夫
約翰Ｊ 艾利斯蒙納翰
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明揭露場效電晶體的裝置結構以及形成場效電晶體的裝置結構的方法。形成第一介電層，以及在該第一介電層上形成第二介電層。形成垂直延伸穿過該第一及第二介電層的開口。在形成該第一開口以後，通過選擇性蝕刻製程相對該第一介電層橫向凹入該第二介電層，以相對垂直延伸穿過該第一介電層的該開口的一部分，加寬垂直延伸穿過該第二介電層的該開口的一部分。在橫向凹入該第二介電層以後，形成閘極電極，該閘極電極包括位於垂直延伸穿過該第一介電層的該開口的該部分中的窄段以及位於垂直延伸穿過該第二介電層的該開口的該部分中的寬段。

Description

具有T形閘極電極的場效電晶體
本發明關於半導體裝置製造及積體電路，尤其關於場效電晶體的裝置結構以及形成場效電晶體的裝置結構的方法。
互補金屬氧化物半導體(complementary-metal-oxide-semiconductor；CMOS)製程(process)可用以構建p型場效電晶體(p-type field-effect transistor；pFET)與n型場效電晶體(n-type field-effect transistor；nFET)的組合，該些電晶體經耦接以實施邏輯閘(logic gate)及其它類型的積體電路，例如開關。場效電晶體通常包括本體區、定義於該本體區中的源極及汲極，以及與該本體區中的通道關聯的閘極電極。當向該閘極電極施加超過指定臨界值電壓的控制電壓時，在該源極與汲極之間的該通道中的反型或耗盡層中發生載子流動(carrier flow)，從而產生裝置輸出電流。
絕緣體上矽(silicon-on-insulator；SOI)基板在CMOS製程中可能是有利的。與利用塊體矽晶圓構建 的場效電晶體相比，絕緣體上矽基板允許場效電晶體以顯著較高的速度操作，改進電性隔離並降低電性損失。依據該SOI基板的裝置層的厚度，場效電晶體可以部分耗盡模式操作，其中，當向閘極電極施加典型的控制電壓時，位於本體區內的通道中的耗盡層不完全延伸至埋置氧化物層。
需要改進的場效電晶體的裝置結構以及形成場效電晶體的裝置結構的方法。
在本發明的一個實施例中，一種方法包括形成第一介電層以及位於該第一介電層上的第二介電層。形成垂直延伸穿過該第一及第二介電層的開口。在形成該開口以後，通過選擇性蝕刻製程相對該開口內部的該第一介電層橫向凹入該第二介電層，以相對垂直延伸穿過該第一介電層的該開口的一部分，加寬垂直延伸穿過該第二介電層的該開口的一部分。在橫向凹入該第二介電層以後，形成閘極電極，該閘極電極包括位於垂直延伸穿過該第一介電層的該開口的該部分中的窄段(narrow section)及位於垂直延伸穿過該第二介電層的該開口的該部分中的寬段(wide section)。
在本發明的一個實施例中，一種結構包括：包括延伸至基板的頂部表面的開口的介電層，以及位於該開口內部及該基板的該頂部表面上的閘極介電質。該結構還包括閘極電極，該閘極電極包括寬段及窄段，該窄段垂 直位於該寬段與該閘極介電層之間，且該窄段位於該介電層中的該第一開口內部。
10‧‧‧基板
11、23‧‧‧頂部表面
12‧‧‧裝置層
14‧‧‧埋置氧化物(BOX)層
15、17‧‧‧本體區
16‧‧‧處理晶圓
18‧‧‧溝槽隔離區
20‧‧‧屏蔽氧化物層
22、24、26‧‧‧介電層
25‧‧‧腔體
28、30‧‧‧開口
31‧‧‧接觸或處理晶圓接觸
32‧‧‧閘極介電層
34、38‧‧‧寬段
35‧‧‧閘極電極或T形閘極電極
36、40‧‧‧窄段
42、44、46、48‧‧‧摻雜區
52、54‧‧‧間隙壁
56、58‧‧‧氣隙間隙壁
60‧‧‧源區
62‧‧‧汲區
64‧‧‧矽化物層
70、72、74‧‧‧層
w1、w2‧‧‧寬度
包含於並構成本說明書的一部分的附圖說明本發明的各種實施例，並與上面所作的本發明的概括說明以及下面所作的實施例的詳細說明一起用以解釋本發明的實施例。
第1圖至第8圖顯示依據本發明的實施例處於製程方法的連續階段中的裝置結構的剖視圖。
第9圖顯示依據本發明的實施例的裝置結構的剖視圖。
請參照第1圖並依據本發明的實施例，以絕緣體上矽(SOI)基板為代表形式的基板10包括裝置層12，採用由矽的氧化物(例如，SiO2)組成的埋置氧化物(buried oxide；BOX)層14的形式的埋置介電層，以及處理晶圓(handle wafer)16。裝置層12及BOX層14終止於處理晶圓16的邊緣。裝置層12通過中間的BOX層14與處理晶圓16隔開且可遠薄於處理晶圓16。裝置層12通過BOX層14與處理晶圓16電性隔離。裝置層12與處理晶圓16可由單晶半導體材料例如矽組成。BOX層14具有沿界面與裝置層12直接接觸的頂部表面以及沿另一個界面與處理晶圓16直接接觸的底部表面，且這些表面通過BOX層14的厚度隔開。處理晶圓16可經輕摻雜以具有例如p型 導電性。
溝槽隔離區18形成於裝置層12中，並將裝置層12劃分為本體區15、17。通過沉積介電材料來填充溝槽並利用例如化學機械拋光(chemical-mechanical polishing；CMP)平坦化該介電材料可形成溝槽隔離區18。構成溝槽隔離區18的該介電材料可為電性絕緣體，例如通過化學氣相沉積(chemical vapor deposition；CVD)沉積的矽的氧化物(例如，二氧化矽(SiO2))。
在基板10的頂部表面11(包括裝置層12及溝槽隔離區18的頂部表面)上形成屏蔽氧化物層(screen oxide layer)20。在裝置層12中所定義的本體區15中形成阱(well)期間，屏蔽氧化物層20保護位於基板10的頂部表面11的裝置層12。在一個實施例中，該阱可為p阱，通過在給定的注入條件下注入選自週期表的第III族的p型摻雜物(例如，硼)離子使裝置層12的組成半導體材料具有p型導電性來形成該P阱。
請參照第2圖，其中類似的附圖標記表示第1圖中類似的特徵且在下一製造階段，在屏蔽氧化物層20上順序形成介電層22、24、26作為堆疊。以屏蔽氧化物層20為中間層，介電層22形成於基板10的頂部表面11上，介電層24形成於介電層22的頂部表面上，以及介電層26形成於介電層24的頂部表面上。介電層22、26可由相同的電性絕緣體組成，例如通過CVD沉積的二氧化矽(SiO2)。介電層24可由具有與介電層22及介電層26不 同的蝕刻選擇性的電性絕緣體組成。在介電層22、26由二氧化矽組成的一個實施例中，介電層24可由通過CVD所沉積的氮化矽(Si3N4)組成。
通過使用光刻及一個或多個蝕刻製程圖案化介電層22、24、26及屏蔽氧化物層20，以定義開口28、30。開口28與裝置層12的本體區15對齊，且開口30與裝置層12的本體區17對齊。在一個實施例中，可同時形成開口28、30。延伸穿過介電層26的開口28、30的一部分可沿朝向介電層24的方向向內收窄並與延伸穿過層22、24的開口的部分相比加寬。通過調節用以蝕刻穿過介電層26的該蝕刻製程的橫向及垂直分量可設置該收窄。
請參照第3圖，其中類似的附圖標記表示第2圖中類似的特徵且在下一製造階段，通過停止於處理晶圓16的材料上的一個或多個蝕刻製程使開口30沿深度垂直延伸穿過裝置層12並穿過BOX層14至處理晶圓16。可施加蝕刻遮罩(未顯示)，當沿深度延伸開口30時，該蝕刻遮罩覆蓋開口28。
接著，通過蝕刻製程相對介電層22及介電層24橫向凹入介電層24，以形成垂直位於介電層22上方並垂直位於介電層26下方的腔體25。在腔體25的位置，與保留初始寬度的延伸穿過介電層22的開口28的部分相比，延伸穿過介電層24的開口28的一部分通過形成腔體25而被加寬。沿介電層24的厚度，腔體25相對開口28的垂直中心線對稱地設置。若介電層22、26由二氧化矽組 成且介電層24由氮化矽組成，則可選擇用於相對二氧化矽選擇性地等向性蝕刻氮化矽的濕式或乾式蝕刻製程的蝕刻化學。例如，合適的蝕刻化學可為用以相對二氧化矽選擇性濕化學蝕刻氮化矽的熱磷酸(hot phosphoric acid)。
橫向凹入介電層24的該蝕刻製程也相對裝置層12及BOX層14的材料選擇性移除介電層24的材料。本文中所使用的關於材料移除製程(例如，蝕刻)的術語“選擇性”表示目標材料的材料移除速率(也就是，蝕刻速率)高於暴露於該材料移除製程的至少另一種材料的材料移除速率(也就是，蝕刻速率)。在通過開口28暴露的裝置層12以及毗鄰開口30的側壁的裝置層12的半導體材料上可形成可選的保護層(未顯示)。
請參照第4圖，其中類似的附圖標記表示第3圖中類似的特徵且在下一製造階段，在開口28內部的裝置層12的頂部表面上形成閘極介電層32。閘極介電層32可由介電材料例如二氧化矽(SiO2)構成，其可通過氧化裝置層12的頂部表面生長。薄介電材料層可同時形成於位於開口30的底部的處理晶圓16上，且可在掩蔽開口28的情況下通過蝕刻移除。
用半導體材料填充開口28以定義T形閘極電極35，以及用半導體材料填充開口30以定義至處理晶圓16的接觸(contact)31。在一個實施例中，用同一半導體材料沉積層的部分同時填充開口28與開口30。在一個實施例中，該半導體材料可包括多晶矽半導體材料例如未摻雜 多晶矽(也就是，多晶矽)、或者非晶半導體材料例如非晶矽，其通過CVD沉積並通過例如CMP相對介電層26的頂部表面平坦化。位於介電層26中的開口28、30的該收窄部分可提升沿開口28、30的深度填充的能力。相對介電層26凹入所沉積的半導體材料，並在凹入以後，通過濕化學蝕刻製程(例如，緩衝氫氟酸)可剝離介電層26。
填充開口28以形成閘極電極35的該半導體材料順應開口28的組合形狀及幾何。尤其，與沿介電層22的厚度位於開口28中的該半導體材料的窄段36相比，沿介電層24的厚度位於開口28中的該半導體材料的寬段34較寬。窄段36垂直位於寬段34與閘極介電層32之間，且寬段34的增加寬度起因於先前相對介電層22及26橫向凹入介電層24而形成腔體25。
該半導體材料的段34、36共同形成場效電晶體的T形閘極電極35。寬段34的寬度w1大於窄段36的寬度w2。在一個實施例中，閘極電極35的寬段34可為20奈米至100奈米厚，且閘極電極35的寬段34的寬度可為0.15微米至0.09微米。在一個實施例中，閘極電極35的窄段36可為20奈米至100奈米厚，且閘極電極35的窄段36的寬度可小於0.09微米。
位於開口30內部的該半導體材料順應開口30的組合形狀及幾何，並定義可在裝置層12的頂部表面訪問的至處理晶圓16的接觸31。尤其，接觸31包括由該組成半導體材料構成的寬段38以及垂直位於寬段38與處 理晶圓16之間的由該組成半導體材料構成的窄段40。寬段38位於沿介電層24的厚度位於開口30中，且窄段40沿介電層22、裝置層12及BOX層14的厚度位於開口30中。寬段38的增加寬度起因於先前相對介電層22及26橫向凹入介電層24。
請參照第5圖，其中類似的附圖標記表示第4圖中類似的特徵且在下一製造階段，通過蝕刻製程移除介電層24，例如用熱磷酸以相對二氧化矽及多晶矽選擇性濕化學蝕刻氮化矽。在該閘極電極的寬段34中、該處理晶圓接觸的寬段38中，以及鄰近閘極電極35的窄段36的淺深度處的裝置層12中通過離子注入分別形成摻雜區42、44、46。在一個實施例中，該注入可以有效使該半導體材料具有n型導電性的濃度提供選自週期表的第V族的n型摻雜物離子(例如，砷(As)或磷(P))。
在該閘極電極的窄段36下方的淺深度處的裝置層12中通過離子注入形成摻雜區48。在一個實施例中，該注入可以有效使裝置層12的組成半導體材料具有p型導電性的濃度提供選自週期表的第III族的p型摻雜物離子(例如，硼)。
在各種情況下，該離子可自合適的源氣體生成並用離子注入工具通過所選注入條件(例如，離子種類、劑量、動能、傾斜角度)注入。與閘極電極35的窄段36相鄰的裝置層12中的摻雜區46可代表後續形成的源/汲區的延伸區。位於閘極電極35的窄段36下方的裝置層12 中的摻雜區48可代表與後續形成的源/汲區關聯的環狀區(halo)。該注入條件可經選擇以在裝置層12中的所需位置設置摻雜區46及摻雜區48。與摻雜區48相比，摻雜區46位於裝置層12中的淺深度。
運用閘極電極35的寬段34及閘極電極35的窄段36的雙厚度的雙重穿閘極注入用以自對準延伸區及環狀區注入至通道區。各次注入的能量可經調整以被閘極電極35的寬段34及閘極電極35的窄段36的其中一者或兩者阻擋。在經選擇以穿過閘極電極35的寬段34及閘極電極35的窄段36並停止於裝置層12的本體區15中的注入條件(例如，動能)下通過注入形成摻雜區48。在經選擇以穿過閘極電極35的寬段34而不穿過閘極電極35的窄段36並停止於裝置層12的本體區15中的注入條件(例如，動能)下通過注入形成於裝置層12中的摻雜區46。用以形成摻雜區48的該注入的離子動能可高於用以形成摻雜區46的該注入的離子動能。摻雜區48被埋置於裝置層12的本體區15的頂部下方的上段下方，以減小電場，從而降低漏電流並改進低雜訊(noise)放大器應用的增益。
請參照第6圖，其中類似的附圖標記表示第1圖中類似的特徵且在下一製造階段，在所述注入之後接著通過包括濕化學蝕刻或反應離子蝕刻(RIE)的回蝕刻製程可凹入介電層22的頂部表面23。介電層22僅該回蝕刻製程部分地移除，以降低其厚度。介電層22的該凹入形成位於閘極電極35的寬段34與介電層22的頂部表面23 之間的開放空間，以及垂直位於處理晶圓接觸31的寬段38與介電層22的頂部表面23之間的開放空間。位於閘極電極35的寬段34下方的該開放空間與閘極電極35的窄段36相鄰。介電層22的頂部表面23垂直位於閘極電極35的寬段34與基板10的頂部表面11之間。
通過沉積例如氮化矽(Si3N4)的共形層並用非等向性蝕刻製程(例如RIE蝕刻)自水平表面優先移除該共形層的介電材料並停止於介電層22的材料上來形成間隙壁(spacer)52、54。間隙壁52形成於閘極電極35的寬段34的側邊並垂直延伸至介電層22的頂部表面。至少部分由於在形成間隙壁52之前凹入介電層22，在垂直位於閘極電極35的寬段34與介電層22的該頂部表面之間的該開放空間中形成氣隙間隙壁56。閘極電極35的窄段36與間隙壁52為氣隙間隙壁提供橫向邊界。類似地，通過在寬段38的側壁添加間隙壁54，形成與處理晶圓接觸31的寬段38相關的氣隙間隙壁58。
請參照第7圖，其中類似的附圖標記表示第6圖中類似的特徵且在下一製造階段，通過包括濕化學蝕刻或RIE的蝕刻製程可自間隙壁52、54的足印(footprint)外部的區域移除介電層22。通過反向摻雜本體區15，在閘極電極35的寬段34及相鄰間隙壁52的投影足印外部的裝置層12中形成源區60及汲區62。通過向裝置層12的該半導體材料中注入合適的摻雜物例如用於n型導電性的第V族摻雜物如砷(As)或磷(P)，可以自對準方式形成源 區60及汲區62。該自對準起因於由閘極電極35的寬段34及相鄰間隙壁52提供的掩蔽。源區60與汲區62通過位於閘極電極35下方的本體區15中的通道區隔開。構成源區60及汲區62的半導體材料經摻雜以具有與本體區15中所包含的半導體材料的導電類型相反的導電類型。當形成源區60及汲區62時，也可摻雜閘極電極35及處理晶圓接觸31的相應寬段34、38。
在經選擇既不穿過閘極電極35的寬段34也不穿過閘極電極35的窄段36但停止於裝置層12的本體區15中的注入條件(例如，動能)下通過注入在裝置層12中形成源區60及汲區62。用以形成源區60及汲區62的該注入的離子動能可低於用以形成摻雜區48的該注入的離子動能，並且也可低於用以形成摻雜區46的該注入的離子動能。
請參照第8圖，其中類似的附圖標記表示第7圖中類似的特徵且在下一製造階段，接著執行矽化、中間製程(middle-of-line；MOL)製程，以及後端製程(back-end-of-line；BEOL)製程。尤其，在源區60、汲區62以及閘極電極35的寬段34上的部分中形成矽化物層64。類似地，在處理晶圓接觸31的寬段38上形成一段矽化物層64。矽化物層64可通過矽化製程(也就是，自對準矽化)形成，其包括一個或多個退火步驟，以使矽化物形成金屬(例如鈦(Ti)、鈷(Co)或鎳(Ni))的沉積層與裝置層12、該閘極電極的寬段34，以及該處理晶圓接觸 的寬段38的半導體材料反應，從而在其相應頂部表面形成矽化物相(silicide phase)。在該代表性實施例中，該閘極電極的寬段34沿其厚度被部分矽化，以形成例如矽化多晶矽/多晶矽堆疊。
在一個替代實施例中，可完全矽化閘極電極35的寬段34，以沿寬段34的整個高度形成矽化多晶矽，其與閘極電極35的窄段36堆疊。該完全矽化寬段34改進閘極電阻(Rgate)而不降低增益，且可將該裝置的雜訊係數與該裝置增益解耦。窄段36可由半導體材料(例如，矽)組成。在一個替代實施例中，窄段36可沿其高度的一部分被部分矽化，以向寬段34的完全矽化多晶矽添加矽化多晶矽/多晶矽組合。
由於段34、36形成於開口28(該開口沿介電層24的厚度比沿介電層22的厚度具有較大寬度)中的方式，閘極電極35的寬段34的寬度獨立於窄段36的寬度。閘極電極35的寬段34的寬度也獨立於閘極電極35的段36的總高度或厚度，從而允許優化寄生電阻及電容。寬段34的厚度等於其中形成腔體25的介電層24的厚度。可用同一半導體材料沉積層形成閘極電極35與處理晶圓接觸31，從而可降低生產成本。
T形閘極電極35的寬段34與閘極電極35的窄段36自對準，這起因於在開口28中形成這些段34、36，其中，通過相對介電層22對稱橫向蝕刻來凹入介電層24。閘極電極35的段34、36的自對準可改進各種注入的疊加 並通過消除遮罩來降低生產成本。
該T形閘極電極位於閘極介電層32、源區60、汲區62及本體區15中的通道區上方，並通過在有形的、多寬度空間中沉積其組成半導體材料而不使用蝕刻製程來形成。T形閘極電極35與閘極介電層32自對準，因為在開口28的底部形成閘極介電層32以及後續在開口28中形成閘極電極35的段34、36。通過由該閘極電極掩蔽本體區15，源區60及汲區62相對T形閘極電極35自對準，因此，位於本體區15中的該通道區同樣與閘極電極35自對準。
與閘極電極35的窄段36的側壁相鄰的氣隙間隙壁56可用以降低電容並且可進一步改進雜訊係數。氣隙間隙壁56可改進截止頻率(fT)，以至少部分補償閘極電極35的寬段34的引入。
請參照第9圖，其中類似的附圖標記表示第8圖中類似的特徵且依據本發明的實施例，閘極電極35的窄段36可包括多種材料。尤其，閘極電極35的窄段36可包括連續沉積的多個層70、72、74。層70及74可由半導體材料(例如，多晶矽)組成，且層72可由金屬閘極材料(例如，鎢(W)或另一種金屬)組成，層72位於層70與層74之間以形成多晶矽/金屬/多晶矽堆疊，且其中，寬段34可為多晶矽，其經部分或全部矽化以進一步促進該堆疊。在層72中添加該金屬閘極材料可用以進一步降低Rgate及雜訊係數。同樣，處理晶圓接觸31的窄段40可 由相同的一組層70、72、74形成。
如上所述的方法用於積體電路晶片的製造中。製造者可以原始晶圓形式(例如作為具有多個未封裝晶片的單個晶圓)、作為裸晶片，或者以封裝形式分配所得的積體電路晶片。在後一種情況中，該晶片設於單晶片封裝件中(例如塑料承載件，其具有附著至母板或其它更高層次承載件的引腳)或者多晶片封裝件中(例如陶瓷承載件，其具有單面或雙面互連或嵌埋互連)。在任何情況下，可將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置積體，作為中間產品或最終產品的部分。例如，本文中所述的實施例中的該場效電晶體及/或處理晶圓接觸可用於開關、低雜訊放大器或邏輯電路中。
本文中引用術語例如“垂直”、“水平”、“橫向”等作為示例來建立參考框架，並非限制。術語例如“水平”及“橫向”是指與半導體基板的頂部表面平行的平面中的方向，而不論其實際的三維空間取向。術語例如“垂直”及“正交”是指垂直於該“水平”及“橫向”方向的方向。術語例如“上方”及“下方”表示元件或結構相對彼此以及/或者相對該半導體基板的頂部表面的定位，而不是相對標高。
與另一個元件“連接”或“耦接”的特徵可與該另一個元件直接連接或耦接，或者可存在一個或多個中間元件。如果不存在中間元件，則特徵可與另一個元件“直接連接”或“直接耦接”。如存在至少一個中間元件，則特徵可與另一個元件“非直接連接”或“非直接耦接”。
對本發明的各種實施例所作的說明是出於說明目的，而非意圖詳盡無遺或限於所揭露的實施例。許多修改及變更對於本領域的普通技術人員將顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使本領域的普通技術人員能夠理解本文中所揭露的實施例。

Claims (20)

  1. 一種方法，包括：形成第一介電層；在該第一介電層上形成第二介電層；形成垂直延伸穿過該第一介電層及該第二介電層的第一開口；在形成該第一開口以後，通過選擇性蝕刻製程相對該第一介電層橫向凹入該第二介電層，以相對垂直延伸穿過該第一介電層的該第一開口的第二部分，加寬垂直延伸穿過該第二介電層的該第一開口的第一部分；以及在橫向凹入該第二介電層以後，形成包括位於該第一開口的該第一部分中的寬段及位於該第一開口的該第二部分中的窄段的閘極電極。
  2. 如申請專利範圍第1項所述的方法，更包括：在形成該閘極電極之前，在通過該第一介電層中的該第一開口的該第一部分所暴露的基板的區域上形成閘極介電層，其中，該閘極電極的該窄段與該閘極介電層接觸。
  3. 如申請專利範圍第2項所述的方法，其中，於形成時，該閘極電極的該窄段與該閘極介電層通過該第一開口自對準，以及，於形成時，該閘極電極的該寬段與該閘極電極的該窄段自對準。
  4. 如申請專利範圍第1項所述的方法，更包括： 矽化該閘極電極的該寬段。
  5. 如申請專利範圍第4項所述的方法，其中，完全矽化該閘極電極的該寬段，且更包括：矽化與該閘極電極的該寬段相鄰的該閘極電極的該窄段的一部分。
  6. 如申請專利範圍第4項所述的方法，其中，該閘極電極的該窄段包括多個層，且該多個層的至少其中一層由金屬組成。
  7. 如申請專利範圍第1項所述的方法，其中，該第一介電層形成於絕緣體上矽基板的裝置層上，且更包括：形成垂直延伸穿過該第一介電層及該第二介電層的第二開口；使該第二開口延伸穿過該裝置層及該絕緣體上矽基板的埋置氧化物層至該絕緣體上矽基板的處理晶圓；以及在該第二開口中形成至該處理晶圓的接觸。
  8. 如申請專利範圍第7項所述的方法，其中，該第一開口與該第二開口同時形成於該第一介電層及該第二介電層中。
  9. 如申請專利範圍第7項所述的方法，其中，該接觸與該閘極電極由半導體材料層同時形成，且更包括：在使該第二開口延伸穿過該裝置層及該埋置氧化物層至該處理晶圓以後，沉積該半導體材料層，從而同時填充該第一開口以形成該閘極電極及該第二開口以 形成該接觸。
  10. 如申請專利範圍第7項所述的方法，更包括：在形成該第二開口以後，通過該選擇性蝕刻製程相對該第一介電層橫向凹入該第二介電層，以相對垂直延伸穿過該第一介電層的該第二開口的第二部分，加寬垂直延伸穿過該第二介電層的該第二開口的第一部分，其中，該接觸包括位於該第二開口的該第一部分中的寬段及位於該第二的該第二部分中的窄段。
  11. 如申請專利範圍第1項所述的方法，更包括：自該第一介電層移除該第二介電層；以及在移除該第二介電層以後，相對該閘極電極的該寬段凹入該第一介電層的頂部表面，其中，該閘極電極的該寬段與該第一介電層的該頂部表面垂直隔開。
  12. 如申請專利範圍第11項所述的方法，更包括：在凹入該第一介電層的該頂部表面以後，形成自該閘極電極的該寬度延伸至該第一介電層的該頂部表面的介電間隙壁，其中，氣隙間隙壁被橫向限制於該介電間隙壁與該閘極電極的該窄段之間，且該氣隙間隙壁被垂直限制於該第一介電層的該頂部表面與該閘極電極的該寬段之間。
  13. 如申請專利範圍第1項所述的方法，其中，通過獨立於用以相對該第一介電層橫向凹入該第二介電層的該蝕 刻製程的蝕刻製程形成該第一開口。
  14. 如申請專利範圍第1項所述的方法，其中，該閘極電極的該窄段位於由半導體材料組成的本體區上，且更包括：在經選擇以使離子穿過該閘極電極的該寬段並穿過該閘極電極的該窄段進入該本體區的注入條件下，通過第一注入在該本體區中形成第一摻雜區；以及在經選擇以使離子穿過該閘極電極的該寬段進入該本體區而不穿過該閘極電極的該窄段進入該本體區的注入條件下，通過第二注入在該本體區中形成第二摻雜區。
  15. 如申請專利範圍第1項所述的方法，更包括：在形成該第一開口之前，在該第二介電層的頂部表面上形成第三介電層，其中，當橫向凹入該第二介電層時，在該第一介電層與該第二介電層之間形成腔體，該閘極電極的該窄段形成於該第一開口中，且該閘極電極的該寬段位於該第一開口中及該腔體中。
  16. 一種利用基板所形成的結構，該結構包括：位於該基板上的介電層，該介電層包括延伸至該基板的頂部表面的第一開口；閘極介電層，位於該第一開口內部及該基板的該頂部表面上；以及包括寬段及窄段的閘極電極，該窄段垂直位於該 寬段與該閘極介電層之間，且該窄段位於該介電層中的該第一開口內部。
  17. 如申請專利範圍第16項所述的結構，其中，該介電層形成於絕緣體上矽基板的裝置層上，該介電層包括延伸至該基板的該頂部表面的第二開口，且更包括：接觸，延伸穿過該介電層中的該第二開口、該裝置層，以及該絕緣體上矽基板的埋置氧化物層至該絕緣體上矽基板的處理晶圓，該接觸包括寬段及窄段，該窄段垂直位於該寬段與該閘極介電層該處理晶圓之間，且該窄段部分地位於該介電層中的該第一開口內部。
  18. 如申請專利範圍第16項所述的結構，其中，該介電層包括位於該閘極電極的該寬段與該基板的該頂部表面之間的頂部表面。
  19. 如申請專利範圍第18項所述的結構，更包括：介電間隙壁，自該閘極電極的該寬段延伸至該介電層的該頂部表面；以及氣隙間隙壁，被橫向限制於該介電間隙壁與該閘極電極的該窄段之間，該氣隙間隙壁被垂直限制於該介電層的該頂部表面與該閘極電極的該寬段之間。
  20. 如申請專利範圍第16項所述的結構，其中，該閘極電極的該寬段具有厚度，且該閘極電極的該寬段沿該厚度由矽化物組成。
TW107101408A 2017-03-14 2018-01-15 具有ｔ形閘極電極的場效電晶體及其形成方法 TWI694498B (zh)

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