CN108568613A - 焊料合金及接合结构体 - Google Patents

焊料合金及接合结构体 Download PDF

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Publication number
CN108568613A
CN108568613A CN201810163713.8A CN201810163713A CN108568613A CN 108568613 A CN108568613 A CN 108568613A CN 201810163713 A CN201810163713 A CN 201810163713A CN 108568613 A CN108568613 A CN 108568613A
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China
Prior art keywords
solder alloy
bonded structure
solder
alloy
comparative example
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CN201810163713.8A
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English (en)
Inventor
北浦秀敏
古泽彰男
日根清裕
酒井树
酒井一树
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Publication of CN108568613A publication Critical patent/CN108568613A/zh
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/26Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262Sn as the principal constituent
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0227Rods, wires
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C13/00Alloys based on tin
    • C22C13/02Alloys based on tin with antimony or bismuth as the next major constituent
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    • BPERFORMING OPERATIONS; TRANSPORTING
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    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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Abstract

一种焊料合金,其中,Sb的含有率为3wt%以上且15wt%以下,Te的含有率为0.01wt%以上且1.5wt%以下,并且,Au的含有率为0.005wt%以上且1wt%以下,余量为Sn。

Description

焊料合金及接合结构体
技术领域
本发明涉及用于电源模块等的焊料合金及使用其的接合结构体。
背景技术
作为现有的焊料合金及使用其的接合结构体,例如日本专利第4147875号中记载了一种钎料、以及将使用该钎料组装而成的半导体装置与基板进行了接合的接合结构体,所述钎料的特征在于,其包含Sb 5质量%以上且20质量%以下、Te 0.01质量%以上且5质量%以下,余量由Sn、任意的添加物和不可避免的杂质组成。
发明内容
本发明的焊料合金中,Sb的含有率为3wt%以上且15wt%以下,Te的含有率为0.01wt%以上且1.5wt%以下,并且,Au的含有率为0.005wt%以上且1wt%以下,余量为Sn。
根据本发明,可提供使焊料接合部的耐裂纹性提高、实现高可靠性的焊料合金及使用其的接合结构体。
附图说明
图1是本发明的一个实施方式的接合结构体的制造方法的说明图。
图2是本发明的一个实施方式的接合结构体的制造方法的说明图。
具体实施方式
在说明实施方式之前,对现有的问题点进行简单说明。
日本专利第4147875号中记载的焊料合金通过在Sn中添加Te、Ag、Cu、Fe、Ni而使接合可靠性提高,但未能实现可耐受1000次循环以上的热循环试验的连接可靠性。因此,对于长时间需要连接可靠性的车载等目的而言,要求实现充分的接合可靠性。
本发明是为了解决上述现有的课题而完成的,其目的在于提供使焊料接合部的耐裂纹性提高、实现高可靠性的焊料合金。
本发明的焊料合金中,Sb的含有率为3wt%以上且15wt%以下,Te的含有率为0.01wt%以上且1.5wt%以下,并且,Au的含有率为0.005wt%以上且1wt%以下,余量为Sn。
在本说明书中,“含有率”是指各元素的重量相对于焊料合金整体的重量的比例,使用wt%(重量百分比)的单位来表示。
在本说明书中,“焊料合金”是指:只要其金属组成在实质上由列举的金属构成,就也可以含有不可避免地混入的微量金属(例如小于0.005wt%)。焊料合金可以具有任意的形态,例如可以单独或者与金属以外的其他成分(例如助焊剂等)一起用于软钎焊。
本发明的焊料合金中,以具有规定含有率的方式添加了Te,因此,因Te向Sn中固溶而发生伸长率的提高。此外,本发明的焊料合金中,以具有规定含有率的方式添加了Te和Au这两者,因此,在高温下,离子半径不同的Au与固溶于Sn的Te复杂地进行置换,并产生位错,从而发生高温中的伸长率的提高。因此,本发明的焊料合金与仅添加了Te的SnSb系焊料相比,具有高温中的更优异的伸长率。由此,能够吸收在热循环时产生的反复应力,从而能够实现接合结构体的高可靠性。
另外,一个实施方式的接合结构体中,半导体元件与电路基板借助包含Sb、Te、Au和Sn的焊料接合层进行了接合,在半导体元件的金属层与焊料接合层的界面处、以及电路基板的镀层与焊料接合层的界面处包含SnNi合金或SnCu合金。
上述实施方式的接合结构体在热循环中的耐裂纹性优异,具有高可靠性。
以下,对于本发明的实施方式的焊料合金,一边使用附图一边进行说明。
<焊料合金105>
焊料合金105是包含Sb、Te、Au且余量为Sn的合金。
焊料合金105中的Sb的含有率为3wt%以上且15wt%以下。通过使焊料合金中的Sb的含有率处于这样的范围,能够改善焊料接合部的热疲劳特性。
焊料合金105中的Te的含有率为0.01wt%以上且1.5wt%以下,Au的含有率为0.005wt%以上且1wt%以下,余量为Sn。在此,焊料合金105中的Au可以通过在包含Sb和Te且余量为Sn的焊料合金的表面实施Au镀覆来提供。在此情况下,在焊料合金105的熔融时,Au熔入至焊料合金105。本发明的焊料合金中,以具有规定含有率的方式添加了Te和Au这两者,因此,在高温中,离子半径不同的Au与固溶于Sn的Te复杂地进行置换,并产生位错,由此,产生高温中的伸长率的提高。因此,本发明的焊料合金与仅添加了Te的SnSb系焊料相比,具有高温中的更优异的伸长率。因此,能够吸收在热循环时产生的反复应力,使耐裂纹性提高,从而能够实现接合结构体的高可靠性。
焊料合金105的尺寸可因所制造的接合结构体而异,例如为10mm见方,也可以使用具有0.05mm以上且0.5mm以下的厚度的焊料合金105。通过使焊料合金105的厚度为0.5mm以下,所形成的焊料接合部的热阻不会变高,能够高效地散逸半导体元件101的热。通过使焊料合金105的厚度为0.05mm以上,能够抑制焊料接合时产生空隙,能够使焊料接合部的热阻提高。
接着,对于本发明的实施方式的接合结构体,一边使用附图一边进行说明。
<半导体元件101>
图1所示的半导体元件101包含:硅芯片102、形成于硅芯片102的下表面的电阻层103、以及形成于电阻层103的下表面的金属层104。从制造容易性出发,硅芯片102优选纵长为10mm、横长为10mm且具有0.2mm的厚度,但并不限定于此,可以有各种尺寸。
半导体元件101的电阻层103是由任意的纯金属或合金形成的层,例如可以使用Ti、Al、Cr、Ni或包含这些金属的合金等,但并不限定于此。通过在电阻层中使用上述金属,能够得到适当的电阻性接合。电阻层103的厚度没有特别限定,可以为例如0.05μm以上且0.5μm以下,可以为例如0.1μm。通过使电阻层103具有这样的厚度,容易确保电阻值和接合可靠性。
半导体元件101的金属层104是由任意的纯金属或合金形成的层,例如可以使用Ni、Cu或包含这些金属的合金等,但并不限定于此。金属层104的厚度没有特别限定,可以为例如0.5μm以上且10μm以下,可以为例如1μm。通过使金属层104具有这样的厚度,能够与焊料合金牢固地接合。
<电路基板106>
电路基板106包含:引线框107和形成于引线框107的表面的镀层108。
电路基板106的引线框107的材料可以使用金属或陶瓷等导热性良好的材料。作为引线框107的材料,例如可以使用铜、铝、氧化铝、氮化铝、氮化硅等,但不限定于此。从制造容易性出发,引线框107优选纵长为20mm、横长为20mm且具有1mm的厚度,但并不限定于此,可以有各种尺寸。
电路基板106的镀层108是由任意的纯金属或合金形成的层,例如可以使用Ni、Cu或包含这些金属的合金等,但并不限定于此。镀层的厚度没有特别限定,可以为例如0.5μm以上且10μm以下,可以为例如1μm。通过使镀层具有这样的厚度,能够与焊料合金牢固地接合。
<接合结构体201>
使用本发明的焊料合金制造的接合结构体201在图2中以示意图表示。接合结构体201具有由半导体元件101与电路基板106借助合金层202和焊料接合层203进行接合而得到的结构。
为了制造接合结构体201,如图1所示,在电路基板106的镀层108上载置焊料合金105,进而以焊料合金105与半导体元件101的金属层104接触的方式,在焊料合金105上设置半导体元件101。接下来,一边使温度每分钟升高10℃,一边进行从室温至300℃为止的加热,在300℃保持1分钟后,一边使温度每分钟降低10℃,一边进行从300℃至室温为止的冷却,由此,在焊料合金105与金属层104之间、以及焊料合金105与镀层108之间形成合金层202,从而能够制造图2所示的接合结构体201。
接合结构体201的合金层202是在上述这样的接合结构体的制造过程中形成的金属间化合物。金属层104及镀层108为Ni或Cu的情况下,合金层202中包含SnNi合金或SnCu合金。即,在半导体元件101的金属层104与焊料接合层203的界面处、以及电路基板的镀层108与焊料接合层203的界面处包含SnNi合金或SnCu合金。通过在金属层104与焊料接合层203之间的合金层202、以及电路基板的镀层108与焊料接合层203之间的合金层202中形成SnNi合金或SnCu合金,金属层104与焊料接合层203、以及电路基板的镀层108与焊料接合层203借助金属进行接合,能够得到良好的接合强度。合金层202中可含有的SnNi合金及SnCu合金中,也可以含有Te和Au中的至少一种。即,半导体元件101的金属层104与焊料接合层203的界面处、以及电路基板的镀层108与焊料接合层203的界面处所含的SnNi合金或SnCu合金可以含有Te和Au中的至少一种。通过在SnNi合金及SnCu合金中包含Te和Au中的至少一种,合金层202成为多元合金,合金的强度提高,即使因热循环等而施加了应力时,也能够抑制合金层202中产生裂纹。接合结构体201的焊料接合层203中含有焊料合金105所含的Sb、Te、Au等金属元素,与接合前的焊料合金105具有大致同等的组成,但焊料接合层203中,Sn含有率按照形成合金层202时Sn发生了反应的比例而降低。
实施例
(实施例1)
如表1所示,准备将Sb含有率、Te含有率、Au含有率改变且余量为Sn的多个焊料合金105,在200℃的气氛温度中进行拉伸试验。为了进行拉伸试验,制作了将焊料合金浇铸为哑铃形状而得到的评价样品。评价样品的形状如下设定:固定于拉伸试验机的部分为直径6mm、长度20mm,哑铃的缩颈部分为直径3mm、长度20mm。将拉伸试验机的上下样品固定夹具的间隔设定为20mm,并固定评价样品,将气氛温度设为200℃后,以仅施加评价样品的轴方向的力的方式用拉伸试验机拉伸评价样品,从而进行评价样品的拉伸试验。
评价样品的伸长率(%)是指,拉伸试验中评价样品发生断裂时的固定夹具间隔的增加量相对于试验前的固定夹具的间隔20mm的比例。例如,评价样品发生断裂时的固定夹具间隔为40mm的情况下,伸长率为(40-20)/20×100=100(%)。
将拉伸试验中的伸长率(%)的测定结果一并示于表1中。
[表1]
拉伸试验的结果如下:Sb含有率为3wt%、Te含有率为0.01wt%、Au含有率为0.005wt%的实施例1-1为129%,Sb含有率为15wt%、Te含有率为0.01wt%、Au含有率为0.005wt%的实施例1-2为121%。其与不含Au的比较例1-1中的87%的伸长率、不含Au的比较例1-2中的85%的伸长率相比是良好的结果。
由上述结果可知:通过不仅添加Te还添加Au,高温中的伸长率有效地提高。可以认为:通过添加Te和Au这两种元素,发生Te向Sn相中的固溶和由此产生的Au向SnTe相中的固溶,因此,与仅添加了Te的SnSb系焊料相比,在高温中的伸长率进一步提高。由此,能够吸收在热循环时产生的反复应力,能够实现接合结构体的高可靠性。
(实施例2)
按照以下的实施例2-1~2-16(参照表2)中示出的方式制作本发明的接合结构体。
(实施例2-1)
首先准备焊料合金105、半导体元件101和电路基板106。对于焊料合金105,准备包含3wt%的Sb、0.01wt%的Te和0.005wt%的Au且余量为Sn的合金。对于半导体元件101准备如下元件:在纵长为10mm、横长为10mm且具有0.2mm厚度的硅芯片102的下表面设置由Ti形成的电阻层103,进而在由Ti形成的电阻层103的下表面设置由Ni形成的金属层104而得到的元件。对于电路基板106准备如下基板:具有纵长为20mm、横长为20mm且具有1mm的厚度的由铜形成的引线框,并在引线框107的表面设置有具有1μm厚度的由Ni形成的镀层108。
接着,在所准备的电路基板106的由Ni形成的镀层108上载置具有0.1mm厚度的焊料合金105,进而以焊料合金105与由Ni形成的金属层104接触的方式,在焊料合金105上设置半导体元件101,一边使温度每分钟升高10℃,一边进行从室温至300℃为止的加热。在300℃保持1分钟后,一边使温度每分钟降低10℃,一边进行从300℃至室温为止的冷却,从而制造接合结构体201。
(实施例2-2)
将焊料合金105的Au含有率设为1wt%,除此以外的条件与实施例2-1相同,制作了接合结构体201。
(实施例2-3)
将焊料合金105的Te含有率设为1.5wt%,除此以外的条件与实施例2-1相同,制作了接合结构体201。
(实施例2-4)
将焊料合金105的Au含有率设为1wt%,除此以外的条件与实施例2-3相同,制作了接合结构体201。
(实施例2-5)
将焊料合金105的Sb含有率设为5wt%,除此以外的条件与实施例2-1相同,制作了接合结构体201。
(实施例2-6)
将焊料合金105的Au含有率设为1wt%,除此以外的条件与实施例2-5相同,制作了接合结构体201。
(实施例2-7)
将焊料合金105的Te含有率设为1.5wt%,除此以外的条件与实施例2-5相同,制作了接合结构体201。
(实施例2-8)
将焊料合金105的Au含有率设为1wt%,除此以外的条件与实施例2-7相同,制作了接合结构体201。
(实施例2-9)
将焊料合金105的Sb含有率设为10wt%,除此以外的条件与实施例2-1相同,制作了接合结构体201。
(实施例2-10)
将焊料合金105的Au含有率设为1wt%,除此以外的条件与实施例2-9相同,制作了接合结构体201。
(实施例2-11)
将焊料合金105的Te含有率设为1.5wt%,除此以外的条件与实施例2-9相同,制作了接合结构体201。
(实施例2-12)
将焊料合金105的Au含有率设为1wt%,除此以外的条件与实施例2-11相同,制作了接合结构体201。
(实施例2-13)
将焊料合金105的Sb含有率设为15wt%,除此以外的条件与实施例2-1相同,制作了接合结构体201。
(实施例2-14)
将焊料合金105的Au含有率设为1wt%,除此以外的条件与实施例2-13相同,制作了接合结构体201。
(实施例2-15)
将焊料合金105的Te含有率设为1.5wt%,除此以外的条件与实施例2-13相同,制作了接合结构体201。
(实施例2-16)
将焊料合金105的Au含有率设为1wt%,除此以外的条件与实施例2-15相同,制作了接合结构体201。
(比较例2)
此外,按照以下的比较例2-1~2-15(参照表2)中示出的方式制作接合结构体。
(比较例2-1)
将焊料合金105的Sb含有率设为2wt%,除此以外的条件与实施例2-1相同,制作了接合结构体201。
(比较例2-2)
将焊料合金105的Te含有率设为1.5wt%,Au含有率设为1wt%,除此以外的条件与比较例2-1相同,制作了接合结构体201。
(比较例2-3)
将焊料合金105的Sb含有率设为3wt%,Te含有率设为0.005wt%,使除此以外的条件与比较例2-1相同,制作了接合结构体201。
(比较例2-4)
将焊料合金105的Au含有率设为1wt%,使除此以外的条件与比较例2-3相同,制作了接合结构体201。
(比较例2-5)
将焊料合金105的Te含有率设为0.01wt%,Au含有率设为0wt%,除此以外的条件与比较例2-3相同,制作了接合结构体201。
(比较例2-6)
将焊料合金105的Te含有率设为3wt%,Au含有率设为1.5wt%,除此以外的条件与比较例2-3相同,制作了接合结构体201。
(比较例2-7)
将焊料合金105的Sb含有率设为5wt%,除此以外的条件与比较例2-3相同,制作了接合结构体201。
(比较例2-8)
将焊料合金105的Te含有率设为1.5wt%,Au含有率设为1.5wt%,除此以外的条件与比较例2-7相同,制作了接合结构体201。
(比较例2-9)
将焊料合金105的Sb含有率设为10wt%,除此以外的条件与比较例2-3相同,制作了接合结构体201。
(比较例2-10)
将焊料合金105的Te含有率设为3wt%,Au含有率设为1wt%,除此以外的条件与比较例2-9相同,制作了接合结构体201。
(比较例2-11)
将焊料合金105的Sb含有率设为15wt%,除此以外的条件与比较例2-3相同,制作了接合结构体201。
(比较例2-12)
将焊料合金105的Te含有率设为0.01wt%,Au含有率设为0wt%,除此以外的条件与比较例2-11相同,制作了接合结构体201。
(比较例2-13)
将焊料合金105的Te含有率设为3wt%,Au含有率设为1.5wt%,除此以外的条件与比较例2-11相同,制作了接合结构体201。
(比较例2-14)
将焊料合金105的Sb含有率设为16wt%,除此以外的条件与实施例2-1相同,制作了接合结构体201。
(比较例2-15)
将焊料合金105的Te含有率设为1.5wt%,Au含有率设为1wt%,除此以外的条件与比较例2-14相同,制作了接合结构体201。
对所制作的实施例2-1~2-16及比较例2-1~2-15的接合结构体201进行热循环试验,进行耐裂纹性的评价。热循环试验使用液槽试验槽,将-40℃、150℃各5分钟作为1次循环,进行1000次循环。用超声波显微镜观察试验后的样品,将剥离面积除以接合面积来算出裂纹率。若裂纹率为10%以上,则无法将硅芯片的发热高效地散逸至引线框,因此,将小于10%判定为○,将10%以上判定为×。
将热循环试验后的裂纹率与判定结果一并示于表2中。
[表2]
Sb含有率为3wt%的实施例2-1及实施例2-4的裂纹率均为9%,判定均为○。与此相对,Sb含有率为2wt%的比较例2-1及比较例2-2的裂纹率分别为31%和32%,判定均为×。
另外,Sb含有率为15wt%的实施例2-13及实施例2-16的裂纹率分别为4%及7%,判定均为○。与此相对,Sb含有率为16wt%的比较例2-14及比较例2-15的裂纹率分别为31%及33%,判定均为×。
由以上的结果可知,Sb为3wt%以上且15wt%以下的情况下,耐裂纹性提高。这可被认为是,Sb低于3wt%的情况下,无法得到SnSb化合物的分散强化的效果。另外,Sb超过15wt%的情况下,虽然强度提高,但是焊料合金的延展性降低,因此可推测耐裂纹性降低。
在Sb含有率为3wt%以上且15wt%以下的组成的样品中,根据实施例2-1~16,Te含有率为0.01wt%以上且1.5wt%以下、并且Au含有率为0.005wt%以上且1wt%以下的情况下,裂纹率变得小于10%,得到判定为○的良好结果。
即使是Sb含有率为3wt%以上且15wt%以下的组成的样品,像比较例2-5、比较例2-12这样,Au含有率为0wt%的情况下,裂纹率为20%以上,判定为×。
即使是Sb含有率为3wt%以上且15wt%以下的组成的样品,像比较例2-3、比较例2-4、比较例2-7、比较例2-9、比较例2-11这样,Te含有率为0.005wt%以下的情况下,裂纹率为17%以上,判定为×。
即使是Sb含有率为3wt%以上且15wt%以下的组成的样品,像比较例2-6、比较例2-10、比较例2-13这样,Te含有率为3wt%以上的情况下,裂纹率为19%以上,判定为×。
即使是Sb含有率为3wt%以上且15wt%以下的组成的样品,像比较例2-6、比较例2-8、比较例2-13这样,Au含有率为1.5wt%以上的情况下,裂纹率为19%以上,判定为×。
由以上的结果可知,Te含有率为0.01wt%以上且1.5wt%以下、且Au含有率为0.005wt%以上且1wt%以下的情况下,实现了特别优异的耐裂纹性。这可被认为是,Te含有率为0.005wt%以下的情况下,几乎得不到Te的固溶所带来的效果。另外,Te含有率为3wt%以上的情况下,无法固溶而以化合物的形式析出,因此可推测延展性恶化,耐裂纹性降低。
另外,可推测:通过以Au含有率至少为0.005wt%的方式进行添加,离子半径不同的Au在固溶有Te的Sn中复杂地置换,并产生位错,由此高温中的伸长率提高,耐裂纹性也提高。另一方面,若Au含有率多于1wt%,则作为脆弱化合物的AuSn析出,因此可认为耐裂纹性并未提高。
(实施例3)
此外,按照以下的实施例3-1所示的方式制作本发明的接合结构体。
(实施例3-1)
准备焊料合金105、半导体元件101和电路基板106。首先,将Sb为3wt%、Te为0.01wt%且余量为Sn的合金成形为0.1mm厚的板状。进而,在成形的焊料合金的上下两面,按照相对于上述合金板整体重量的比例为1wt%的方式,以0.19μm的厚度实施Au镀覆。此时,在构成Au镀层的金的重量和所形成的焊料合金的重量的总重量中,Sb具有13wt%的比例,Te具有0.01wt%的比例,Au具有1wt%的比例。
对于半导体元件101,准备在纵长为10mm、横长为10mm且具有0.2mm厚度的硅芯片102的下表面设置有由Ti形成的电阻层103,进而在由Ti形成的电阻层103的下表面设置有由Ni形成的金属层104的元件。对于电路基板106,准备纵长为20mm、横长为20mm且具有1mm厚度的电路基板。电路基板106具有由铜形成的引线框,在引线框107的表面设置有具有1μm厚度的由Ni形成的镀层108。
接着,在所准备的电路基板106的由Ni形成的镀层108上载置具有100.38μm的厚度的焊料合金105。进而,按照焊料合金105与由Ni形成的金属层104接触的方式,在焊料合金105上设置半导体元件101,一边使温度每分钟升高10℃,一边进行从室温至300℃为止的加热。在300℃保持1分钟后,一边使温度每分钟降低10℃,一边进行从300℃至室温为止的冷却,由此制造接合结构体201。所制作的接合结构体进行与实施例2同样的热循环试验,进行耐裂纹性的判定。
实施例3-1的热循环试验后的裂纹率为8%,判定为○。其原因可被认为是,在实施例3-1中对SnSbTe焊料合金实施了Au镀覆,通过接合时的加热而使Au扩散至焊料接合层,因此形成了与实施例2-2同样的接合结构体。由实施例3-1的结果可知,只要是本发明的组成范围,则Au可以形成于焊料合金的表面。
根据本发明的焊料合金及接合结构体,高温中的伸长率得以改善,接合结构体的耐裂纹性提高,因此,可以适用于电源模块等半导体元件的接合用途。

Claims (3)

1.一种焊料合金,其中,Sb的含有率为3wt%以上且15wt%以下,Te的含有率为0.01wt%以上且1.5wt%以下,并且,Au的含有率为0.005wt%以上且1wt%以下,余量为Sn。
2.一种接合结构体,其是由半导体元件与电路基板借助包含Sb、Te、Au和Sn的焊料接合层进行接合而得到的,
所述半导体元件的金属层与所述焊料接合层的界面处、以及所述电路基板的镀层与焊料接合层的界面处包含SnNi合金或SnCu合金。
3.根据权利要求2所述的接合结构体,其中,所述半导体元件的金属层与所述焊料接合层的界面处、以及所述电路基板的镀层与所述焊料接合层的界面处包含的SnNi合金或SnCu合金中包含Te和Au中的至少一种。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109396586A (zh) * 2018-12-13 2019-03-01 华北水利水电大学 一种环氧树脂器件与pcb印刷电路板基材的钎焊方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4140635A1 (en) * 2021-08-31 2023-03-01 Infineon Technologies AG Semiconductor device with a ni comprising layer and method for fabricating the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004026527A1 (en) * 2002-09-19 2004-04-01 Sumitomo Metal Mining Co., Ltd. Soldering filler metal, assembly method for semiconductor device using same, and semiconductor device
JP2006035310A (ja) * 2004-06-24 2006-02-09 Sumitomo Metal Mining Co Ltd 無鉛はんだ合金
CN103167926A (zh) * 2010-12-24 2013-06-19 株式会社村田制作所 接合方法、接合结构、电子装置、电子装置的制造方法及电子部件
WO2014057261A1 (en) * 2012-10-09 2014-04-17 Alpha Metals, Inc. Lead-free and antimony-free tin solder reliable at high temperatures
CN103962744A (zh) * 2009-04-20 2014-08-06 松下电器产业株式会社 焊锡材料及电子部件接合体
CN104835796A (zh) * 2015-05-07 2015-08-12 嘉兴斯达微电子有限公司 一种无铅扩散焊的功率模块

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102196881B (zh) * 2008-10-24 2014-06-04 三菱电机株式会社 半导体装置
US8348139B2 (en) * 2010-03-09 2013-01-08 Indium Corporation Composite solder alloy preform
WO2012077228A1 (ja) * 2010-12-10 2012-06-14 三菱電機株式会社 無鉛はんだ合金、半導体装置、および半導体装置の製造方法
JP6128211B2 (ja) * 2013-05-10 2017-05-17 富士電機株式会社 半導体装置および半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004026527A1 (en) * 2002-09-19 2004-04-01 Sumitomo Metal Mining Co., Ltd. Soldering filler metal, assembly method for semiconductor device using same, and semiconductor device
JP2006035310A (ja) * 2004-06-24 2006-02-09 Sumitomo Metal Mining Co Ltd 無鉛はんだ合金
CN103962744A (zh) * 2009-04-20 2014-08-06 松下电器产业株式会社 焊锡材料及电子部件接合体
CN103167926A (zh) * 2010-12-24 2013-06-19 株式会社村田制作所 接合方法、接合结构、电子装置、电子装置的制造方法及电子部件
WO2014057261A1 (en) * 2012-10-09 2014-04-17 Alpha Metals, Inc. Lead-free and antimony-free tin solder reliable at high temperatures
CN104835796A (zh) * 2015-05-07 2015-08-12 嘉兴斯达微电子有限公司 一种无铅扩散焊的功率模块

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109396586A (zh) * 2018-12-13 2019-03-01 华北水利水电大学 一种环氧树脂器件与pcb印刷电路板基材的钎焊方法
CN109396586B (zh) * 2018-12-13 2020-09-01 华北水利水电大学 一种环氧树脂器件与pcb印刷电路板基材的钎焊方法

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