CN105592636B - 电子装置及其制造方法 - Google Patents

电子装置及其制造方法 Download PDF

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Publication number
CN105592636B
CN105592636B CN201510741043.XA CN201510741043A CN105592636B CN 105592636 B CN105592636 B CN 105592636B CN 201510741043 A CN201510741043 A CN 201510741043A CN 105592636 B CN105592636 B CN 105592636B
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alloys
electronic device
electrical components
alloy
circuit board
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CN105592636A (zh
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上村泰纪
清水浩三
作山诚树
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Fujitsu Ltd
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Fujitsu Ltd
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    • HELECTRICITY
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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/26Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C13/00Alloys based on tin
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C28/00Alloys based on a metal not provided for in groups C22C5/00 - C22C27/00
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    • C22CALLOYS
    • C22C30/00Alloys containing less than 50% by weight of each constituent
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

本发明公开了一种电装置及其制造方法。电装置包括:第一电部件、第二电部件、以及连接第一电部件与第二电部件的In‑Sn‑Ag合金,所述In‑Sn‑Ag合金包含AgIn2和Ag2In,Ag2In含量低于AgIn2含量。

Description

电子装置及其制造方法
技术领域
本文所讨论的实施方案涉及其中电部件(电子/电气部件)是利用接合材料安装的电子装置以及用于制造该电子装置的方法。
背景技术
通常,由于其高的可加工性和生产率,利用钎焊的安装方法被广泛地用于安装电部件(例如,印刷线路板上的半导体器件)。当通过钎焊将半导体器件安装在印刷线路板上时,高的回流温度引起半导体器件和印刷线路板的翘曲,从而导致电子装置的半导体器件与印刷线路板之间的钎料接合部具有差的机械连接和电连接的可靠性。因而,在低的回流温度下利用具有低熔点的钎焊材料将半导体器件钎焊至印刷线路板。具有低熔点的一种钎焊材料为熔点为117℃的InSn共晶钎料。与Sn-Bi合金钎焊材料和Sn-Ag-Cu合金钎焊材料相比,In-Sn合金钎焊材料具有较低的熔点和较低的强度。提出使具有低熔点的钎焊材料包含金属间化合物以增加钎焊材料的强度(例如,参见日本公开特许公报第2006-909号和第2002-124533号)。然而,即使在利用如上所述钎焊材料安装电部件时,例如由于对在电部件上的跌落冲击的抵抗不足,电子装置的电部件之间具有差的机械连接和电连接可靠性。
发明内容
本文所讨论的实施方案的目的为提供一种在电部件之间具有高的机械连接和电连接的可靠性的电子装置。
根据本发明的一个方面,一种装置包括:第一电部件;第二电部件;以及连接第一电部件与第二电部件的In-Sn-Ag合金,In-Sn-Ag合金包含AgIn2和Ag2In,Ag2In含量低于AgIn2含量。
本文所讨论的实施方案提供了一种在电部件之间具有高的机械连接和电连接的可靠性的电子装置。
附图说明
图1A为根据第一实施方案的电子装置的截面图;
图1B为被图1A中的虚线A围绕的部分的放大图;
图2为关于具有0重量%、1重量%、5重量%和10重量%的Ag含量的In-Sn-Ag合金的拉伸测试结果的曲线图;
图3为关于具有0重量%、1重量%、3重量%和5重量%的Ag含量的In-Sn-Ag合金的高速剪切强度测试结果的曲线图;
图4A为接合至Cu板的In-Sn-1Ag合金中的Ag的元素分布图;
图4B为接合至Cu板的In-Sn-5Ag合金中的Ag的元素分布图;
图4C为接合至Cu板的In-Sn-10Ag合金中的Ag的元素分布图;
图5为制造根据第一实施方案的电子装置的过程的截面图(1);
图6A为制造根据第一实施方案的电子装置的过程的截面图(2);
图6B为被图6A中的虚线A围绕的部分的放大图;
图7为制造根据第一实施方案的电子装置的过程的截面图(3);
图8为制造根据第一实施方案的电子装置的过程的截面图(4);
图9为制造根据第一实施方案的电子装置的过程的截面图(5);
图10为制造根据第一实施方案的电子装置的过程的截面图(6);
图11为在对Cu板上的In-Sn-1Ag合金进行回流加热的步骤中和在回流加热步骤之后的冷却步骤中加热器中温度变化的曲线图;
图12A为根据第二实施方案的电子装置的截面图;
图12B为被图12A中的虚线A围绕的部分的放大图;
图12C为被图12A中的虚线B围绕的部分的放大图;
图13为制造根据第二实施方案的电子装置的过程的截面图(1);
图14为制造根据第二实施方案的电子装置的过程的截面图(2);
图15为制造根据第二实施方案的电子装置的过程的截面图(3);
图16为制造根据第二实施方案的电子装置的过程的截面图(4);
图17为制造根据第二实施方案的电子装置的过程的截面图(5);
图18为制造根据第二实施方案的电子装置的过程的截面图(6);
图19为制造根据第二实施方案的电子装置的过程的截面图(7);
图20为制造根据第二实施方案的电子装置的过程的截面图(8);
图21为制造根据第二实施方案的电子装置的过程的截面图(9);
图22为列出回流之后的In-Sn-1Ag合金、In-Sn-3Ag合金和In-Sn-5Ag合金的In含量、AgIn2含量和Ag2In含量的表;以及
图23为列出回流之后的In-Sn共晶钎料、In-Sn-1Ag合金、In-Sn-3Ag合金和In-Sn-5Ag合金的强度和延展性的表。
具体实施方式
下面将参照附图详细描述本文所讨论的实施方案。
(第一实施方案)下面将参照图1描述根据第一实施方案的电子装置的结构。图1A和图1B为根据第一实施方案的电子装置的截面图。
参照图1A,根据第一实施方案的电子装置1包括半导体器件11、在半导体器件11处的电极12、电路板22、在电路板22上的电极21、接合部31和底部填料41。在电子装置1中,半导体器件11经由电极12、接合部31和电极21电连接至电路板22。半导体器件11与电路板22之间的空间被填充有底部填料41。
图1B为被图1A中的虚线A围绕的部分的放大图。在由Cu制成的电极12上设置有阻挡金属膜15,所述电极12设置在半导体器件11的表面上。阻挡金属膜15依次包括在Cu电极12上的Ni膜13和Au膜14。在由Cu制成的电极21上设置有阻挡金属膜25,所述电极21设置在电路板22的表面上。阻挡金属膜25依次包括在Cu电极21上的Ni膜23和Au膜24。在Cu电极12和Cu电极21上的阻挡金属膜15和阻挡金属膜25可以抑制连接介质32向Cu电极12和Cu电极21中的扩散,从而提高接合部31的连接的可靠性。
接合部31由包含金属间化合物Ag2In和金属间化合物AgIn2的In-Sn-Ag合金构成。接合部31的Ag2In含量低于接合部31的AgIn2含量。在Ag2In含量和AgIn2含量满足这个条件的情况下,接合部31具有高的强度和延展性。接合部31优选地包含不小于43重量%并且不大于60重量%的In,这是因为这还增加了接合部31的强度。接合部31优选地包含3重量%或更少的Ag这是因为这还增加了接合部31的强度和延展性。
如果接合部31的In含量少于43重量%,则接合部31包含大量长大(grown)的Ag2In而不是精细分散的AgIn2并且接合部31具有不足的延展性。如果接合部31的In含量多于60重量%,则接合部31中的金相组织不是In相和Sn相的共晶金相组织,并且其中在In中溶解有Sn的In相的金相组织生长。因而,接合部31具有不足的强度。
就接合部31的高强度和延展性而言,接合部31的In含量较优选地在不小于48重量%并且不大于58重量%的范围,特别优选地在不小于50重量%并且不大于54重量%的范围。
在下面的实验中检验接合部31的接合材料的组成、接合部31中的金属间化合物与接合部31的强度和延展性之间的关系。
一种用于评估连接的可靠性的方法为根据国际标准化组织标准ISO6892-1的金属材料的拉伸测试。在这个评估测试方法中,通过向接合材料施加拉伸应变直到接合材料破裂来测量接合材料的强度和延展性。通过所述评估测试方法来测量强度和延展性。
下面的接合材料(1)至(4)被加热至峰值温度150℃,然后被冷却以制备在平行部分的截面中具有5mm的宽度、4mm的厚度和20mm的标距长度的拉伸测试样品。
(1)In-48Sn共晶钎料
(2)由In-48Sn共晶钎料和1重量%的Ag构成的In-Sn-1Ag合金
(3)由In-48Sn共晶钎料和5重量%的Ag构成的In-Sn-5Ag合金
(4)由In-48Sn共晶钎料和10重量%的Ag构成的In-Sn-10Ag合金
利用INSTRON拉伸测试仪4466以2mm/分钟的十字头速度对样品进行拉伸测试。图2为关于样品的拉伸测试结果的曲线图。拉伸测试遵从标准ISO 6892-1。在图2中,横轴为接合材料的应变(位移),纵轴为施加到接合材料的载荷。在图2的曲线图中,纵轴上的最大值与接合材料的强度对应。在图2的曲线图中,当施加到接合材料的载荷随着应变增加显著下降时,接合材料破裂。在接合材料破裂时的点处的应变与延展性对应。
在图2中,在In-Sn-10Ag合金中的载荷在约4.6mm的位移处显著下降。另一方面,在In-48Sn共晶钎料、In-Sn-1Ag合金和In-Sn-5Ag合金中的载荷在图2的范围之外的位移处显著下降。
从图2的曲线图中发现,In-Sn-10Ag合金在经受拉伸测试的接合材料之中具有最高的强度并且具有非常低的延展性。相比之下,In-Sn-1Ag合金在经受拉伸测试的接合材料之中具有最低的强度。还发现,In-Sn-1Ag合金在破裂时的应变(未示出)大于In-Sn共晶钎料在破裂时的应变并且In-Sn-1Ag具有最高的延展性。
用于评估连接的可靠性的另一方法为根据电子设备工程联合委员会标准JESD22-B117A的高速剪切测试。在这个评估测试方法中,向接合材料施加机械剪切应力以测量接合材料的强度和延展性。通过评估测试方法测量强度和延展性。
然后,通过在150℃的峰值温度下对设置在铜电极上的直径为540μm的下面的接合材料(5)至接合材料(8)进行回流来制备高速剪切测试样品。回流之后的样品的直径为600μm。
(5)In-48Sn共晶钎料
(6)由In-48Sn共晶钎料和1重量%的Ag构成的In-Sn-1Ag合金
(7)由In-48Sn共晶钎料和3重量%的Ag构成的In-Sn-3Ag合金
(8)由In-48Sn共晶钎料和5重量%的Ag构成的In-Sn-5Ag合金
在图22中示出的表列出了回流之后In-Sn-1Ag合金、In-Sn-3Ag合金和In-Sn-5Ag合金的In含量、AgIn2含量和Ag2In含量。根据In、AgIn2和Ag2In的面积比和比重来计算合金的In含量、AgIn2含量和Ag2In含量。在利用电子探针显微分析仪制备的元素分布图上测量In、AgIn2和Ag2In的面积比。
利用Dage测试机器DAGE SIRIES 4000HS在距离电极100μm的高度处并且以3000mm/s的剪切速度对样品进行高速剪切测试。图3为关于样品的高速剪切测试结果的曲线图。高速剪切测试遵从标准JESD 22-B117A。在图3中,横轴为接合材料的位移,并且纵轴为施加到接合材料的载荷。在图3的曲线图中,在纵轴上的最大值为接合材料的强度。在当施加到接合材料的载荷下降至最大载荷的一半时的点处的位移与接合材料的延展性对应。当施加到接合材料的载荷下降至最大载荷的一半时,接合材料破裂。
在图23中示出的表列出了回流之后In-Sn共晶钎料、In-Sn-1Ag合金、In-Sn-3Ag合金和In-Sn-5Ag合金的强度和延展性。从表2发现,与其他接合材料相比,In-Sn-5Ag合金具有较高的强度。然而,与其他接合材料相比,In-Sn-5Ag合金具有较低的延展性。还发现与不含Ag的InSn共晶钎料相比,In-Sn-1Ag合金和In-Sn-3Ag合金具有较高的强度和延展性。因为与In-Sn共晶钎料相比,In-Sn-3Ag合金具有稍高的延展性,向In-Sn共晶钎料添加多于3重量%的Ag可能降低了In-Sn共晶钎料的延展性。
利用电子探针显微分析仪获得接合至铜板的In-Sn-1Ag合金、In-Sn-5Ag合金和In-Sn-10Ag合金的每一种元素的元素分布图。图4A为In-Sn-1Ag合金中Ag的元素分布图。图4B为In-Sn-5Ag合金中Ag的元素分布图。图4C为In-Sn-10Ag合金中Ag的元素分布图。在In-Sn-10Ag合金中,AgIn2含量在2重量%至3重量%的范围内,Ag2In含量在10重量%至13重量%的范围内,以及In含量为47重量%。
从In-Sn-1Ag合金的每个元素的元素分布图中发现,在图4A中代表Ag的白点与金属间化合物AgIn2大致对应。每个点的大小为约1μm。AgIn2一般在In-Sn-1Ag合金中精细分布。In-Sn-1Ag合金的AgIn2含量在2重量%至4重量%的范围内。Ag2In构成约0.0001重量%并且在每个元素的元素分布图中不能被清晰地识别。
从In-Sn-1Ag合金的元素分布图可以发现,In-Sn-1Ag合金包括精细分散的AgIn2。基于图2中的拉伸测试结果,与InSn共晶钎料相比,In-Sn-1Ag合金具有较高的延展性。根据测量结果认为AgIn2有助于In-Sn-Ag合金的延展性。
发现,尽管基于图2中的拉伸测试结果、与InSn共晶钎料相比In-Sn-1Ag合金具有稍低的强度,但是基于图3的高速剪切测试结果、与InSn共晶钎料相比In-Sn-1Ag合金具有较高的强度。在拉伸测试中根据接合材料的拉伸应变来测量接合材料本身的强度,而接合至铜板的接合材料的剪切强度在高速剪切测试中测量。认为,在高速剪切测试中In-Sn-Ag合金与铜板的铜形成金属间化合物层并且因而具有高的强度。高速剪切测试结果示出了接合至电部件的接合材料的强度并且示出了在In-Sn-1Ag合金与电部件之间的接合部具有高的强度和延展性。Cu不是在金属与In-Sn-Ag合金接合材料之间的界面处可以形成金属间化合物层并且因而具有高的强度的唯一金属。In-Sn-Ag合金也可以在In-Sn-Ag合金与用作电极材料的金属(例如,Ni或Au)之间的界面处形成金属间化合物层,并且因而具有高的强度。尽管在拉伸测试中具有低的强度,但是在高速剪切测试中具有高强度的接合材料在电子装置中几乎没有实际困难。
在图4B和图4C中,大小在约10μm至50μm范围内的白色区域表示金属间化合物Ag2In,并且大小为约1μm的白色区域表示金属间化合物AgIn2。与精细分散在In-Sn-Ag合金中的AgIn2不同,在In-Sn-Ag合金中Ag2In长大。在图4B和图4C中,因为与AgIn2相比长大的Ag2In占据了较大的面积,所以In-Sn-5Ag合金和In-Sn-10Ag合金中的每一种中的Ag2In含量高于对应的AgIn2含量。在表1中,In-Sn-5Ag合金的AgIn2含量在2重量%至3重量%的范围内,并且Ag2In含量在3.5重量%至4.5重量%的范围内。
从In-Sn-10Ag合金的元素分布图发现In-Sn-10Ag合金包含精细分散的AgIn2和长大的Ag2In。基于图2中的拉伸测试结果,与InSn共晶钎料相比,In-Sn-10Ag合金具有较高的强度但是非常低的延展性。
将图4A与图4C进行比较,尽管In-Sn-1Ag合金和In-Sn-10Ag合金两者均包含AgIn2,但是In-Sn-10Ag合金与In-Sn-1Ag合金的不同之处在于In-Sn-10Ag合金包含长大的Ag2In。因而,认为In-Sn-10Ag合金由于长大的Ag2In而具有较高的强度但是较低的延展性。
In-Sn-1Ag合金和In-Sn-3Ag合金为其中Ag2In含量比AgIn2含量低的In-Sn-Ag合金。其中Ag2In含量比AgIn2含量高的In-Sn-Ag合金导致接合部31的非常低的延展性以及电子装置1具有差的机械连接和电连接的可靠性。
在长大的Ag2In含量高于AgIn2含量的情况下,由于Ag2In晶粒大于AgIn2晶粒,所以In-Sn-Ag合金的变形往往引起在Ag2In晶粒边界处的应力聚集并且使In-Sn-Ag合金破裂。因而,包含长大的Ag2In的In-Sn-Ag合金往往具有低的延展性。另一方面,强度增加至阻碍形变的程度。由于In-Sn合金的低熔点,较大的金属间化合物晶粒(例如,长大的Ag2In)更可能阻碍形变。因而,包含长大的Ag2In的In-Sn-Ag合金具有高的强度。
在接合部31是由包含AgIn2但是不包含Ag2In的In-Sn-Ag合金构成的情况下,接合部31具有低的强度,并且电子装置1的连接可靠性不足。
在包含精细分散的AgIn2但是不含Ag2In的In-Sn-Ag合金中,精细分散的AgIn2晶粒可以由于其被精细地分散而缓和应力并且可以抑制破裂。因而,包含精细分散的AgIn2的In-Sn-Ag合金具有高的延展性。另一方面,小的晶粒例如精细分散的AgIn2具有短的晶粒边界。短的晶粒边界往往由于晶粒边界滑动而产生变形。尽管由于晶粒边界滑动而引起的变形通常在高温下发生,但是因为In-Sn合金具有低的熔点所以产生了由于晶粒边界滑动而引起的变形。因而,包含精细分散的AgIn2的In-Sn-Ag合金具有低的强度。
尽管根据第一实施方案的电子装置1包括阻挡金属膜,但是可以省略阻挡金属膜。可以在没有阻挡金属膜的情况下将接合部直接设置Cu电极上。尽管在本实施方案中半导体器件被安装在电路板上,但是也可以为另外的实施方案。例如,在另一些实施方案中,本实施方案的接合部可以被应用于各种电部件(例如,半导体器件与插入件(互联导电物,interposer),或者插入件与电路板)的接合部。
(用于制造根据第一实施方案的电子装置的方法)
下面将参照图5至图10描述用于制造根据第一实施方案的电子装置的方法。图5至图10示出了制造根据第一实施方案的电子装置的过程。
如图5所示,例如通过化学镀方法(electroless plating method)在半导体器件11的表面上形成主要由Cu构成的Cu电极12。在Cu电极12上形成有阻挡金属膜15。例如,阻挡金属膜15由Ni膜13和Au膜14构成。Ni膜13是通过化学镀方法形成的并且厚度为约5μm。Au膜14通过化学镀方法被形成在Ni膜13上并且厚度在约0.1μm至0.3μm的范围内。阻挡金属膜15可以抑制连接介质32的扩散到Cu电极12中并且从而提高接合部31的连接的可靠性。
如图6A所示,通过化学镀方法在电路板22的表面上形成主要由Cu构成的Cu电极21。图6B为被图6A中的虚线A围绕的部分的放大图。阻挡金属膜25形成在电路板22的表面上的主要由Cu构成的Cu电极21上。例如,阻挡金属膜25由Ni膜23和Au膜24构成。Ni膜23是通过化学镀方法形成的并且厚度为约5μm。Au膜24通过化学镀方法被形成在Ni膜23上并且厚度在约0.1μm至0.3μm的范围内。阻挡金属膜25可以抑制连接介质32的扩散到Cu电极21中并且从而提高接合部31的连接的可靠性。
在形成阻挡金属膜25之后,在阻挡金属膜25上沉积由In-Sn-Ag合金构成并且厚度在约10μm至15μm范围内的连接介质32。由In-Sn-Ag合金构成的连接介质32包含不小于43重量%并且不大于60重量%的In以及不小于1重量%并且不大于3重量%的Ag。在连接介质32由包含不小于43重量%并且不大于60重量%的In以及不小于1重量%并且不大于3重量%的Ag的In-Sn-Ag合金构成的情况下,回流之后连接介质32可以包含与Ag2In相比较多的AgIn2,并且在图1A中的电子装置1的接合部31具有高的强度和延展性。在下面描述的用于制造根据第一实施方案的电子装置的方法中,为了简洁的目的在附图中省略了阻挡金属膜15和阻挡金属膜25。
如图7所示,向电路板22施加助焊剂51。制备在图5中所示出的半导体器件11。当半导体器件11被倒装芯片接合器61保持时,半导体器件11的电极12和电路板22的电极21被合适地放置。
如图8所示,然后利用助焊剂51的粘着性将利用倒装芯片接合器61保持的半导体器件11临时地附接至电路板22。如本文所使用的术语粘着性指的是利用粘性来保持待被接合的部件之间位置关系的性质。
如图9所示,然后将由包含不小于43重量%并且不大于60重量%的In以及不大于3重量%Ag的In-Sn-Ag合金构成的连接介质32加热至不低于连接介质32的熔点的温度(即113℃或更高)。然而,过高的温度导致电部件的增加的翘曲和连接的较低的可靠性。因而,优选地将连接介质32加热至例如在115℃至150℃范围内的温度,并优选地使连接介质32在例如115℃至150℃范围内的温度下熔化,从而将半导体器件11接合至电路板22。
在如上所述的In-Sn-Ag合金的固相线温度之上的温度下的冷却期间,Ag2In从熔融状态的In-Sn-Ag合金结晶。当结晶的Ag2In在熔融的In-Sn-Ag合金中迁移时,结晶的Ag2In与另一结晶的Ag2In结合并且长大。长大的Ag2In是造成低延展性的原因。在低于In-Sn-Ag合金的固相线温度的温度处的冷却期间,金属间化合物AgIn2从固态In-Sn-Ag合金中析出。析出的AgIn2在固态In-Sn-Ag合金中不迁移并且保持精细分散的状态。从图4A中的In-Sn-1Ag合金的元素分布图和图3中的高速剪切测试结果发现,包含精细分散的AgIn2的In-Sn-Ag合金具有高的强度和延展性。
图11为利用回流装置对在Cu板上的In-Sn-1Ag合金进行回流的温度分布。图4A为通过如图11中所示出的温度分布进行回流而制备的样品的截面的元素分布图。
在图11中,横轴为时间(秒),并且纵轴为温度(℃)。In-Sn-1Ag合金的固相线温度为约113℃。在图11中,S1表示在固相线温度之上的温度范围,并且S2表示在固相线温度之下的温度范围。在图11中,温度范围S1中的In-Sn-1Ag合金处于熔融状态,以及温度范围S2中的In-Sn-1Ag合金处于固态。
在S2中AgIn2析出。在温度范围S2中的冷却步骤中,当回流装置的内部温度小于约50℃时,AgIn2不能充分地析出,因而,回流装置的冷却控制被降低至约50摄氏度。当回流装置的内部温度在温度范围S2中并且大于50℃时,在从回流装置中取出的Cu板上In-Sn-1Ag合金迅速被冷却,并且可以减少AgIn2的析出。
在回流加热步骤开始之后的约190秒,回流装置的内部温度达到在温度范围S1内的约122℃,并且In-Sn-1Ag合金处于熔融状态。在In-Sn-1Ag合金被加热并且熔化之后,停止对回流装置进行加热,或者降低加热温度。将回流装置的内部温度降至在温度范围S2中的温度,从而使In-Sn-1Ag合金冷却并且凝固。在回流装置的内部温度达到约50摄氏度之后,将在Cu板上的In-Sn-1Ag合金从回流装置中取出并且自然地冷却。
如图11所示,在温度范围S1中的冷却步骤中,In-Sn-1Ag合金的平均冷却速率高于在温度范围S2中的冷却步骤中In-Sn-1Ag合金的平均冷却速率。可以控制在冷却步骤中在回流装置中的冷却速率,使得In-Sn-1Ag合金的AgIn2含量高于In-Sn-1Ag合金的Ag2In含量。在温度范围S1中在冷却步骤中In-Sn-1Ag合金的平均冷却速率优选地不小于1.0℃/s以降低In-Sn-1Ag合金的Ag2In含量。在温度范围S2中在冷却步骤中In-Sn-1Ag合金的平均冷却速率优选为0.4℃/s(低于在温度范围S1中的平均冷却速率1.0℃/s)以增加In-Sn-1Ag合金的AgIn2含量。
基于从在图11中示出的在Cu板上的In-Sn-1Ag合金的温度分布获得的实验数据,在连接介质32的固相线温度之上的冷却步骤中的平均冷却速率高于在连接介质32的固相线温度之下的冷却步骤中的平均冷却速率。在这样的冷却条件下冷却导致在图1A中示出的电子装置1的接合部31的AgIn2含量高于Ag2In含量,并且导致了接合部31的高的强度和延展性。
在图9中所示出的步骤之后,去除残余的助焊剂51。例如,可以通过在约70℃处将在图9中所示出的结构浸没在二甲苯和异丙醇的混合有机溶剂中保持1小时来去除残余的助焊剂51。然后例如在120℃下对在图9中所示出的其中已经去除了残余的助焊剂51的结构进行干燥2小时,并且利用底部填料41填充所述结构,从而完成在图10中所示出的电子装置1。在半导体器件11与电路板22之间的底部填料41增加了其间的接合强度并且提高了电子装置1的连接的可靠性。前述为用于制造根据第一实施方案的电子装置的方法。
如上所述,在根据第一实施方案的电子装置1中,电部件之间的接合部由熔点为约113℃并且Ag2In含量低于AgIn2含量的In-Sn-Ag合金构成。因此,可以通过在低的温度下回流将电部件接合在一起。这降低了电部件的翘曲,并且即使在冲击或应力下接合部也具有高的延展性和强度。因而,接合部无缺陷(例如,裂纹),并且电子装置具有高的连接的可靠性。
(第二实施方案)本实施方案涉及其中电部件是分阶段安装的电子装置。
下面将描述根据第二实施方案的电子装置的结构。图12A为根据第二实施方案的电子装置的截面图。
参照图12A,电子装置100包括半导体器件101、在半导体器件101上的电极102、插入件110、在插入件110上的电极111和电极121、电路板120、在电路板120上的电极131、第一接合部150、第二接合部160、底部填料130和底部填料140。在电子装置100中,半导体器件101经由第一接合部150电连接至插入件110。半导体器件101与插入件110之间的空隙被填充有底部填料130。插入件110经由第二接合部160电连接至电路板120。插入件110与电路板120之间的空隙被填充有底部填料140。光学部件170耦接至半导体器件101。下面的详细描述将省略电子装置100的结构。
图12B为被图12A中的虚线A围绕的部分的放大图。如12C为被图12A中的虚线B围绕的部分的放大图。首先,下面将描述被虚线A围绕的部分的放大图。阻挡金属膜105被设置在由Cu制成的每个电极102上,电极102被设置在半导体器件101的表面上。阻挡金属膜105包括依次在Cu电极102上的Ni膜103和Au膜104。阻挡金属膜115被设置在由Cu制成的电极111的每一个上,电极111被设置在插入件110的表面上。阻挡金属膜115包括依次在Cu电极111上的Ni膜112和Au膜113。
下面将描述被虚线B围绕的部分的放大图。阻挡金属膜125被设置在由Cu制成的每个电极121上,电极121被设置在插入件110的表面上。阻挡金属膜125包括依次在Cu电极121上的Ni膜123和Au膜123。阻挡金属膜135被设置在由Cu制成的电极131的每一个上,电极131被设置在电路板120的表面上。阻挡金属膜135包括依次在Cu电极131上的Ni膜132和Au膜133。
在Cu电极102和Cu电极111上的阻挡金属膜105和阻挡金属膜115可以抑制连接介质151扩散到Cu电极102和Cu电极111中并且因而提高了第一接合部150的连接的可靠性。
在Cu电极121和Cu电极131上的阻挡金属膜125和阻挡金属膜135可以抑制连接介质161扩散到Cu电极121和Cu电极131中并且因而提高了第二接合部160的连接的可靠性。
半导体器件101经由第一接合部150电连接至插入件110。例如,第一接合部150由熔点为138℃的Sn-58Bi合金、熔点为227℃的Sn-0.7Cu合金、熔点为217℃的Sn-3Ag-0.5Cu合金和熔点为221℃的Sn-3.5Ag合金构成。
电路板120经由第二接合部160电连接至插入件110。第二接合部160的熔点为113℃并且由Ag2In含量低于AgIn2含量的In-Sn-Ag合金构成。
因为根据第二实施方案的电子装置100的第二接合部160由Ag2In含量低于AgIn2含量的In-Sn-Ag合金构成,所以电子装置100具有高强度和延展性。尽管光学部件170非常易受热的影响,但是由Ag2In含量低于AgIn2含量的In-Sn-Ag合金构成的第二接合部160使得能够在低温下进行安装,因而提高了光学部件170的连接的可靠性。
虽然根据第二实施方案的电子装置100包括阻挡金属膜,但是阻挡金属膜可以省略。可以在没有阻挡金属膜的情况下将接合部直接设置在Cu电极上。尽管在本实施方案中半导体器件和插入件被分阶段地安装在电路板上,但是其他的实施方案也是可以的。可以将本文所讨论的实施方案应用于各种电部件。例如,用于一次安装的利用接合材料接合的电部件可以为半导体器件和封装基板,并且用于二次安装的利用接合材料接合的电部件可以为封装基板和电路板。
(用于制造根据第二实施方案的电子装置的方法)
下面将参照图13至图21描述用于制造根据第二实施方案的电子装置的方法。图13至图21示出了制造根据第二实施方案的电子装置的过程。
如图13所示,例如通过化学镀方法在半导体器件101的表面上形成了主要由Cu构成的Cu电极102。如在第一实施方案中的半导体器件11上的Cu电极12中一样,可以形成阻挡金属膜。在Cu电极102上的阻挡金属膜105可以抑制连接介质151的扩散到Cu电极102中并且提高第一接合部150的连接的可靠性。在下面描述的用于制造根据第二实施方案的电子装置的方法中,为了简洁的目的在附图中省略了在Cu电极102上的阻挡金属膜。
如图14所示,通过化学镀方法在插入件110的表面上形成了主要由Cu构成的Cu电极111。通过化学镀方法在插入件110的另一表面上形成了主要由Cu构成的Cu电极121。如在第一实施方案中的半导体器件11上的Cu电极12中一样,可以形成金属阻挡层。Cu电极111上的阻挡金属膜115可以抑制连接介质151扩散到Cu电极111中并且提高了第一接合部150的连接的可靠性。Cu电极121上的阻挡金属膜125可以抑制连接介质161的扩散到Cu电极121中并且提高了第二接合部160的连接的可靠性。在下面描述的用于制造根据第二实施方案的电子装置的方法中,为了简洁的目的在附图中省略了在Cu电极111和Cu电极121上的阻挡金属膜。
通过化学镀方法或通过电镀方法利用阻挡金属膜作为籽晶层,在Cu电极111上形成由熔点为138℃的Sn-58Bi合金构成的用于一次安装151的连接介质。在用于一次安装151的连接介质是通过电镀方法形成的情况下,在形成用于一次安装151的连接介质之后去除籽晶层。
如图15所示,当在图13中的半导体器件101被倒装芯片接合器(未示出)保持时,半导体器件101的电极102和插入件110的电极111被合适地放置。然后向插入件110施加助焊剂136以将半导体器件101临时地附接至插入件110。
如图16所示,然后在温度不小于Sn-58Bi合金的熔点(138℃)的温度(例如在160℃至180℃范围内)下对由Sn-58Bi合金构成的用于一次安装151的连接介质进行回流以将半导体器件101接合至插入件110。在将半导体器件101和插入件110接合在一起之后,以与在第一实施方案中的方式相同的方式去除助焊剂136,并且向半导体器件101与插入件110之间浇注底部填料130。在半导体器件101与插入件110之间的底部填料130增加了其间的接合强度并且提高了电子装置100的连接的可靠性。因而,完成了一次安装。
如图17所示,利用光学粘合剂(未示出)将光学部件170接合至半导体器件110。通过紫外辐射使光学粘合剂固化来将光学部件170接合至半导体器件110。
如图18所示,通过化学镀方法在电路板120的表面上形成主要由Cu构成的Cu电极131。如在第一实施方案中在半导体器件11上的Cu电极12中一样,可以形成阻挡金属膜。在Cu电极131上的阻挡金属膜135可以抑制连接介质161的扩散到Cu电极131中并且提高了第二接合部160的连接的可靠性。在下面描述的用于制造根据第二实施方案的电子装置的方法中,为了简洁的目的在附图中省略了在Cu电极131上的阻挡金属膜。
在Cu电极131上沉积由In-Sn-Ag构成并且厚度在约10μm至15μm范围内的用于二次安装161的连接介质。由In-Sn-Ag构成的用于二次安装161的连接介质优选包含不小于43重量%并且不大于60重量%的In以及不大于3重量%的Ag。在用于二次安装161的连接介质由含有不小于43重量%并且不大于60重量%的In以及不大于3重量%的Ag的In-Sn-Ag构成的情况下,回流之后连接介质161可以包含与Ag2In相比较多的AgIn2,并且在图12A中的电子装置100的第二接合部160具有高的强度和延展性。
如图19所示,在附图17中的其中半导体器件101和插入件110接合在一起的结构99被倒装芯片接合器(未示出)保持时,结构99的电极121和电路板120的电极131被合适地放置。然后向电路板120施加助焊剂141以将结构99临时地附接至电路板120。
如图20所示,然后在温度不小于用于二次安装161的连接介质的熔点(113℃)的温度(例如在115℃至130℃范围内)下对由包含不小于43重量%并且不大于60重量%的In以及不大于3重量%的Ag的In-Sn-Ag合金构成的用于二次安装161的连接介质进行回流以将结构99接合至电路板120。用于二次安装161的连接介质的熔融温度的上限温度低于在一次安装中使用的用于一次安装151的连接介质的熔点。在一次安装中使用的用于一次安装151的连接介质的熔点以上,用于一次安装151的连接介质再次熔融,导致错误的定位和差的连接的可靠性。
在通过回流将结构99接合至电路板120之后,在第一实施方案中所描述的冷却条件下执行冷却。更具体地,例如在用于二次安装161的连接介质的固相线温度以上的温度下的平均冷却速率优选地不小于1.0℃/s。用于二次安装161的连接介质的固相线温度以下的温度下的平均冷却速率可以为0.4℃/s,其低于用于二次安装161的连接介质的固相线温度以上的温度下的平均冷却速率(小于1.0℃/s)。在这样的冷却条件下的冷却致使在图12A中示出的电子装置100的第二接合部160的AgIn2含量高于Ag2In含量并且致使了第二接合部160的高的强度和延展性。
在图20中所示出的步骤之后,去除助焊剂141并且浇注底部填料140。因而,完成了在图21中所示出的电子装置100。在插入件110与电路板120之间的底部填料140增加了其间的接合强度并且提高了电子装置100的连接的可靠性。前述是用于制造根据第二实施方案的电子装置100的方法。
如上所述,在根据第二实施方案的电子装置100中,电部件之间的接合部由熔点为约113℃并且Ag2In含量低于AgIn2含量的In-Sn-Ag合金构成。因此,可以通过在低的温度下进行回流来将电部件接合在一起。这降低了电部件的翘曲,并且即使在冲击或应力下接合部也具有高的延展性和强度。因而,接合部无缺陷(例如,裂纹),并且电子装置具有高的连接的可靠性。此外,例如在包括具有低的耐热性的部件(例如光学部件)的电部件是分阶段接合的情况下,可以制造具有高的连接可靠性的电子装置而不会热影响光学部件和电部件。
本文所讨论的实施方案不限于这些实施方案并且可以在不脱离实施方案的要点的情况下进行各种改变。
[附图标记列表]
1电子装置,11半导体器件,12电极,13 Ni膜,14 Au膜,15阻挡金属膜,21电极,22电路板,23 Ni膜,24 Au膜,25阻挡金属膜,31接合部,32连接介质,41底部填料,51助焊剂,61倒装芯片接合器,100电子装置,101半导体器件,102电极,103 Ni膜,104 Au膜,105阻挡金属膜,110插入件,111电极,112 Ni膜,113 Au膜,115阻挡金属膜,120电路板,121电极,122 Ni膜,123 Au膜,125阻挡金属膜,130底部填料,131电极,132 Ni膜,133 Au膜,135阻挡金属膜,136助焊剂,140底部填料,141助焊剂,150第一接合部,151用于一次安装的连接介质,160第二接合部,161用于二次安装的连接介质,170光学部件

Claims (20)

1.一种电子装置,包括:
第一电部件;
第二电部件;以及
连接所述第一电部件与所述第二电部件的In-Sn-Ag合金,所述In-Sn-Ag合金包含AgIn2和Ag2In,Ag2In含量低于AgIn2含量。
2.根据权利要求1所述的电子装置,还包括:
设置在所述第一电部件处的第一电极;以及
设置在所述第二电部件处的第二电极,所述In-Sn-Ag合金连接所述第一电极与所述第二电极。
3.根据权利要求1所述的电子装置,其中所述In-Sn-Ag合金包含不小于43重量%并且不大于60重量%的In。
4.根据权利要求1所述的电子装置,其中所述In-Sn-Ag合金包含不大于3重量%的Ag。
5.根据权利要求1所述的电子装置,还包括:
第三电部件;以及
连接所述第二电部件与所述第三电部件的合金,所述合金由与所述In-Sn-Ag合金不同的材料制成。
6.根据权利要求5所述的电子装置,还包括:
设置在所述第三电部件处的第三电极,所述合金连接所述第二电极与所述第三电极。
7.根据权利要求5所述的电子装置,其中所述材料的熔点高于所述In-Sn-Ag合金的熔点。
8.根据权利要求1所述的电子装置,其中所述第一电部件为半导体器件,并且所述第二电部件为电路板。
9.根据权利要求1所述的电子装置,其中所述第一电部件为半导体器件,并且所述第二电部件为封装基板。
10.根据权利要求1所述的电子装置,其中所述第一电部件为半导体器件,并且所述第二电部件为插入件。
11.根据权利要求1所述的电子装置,其中所述第一电部件为封装基板,并且所述第二电部件为电路板。
12.根据权利要求1所述的电子装置,其中所述第一电部件为插入件,并且所述第二电部件为封装基板。
13.根据权利要求9所述的电子装置,还包括:
电路板,以及
连接所述封装基板与所述电路板的合金,所述合金由与所述In-Sn-Ag合金不同的材料制成。
14.根据权利要求10所述的电子装置,还包括:
电路板,以及
连接所述插入件与所述电路板的合金,所述合金由与所述In-Sn-Ag合金不同的材料制成。
15.根据权利要求12所述的电子装置,还包括:
电路板,以及
连接所述封装基板与所述电路板的合金,所述合金由与所述In-Sn-Ag合金不同的材料制成。
16.根据权利要求8所述的电子装置,还包括:
封装基板,以及
连接所述电路板与所述封装基板的合金,所述合金由与所述In-Sn-Ag合金不同的材料制成。
17.根据权利要求10所述的电子装置,还包括:
封装基板,以及
连接所述插入件与所述封装基板的合金,所述合金由与所述In-Sn-Ag合金不同的材料制成。
18.一种制造电子装置的方法,包括:
经由In-Sn-Ag合金连接第一电部件与第二电部件,所述In-Sn-Ag合金包含不小于43重量%并且不大于60重量%的In,所述In-Sn-Ag合金包含不大于3重量%的Ag;
在不低于所述In-Sn-Ag合金的固相线温度的温度下以第一冷却速率对连接所述第一电部件与所述第二电部件的所述In-Sn-Ag合金进行冷却;以及
在不高于所述In-Sn-Ag合金的固相线温度的温度下以第二冷却速率对连接所述第一电部件与所述第二电部件的所述In-Sn-Ag合金进行冷却,所述第二冷却速率低于所述第一冷却速率。
19.根据权利要求18所述的制造电子装置的方法,其中所述第一冷却速率不小于1℃/s。
20.根据权利要求18所述的制造电子装置的方法,其中所述第二冷却速率小于1℃/s。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
WO2012150452A1 (en) * 2011-05-03 2012-11-08 Pilkington Group Limited Glazing with a soldered connector
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6550665B1 (en) * 2001-06-06 2003-04-22 Indigo Systems Corporation Method for electrically interconnecting large contact arrays using eutectic alloy bumping
CN104103626A (zh) * 2013-04-01 2014-10-15 英特尔公司 混合碳-金属互连结构

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61148774A (ja) 1984-12-21 1986-07-07 富士通株式会社 電気的接続装置
JPH067607A (ja) * 1992-04-28 1994-01-18 Asahi Glass Co Ltd 水切り用の溶剤組成物
US5897341A (en) * 1998-07-02 1999-04-27 Fujitsu Limited Diffusion bonded interconnect
JP3866503B2 (ja) 2000-10-18 2007-01-10 株式会社東芝 半導体装置
JP2006000909A (ja) 2004-06-18 2006-01-05 Murata Mfg Co Ltd はんだ材料および該はんだ材料を用いてはんだ付けされた電子部品
US8058675B2 (en) * 2006-12-27 2011-11-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device using the same
JP2008241656A (ja) * 2007-03-29 2008-10-09 Furukawa Electric Co Ltd:The はんだ試験片の作製方法およびはんだ試験片
WO2009011392A1 (ja) 2007-07-18 2009-01-22 Senju Metal Industry Co., Ltd. 車載電子回路用In入り鉛フリーはんだ
US8138610B2 (en) * 2008-02-08 2012-03-20 Qimonda Ag Multi-chip package with interconnected stacked chips
TWI404809B (zh) * 2009-09-23 2013-08-11 Univ Nat Pingtung Sci & Tech 特殊複合合金組成物
JP5724411B2 (ja) * 2011-01-31 2015-05-27 富士通株式会社 はんだ、はんだ付け方法及び半導体装置
US8673761B2 (en) * 2011-02-19 2014-03-18 International Business Machines Corporation Reflow method for lead-free solder
JP2014096198A (ja) * 2011-03-02 2014-05-22 Central Glass Co Ltd 自動車用窓ガラスと給電端子の接合方法
US9603295B2 (en) * 2011-04-04 2017-03-21 Panasonic Intellectual Property Management Co., Ltd. Mounted structure and manufacturing method of mounted structure
US9099396B2 (en) * 2011-11-08 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US9159686B2 (en) * 2012-01-24 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Crack stopper on under-bump metallization layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6550665B1 (en) * 2001-06-06 2003-04-22 Indigo Systems Corporation Method for electrically interconnecting large contact arrays using eutectic alloy bumping
CN104103626A (zh) * 2013-04-01 2014-10-15 英特尔公司 混合碳-金属互连结构

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