TW201625376A - 電子裝置及其製造方法 - Google Patents

電子裝置及其製造方法 Download PDF

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Publication number
TW201625376A
TW201625376A TW104134841A TW104134841A TW201625376A TW 201625376 A TW201625376 A TW 201625376A TW 104134841 A TW104134841 A TW 104134841A TW 104134841 A TW104134841 A TW 104134841A TW 201625376 A TW201625376 A TW 201625376A
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Prior art keywords
alloy
electronic device
electronic component
electronic
electrode
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TW104134841A
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English (en)
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TWI561330B (en
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上村泰紀
清水浩三
作山誠樹
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富士通股份有限公司
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Publication of TW201625376A publication Critical patent/TW201625376A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C28/00—Alloys based on a metal not provided for in groups C22C5/00 - C22C27/00
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C30/00—Alloys containing less than 50% by weight of each constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
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    • C22C30/04—Alloys containing less than 50% by weight of each constituent containing tin or lead
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

一種電子裝置，其係包含：一第一電子組件；一第二電子組件；以及連接該第一電子組件與該第二電子組件的一In-Sn-Ag合金，該In-Sn-Ag合金包含AgIn2與Ag2In，Ag2In含量低於AgIn2含量。

Description

電子裝置及其製造方法
描述於本文的具體實施例係有關於具有用接合材料安裝電子組件於其中的電子裝置以及用於製造電子裝置的方法。
一般而言，由於有高度的加工性及生產力，利用焊接法的安裝方法廣泛用來安裝電子組件(例如，半導體元件)於印刷線路板上。當半導體元件用焊接法裝在印刷線路板上時，高回焊溫度造成半導體元件及印刷線路板翹曲，從而導致電子裝置中之半導體元件與印刷線路板的焊料接合部有不良的機械及電氣連接可靠性。因此，半導體元件用有低熔點的焊料以低回焊溫度焊接至印刷線路板。有低熔點的焊料之一為熔點為117℃的InSn共熔焊料。In-Sn合金焊料有更低的熔點但是強度低於Sn-Bi合金及Sn-Ag-Cu合金焊料。有人提出，一種低熔點焊料含有介金屬化合物(intermetallic compound)以便增加焊料的強度(例如，參考日本早期專利公開案2006-909及2002-124533)。不過，即使用上述焊料來安裝電子組件，例 如，由於對於電子組件之掉落衝擊的抵抗力不足，電子裝置中之電子組件的機械及電氣連接仍有不良的可靠性。
描述於本文的具體實施例的目標是要提供一種其中電子組件有高度可靠性之機械及電氣連接的電子裝置。
根據本發明之一態樣的一種裝置，其係包含：第一電子組件；第二電子組件；以及連接該第一電子組件與該第二電子組件的In-Sn-Ag合金，該In-Sn-Ag合金包含AgIn2與Ag2In，Ag2In含量低於AgIn2含量。
描述於本文的具體實施例提供一種其中電子組件有高度可靠性之機械及電氣連接的電子裝置。
1‧‧‧電子裝置
11‧‧‧半導體元件
12‧‧‧電極
13‧‧‧鎳膜
14‧‧‧金膜
15‧‧‧阻障金屬膜
21‧‧‧電極
22‧‧‧電路板
23‧‧‧鎳膜
24‧‧‧金膜
25‧‧‧阻障金屬膜
31‧‧‧接合部
32‧‧‧連接介質
41‧‧‧底膠
51‧‧‧焊劑
61‧‧‧覆晶接合器
100‧‧‧電子裝置
101‧‧‧半導體元件
102‧‧‧電極
103‧‧‧鎳膜
104‧‧‧金膜
105‧‧‧阻障金屬膜
110‧‧‧中介層
111‧‧‧電極
112‧‧‧鎳膜
113‧‧‧金膜
115‧‧‧阻障金屬膜
120‧‧‧電路板
121‧‧‧電極
122‧‧‧鎳膜
123‧‧‧金膜
125‧‧‧阻障金屬膜
130‧‧‧底膠
131‧‧‧電極
132‧‧‧鎳膜
133‧‧‧金膜
135‧‧‧阻障金屬膜
136‧‧‧焊劑
140‧‧‧底膠
141‧‧‧焊劑
150‧‧‧第一接合部
151‧‧‧用於首次安裝的連接介質
160‧‧‧第二接合部
161‧‧‧用於二次安裝的連接介質
170‧‧‧光學組件
A‧‧‧點線
第1A圖圖示根據第一具體實施例之電子裝置的橫截面圖；第1B圖為第1A圖中被點線A包圍的部份之放大圖；第2圖的曲線圖圖示Ag含量按重量有0%、1%、5%及10%之In-Sn-Ag合金的拉伸試驗結果；第3圖的曲線圖圖示Ag含量按重量有0%、1%、3%及5%之In-Sn-Ag合金的高速剪切強度試驗結果；第4A圖為Ag在接合至銅片之In-Sn-1Ag合金中的元素分布圖； 第4B圖為Ag在接合至銅片之In-Sn-5Ag合金中的元素分布圖；第4C圖為Ag在接合至銅片之In-Sn-10Ag合金中的元素分布圖；第5圖為製造第一具體實施例之電子裝置之方法的橫截面圖(1)；第6A圖為製造第一具體實施例之電子裝置之方法的橫截面圖(2)；第6B圖的放大圖圖示被第6A圖中之點線A包圍的部份；第7圖為製造第一具體實施例之電子裝置之方法的橫截面圖(3)；第8圖為製造第一具體實施例之電子裝置之方法的橫截面圖(4)；第9圖為製造第一具體實施例之電子裝置之方法的橫截面圖(5)；第10圖為製造第一具體實施例之電子裝置之方法的橫截面圖(6)；第11圖圖示在加熱器中進行銅片上之In-Sn-1Ag合金之回焊加熱步驟時以及在回焊加熱步驟後進行冷卻步驟時的溫度變化曲線圖；第12A圖根據第二具體實施例圖示一電子裝置的橫截面圖；第12B圖為第12A圖中被點線A包圍的部 份的放大圖；第12C圖為第12A圖中被點線B包圍的部份的放大圖；第13圖為製造第二具體實施例之電子裝置之方法的橫截面圖(1)；第14圖為製造第二具體實施例之電子裝置之方法的橫截面圖(2)；第15圖為製造第二具體實施例之電子裝置之方法的橫截面圖(3)；第16圖為製造第二具體實施例之電子裝置之方法的橫截面圖(4)；第17圖為製造第二具體實施例之電子裝置之方法的橫截面圖(5)；第18圖為製造第二具體實施例之電子裝置之方法的橫截面圖(6)；第19圖為製造第二具體實施例之電子裝置之方法的橫截面圖(7)；第20圖為製造第二具體實施例之電子裝置之方法的橫截面圖(8)；第21圖為製造第二具體實施例之電子裝置之方法的橫截面圖(9)；第22圖的表格列出In-Sn-1Ag合金、In-Sn-3Ag合金及In-Sn-5Ag合金在回焊後的In、AgIn2及Ag2In含量；以及 第23圖的表格列出In-Sn共熔焊料、In-Sn-1Ag合金、In-Sn-3Ag合金及In-Sn-5Ag合金在回焊後的強度及延展性。
以下用附圖詳述描述本文的具體實施例。
(第一具體實施例)以下將於下方參考第1圖描述根據第一具體實施例的電子裝置的結構。第1A圖及第1B圖為根據第一具體實施例之電子裝置的橫截面圖。
請參考第1A圖，根據第一具體實施例的電子裝置1包含半導體元件11、在半導體元件11的電極12，電路板22，在電路板22上的電極21，接合部31，以及底膠(underfill)41。在電子裝置1中，半導體元件11經由電極12、接合部31及電極21電氣連接至電路板22。半導體元件11與電路板22之間的空間填滿底膠41。
第1B圖的放大圖圖示被第1A圖中之點線A包圍的部份。阻障金屬膜(barrier metal film)15配置於由銅製成的電極12上，電極12配置於半導體元件11的一表面上。阻障金屬膜15依序包含在銅電極12上的鎳膜13及金膜14。阻障金屬膜25配置於由銅製成的電極21上，電極21配置於電路板22的一表面上。阻障金屬膜25依序包含在銅電極21上的鎳膜23及金膜24。銅電極12及銅電極21上的阻障金屬膜15及阻障金屬膜25可抑制連接介質32擴散進入銅電極12及銅電極21，從而改善接合部31的連接可靠性。
接合部31由包含介金屬化合物Ag2In及介金屬化合物AgIn2的In-Sn-Ag合金構成。接合部31的Ag2In含量低於接合部31的AgIn2含量。當Ag2In含量和AgIn2含量滿足此條件時，接合部31有高強度及延展性。接合部31最好包含不小於43且不大於60重量%的In，因為這可進一步提高接合部31的強度。接合部31最好包含3或更少重量%的Ag，因為這可進一步提高接合部31的強度及延展性。
如果接合部31的In含量小於43重量%，接合部31包含數量比均勻分散AgIn2多的長大Ag2In而有不足的延展性。如果接合部31的In含量大於60重量%，接合部31中的金相結構(metallographic structure)不是In相與Sn相的共熔金相結構，以及在In相的金相結構中，Sn在In長大時分解。因此，接合部31有不足的強度。
在接合部31的高強度及延展性方面，接合部31的In含量範圍不小於48且不大於58重量%更佳，不小於50且不大於54重量%特別較佳。
以下實驗檢驗接合部31的接合材料組合物，接合部31中的介金屬化合物，和接合部31的強度及延展性之間的關係。
評估連接可靠性的方法之一為根據國際標準組織ISO 6892-1的金屬材料拉伸試驗。在此評估試驗方法中，接合材料的強度及延展性的測量係藉由對接合材料施加拉伸應變直到接合材料斷裂。強度及延展性用該評估 試驗方法測量。
加熱以下接合材料(1)至(4)至150℃的尖峰溫度，然後冷卻以製備在平行部份之橫截面中有5毫米寬度的拉伸試驗樣品，4毫米的厚度，以及20毫米的量規長度。
(1)In-48Sn共熔焊料
(2)由In-48Sn共熔焊料及1重量%之Ag構成的In-Sn-1Ag合金
(3)由In-48Sn共熔焊料及5重量%之Ag構成的In-Sn-5Ag合金
(4)由In-48Sn共熔焊料及10重量%之Ag構成的In-Sn-10Ag合金
使用INSTRON拉伸試驗機4466以2毫米/分鐘的十字頭速度使該等樣品經受拉伸試驗。第2圖的曲線圖圖示該等樣品的拉伸試驗結果。該拉伸試驗遵循標準ISO 6892-1。在第2圖中，橫軸為接合材料的應變(位移)，以及縱軸為施加至接合材料的負荷。在第2圖的曲線圖中，縱軸上的最大值對應至接合材料的強度。在第2圖的曲線圖中，當施加至接合材料的負荷隨著應變增加而大幅減少時，該接合材料斷裂。在該接合材料斷裂時的應變對應至延展性。
在第2圖中，In-Sn-10Ag合金的負荷在位移約4.6毫米時大幅減少。另一方面，In-48Sn共熔焊料(eutectic solder)、In-Sn-1Ag合金及In-Sn-5Ag合金的負荷 在位移至第2圖之範圍外時大幅減少。
由第2圖的曲線圖發現，In-Sn-10Ag合金在經受拉伸試驗的接合材料中有最高強度以及有極低延展性。相比之下，In-Sn-1Ag合金在經受拉伸試驗的接合材料中有最低強度。也發現，In-Sn-1Ag合金(未圖示)斷裂時的應變大於In-Sn共熔焊料斷裂時的應變且有最高延展性。
評估連接可靠性的另一方法為根據聯合電子設備工程委員會JESD 22-B117A的高速剪切試驗。在此評估試驗方法中，施加機械剪切應力至接合材料以測量該接合材料的強度及延展性。強度及延展性用該評估試驗方法測量。
接下來，藉由以150℃的尖峰溫度回焊配置於直徑有540微米之銅電極上的下列接合材料(5)至(8)來製備高速剪切試驗樣品。在回焊後，該等樣品有600微米的直徑。
(5)In-48Sn共熔焊料
(6)由In-48Sn共熔焊料及1重量%之Ag構成的In-Sn-1Ag合金
(7)由In-48Sn共熔焊料及3重量%之Ag構成的In-Sn-3Ag合金
(8)由In-48Sn共熔焊料及5重量%之Ag構成的In-Sn-5Ag合金
圖示於第22圖的表格列出In-Sn-1Ag合金、In-Sn-3Ag合金及In-Sn-5Ag合金在回焊後的In、AgIn2 及Ag2In含量。該等合金的In、AgIn2及Ag2In含量由In、AgIn2及Ag2In的面積比及比重(specific gravity)算出。在使用電子探針微分析器(electron probe microanalyzer)製備的元素分布圖上測量In、AgIn2及Ag2In的面積比。
用Dage試驗機DAGE SIRIES 4000HS以離電極有100微米的高度並且以3000毫米/s的剪切速度使該等樣品經受高速剪切試驗。第3圖的曲線圖圖示該等樣品的高速剪切試驗結果。該高速剪切試驗遵循標準JESD 22-B117A。在第3圖中，橫軸為接合材料的位移，以及縱軸為施加至該接合材料的負荷。在第3圖的曲線圖中，縱軸上的最大值為接合材料的強度。在施加至該接合材料之負荷減少到最大負荷之一半時的位移對應至該接合材料的延展性。在施加至該接合材料之負荷減少到最大負荷之一半時，該接合材料斷裂。
圖示於第23圖的表格列出In-Sn共熔焊料、In-Sn-1Ag合金、In-Sn-3Ag合金及In-Sn-5Ag合金在回焊後的強度及延展性。由表格2發現，In-Sn-5Ag合金有高於其他接合材料的強度。不過，In-Sn-5Ag合金有低於其他接合材料的延展性。也發現，In-Sn-1Ag合金及In-Sn-3Ag合金有高於無銀InSn共熔焊料的強度及延展性。由於In-Sn-3Ag合金有比In-Sn共熔焊料高一點的延展性，添加3重量%以上的Ag至In-Sn共熔焊料大概會減少In-Sn共熔焊料的延展性。
使用電子探針微分析器得到接合至銅片之 In-Sn-1Ag合金、In-Sn-5Ag合金及In-Sn-10Ag合金中之每一個元素的元素分布圖。第4A圖為Ag在In-Sn-1Ag合金中的元素分布圖。第4B圖為Ag在In-Sn-5Ag合金中的元素分布圖。第4C圖為Ag在In-Sn-10Ag合金中的元素分布圖。在In-Sn-10Ag合金中，AgIn2含量範圍在2至3重量%之間，Ag2In含量範圍在10至13重量%之間，以及In含量等於47重量%。
發現，在In-Sn-1Ag合金中之每一個元素的元素分布圖中，在第4A圖中表示銀的白點大約對應至介金屬化合物AgIn2。各點有約1微米的大小。AgIn2在In-Sn-1Ag合金中大體均勻地散佈。In-Sn-1Ag合金的AgIn2含量範圍在2至4重量%之間。Ag2In約佔0.0001重量%且在每一個元素的元素分布圖中無法清楚識別。
由In-Sn-1Ag合金的元素分布圖發現，In-Sn-1Ag合金含有均勻分散的AgIn2。基於第2圖的拉伸試驗結果，In-Sn-1Ag合金有高於InSn共熔焊料的延展性。由測量結果看來，AgIn2有助於In-Sn-Ag合金的延展性。
發現，儘管基於第2圖的拉伸試驗結果，In-Sn-1Ag合金有比InSn共熔焊料低一點的強度，然而基於第3圖的高速剪切試驗結果，In-Sn-1Ag合金有高於InSn共熔焊料的強度。儘管接合材料本身強度的測量在拉伸試驗中隨著接合材料的拉伸應變而改變，然而接合至銅片之接合材料的剪切強度是在高速剪切試驗中測量。假設In-Sn-Ag合金在高速剪切試驗中與銅片中的銅形成介金屬 化合物層從而有高強度。高速剪切試驗結果表明接合至電子組件之接合材料的強度以及表明In-Sn-1Ag合金與電子組件的接合部有高強度及延展性。銅不是可在金屬與In-Sn-Ag合金接合材料的介面形成介金屬化合物層從而有高強度的唯一金屬。In-Sn-Ag合金也可在In-Sn-Ag合金與用作電極材料的金屬(例如鎳或金)之間的介面形成介金屬化合物層，從而有高強度。甚至在拉伸試驗有低強度，在高速剪切試驗有高強度的接合材料在電子裝置中很少有實際問題。
在第4B圖及第4C圖中，大小約在10微米至50微米之間的白色區域為介金屬化合物Ag2In，以及大小約1微米的白色區域為介金屬化合物AgIn2。不像AgIn2在In-Sn-Ag合金中均勻分散，Ag2In在In-Sn-Ag合金中會長大。在第4B圖及第4C圖中，由於長大的Ag2In佔據比AgIn2大的面積，In-Sn-5Ag合金與In-Sn-10Ag合金中之每一者的Ag2In含量高於對應AgIn2含量。在表格1中，In-Sn-5Ag合金的AgIn2含量範圍在2至3重量%之間，以及Ag2In含量範圍在3.5至4.5重量%之間。
由In-Sn-10Ag合金的元素分布圖發現，In-Sn-10Ag合金包含均勻分散的AgIn2及長大的Ag2In。基於第2圖的拉伸試驗結果，In-Sn-10Ag合金有較高的強度但是延展性遠低於InSn共熔焊料。
比較第4A圖與第4C圖，儘管In-Sn-1Ag合金與In-Sn-10Ag合金兩者含有AgIn2，然而In-Sn-10Ag合 金與In-Sn-1Ag合金不同的地方在於In-Sn-10Ag合金含有長大的Ag2In。因此，吾等認為In-Sn-10Ag合金有高強度但是延展性低的原因是長大的Ag2In。
In-Sn-1Ag合金與In-Sn-3Ag合金為其中Ag2In含量低於AgIn2含量的In-Sn-Ag合金。In-Sn-Ag合金中Ag2In含量高於AgIn2含量造成接合部31有極低延展性以及電子裝置1的機械及電氣連接有不良的可靠性。
在長大Ag2In含量高於AgIn2含量時，由於Ag2In晶粒大於AgIn2晶粒，In-Sn-Ag合金的變形容易造成應力集中在Ag2In晶界(grain boundary)以及造成In-Sn-Ag合金斷裂。因此，含有長大Ag2In的In-Sn-Ag合金傾向有低延展性。另一方面，強度增加到以致於阻止變形的程度。由於In-Sn合金的低熔點，較大的介金屬化合物晶粒，例如長大的Ag2In，更有可能阻止變形。因此，含有長大Ag2In的In-Sn-Ag合金有高強度。
當接合部31由含有AgIn2及不含Ag2In的In-Sn-Ag合金構成時，接合部31有低強度，以及電子裝置1有不足的連接可靠性。
在含有均勻分散AgIn2及不含Ag2In的In-Sn-Ag合金中，均勻分散的AgIn2晶粒由於均勻分散因此可緩解應力面可抑制斷裂。因此，含有均勻分散AgIn2的In-Sn-Ag合金有高延展性。另一方面，小晶粒，例如均勻分散AgIn2，有短晶界。短晶界容易造成由晶界滑動引起的變形。儘管由晶界滑動引起的變形一般發生在高溫，然 而由於In-Sn合金有低熔點，由晶界滑動引起的變形會發生。因此，含有均勻分散AgIn2的In-Sn-Ag合金有低強度。
儘管根據第一具體實施例的電子裝置1包含數個阻障金屬膜，然而可省略該等阻障金屬膜。在沒有阻障金屬膜下，接合部可直接配置於銅電極上。儘管在本具體實施例中，該半導體元件裝在電路板上，其他的具體實施例也有可能。例如，在其他具體實施例中，本具體實施例的接合部可應用於各種電子組件的接合部，例如半導體元件與中介層，或中介層與電路板。
(用於製造根據第一具體實施例之電子裝置的方法)
以下參考第5圖至第10圖描述用於製造根據第一具體實施例之電子裝置的方法。第5圖至第10圖圖示製造第一具體實施例之電子裝置的方法。
如第5圖所示，例如，由銅構成的銅電極12用無電電鍍法形成半導體元件11的表面上。阻障金屬膜15形成於銅電極12上。例如，阻障金屬膜15由鎳膜13及金膜14構成。鎳膜13用無電電鍍法形成且有約5微米的厚度。金膜14用無電電鍍法形成於鎳膜13上且有約0.1微米至0.3微米的厚度。阻障金屬膜15可抑制連接介質32擴散進入銅電極12，從而改善接合部31的連接可靠性。
由第6A圖所示，主要由銅構成的銅電極21用無電電鍍法形成於電路板22的表面上。第6B圖的放大 圖圖示被第6A圖中之點線A包圍的部份。阻障金屬膜25形成於在電路板22表面上主要由銅構成的銅電極21上。例如，阻障金屬膜25由鎳膜23及金膜24構成。鎳膜23用無電電鍍法形成且有約5微米的厚度。金膜24用無電電鍍法形成於鎳膜23上且有約0.1至0.3微米的厚度。阻障金屬膜25可抑制連接介質32擴散進入銅電極21，從而改善接合部31的連接可靠性。
在阻障金屬膜25形成後，由In-Sn-Ag合金構成且有約10微米至15微米之厚度的連接介質32沉積於阻障金屬膜25上。由In-Sn-Ag合金構成的連接介質32最好包含不小於43且不大於60重量%的In以及不小於1且不大於3重量%的Ag。當由In-Sn-Ag合金構成的連接介質32包含不小於43且不大於60重量%的In以及不小於1且不大於3重量%的Ag時，回焊之後的連接介質32可能包含比Ag2In還多的AgIn2，以及第1A圖之電子裝置1的接合部31有高強度及延展性。在下述用於製造第一具體實施例之電子裝置的方法中，為了簡化附圖省略阻障金屬膜15與阻障金屬膜25。
如第7圖所示，焊劑51施加至電路板22。製備圖示於第5圖的半導體元件11。在半導體元件11用覆晶接合器(flip chip bonder)61固持時，半導體元件11的電極12與電路板22的電極21被適當地定位。
如第8圖所示，用覆晶接合器61固持的半導體元件11隨後利用焊劑51的膠黏性(tackiness)暫時附接 至電路板22。如本文所使用的用語膠黏性係指待接合組件利用黏性(stickiness)保持位置關係的性質。
如第9圖所示，由包含不小於43且不大於60重量%之In且不大於3重量%之Ag的In-Sn-Ag合金構成的連接介質32隨後加熱到不小於連接介質32之熔點的溫度，亦即，113℃或更多。不過，過高的溫度造成電子組件的翹曲增加以及較低的連接可靠性。因此，連接介質32最好加熱到在例如115℃至150℃之間的溫度和熔化，藉此使半導體元件11接合至電路板22。
如上述，在以高於In-Sn-Ag合金之固相溫度(solidus temperature)的溫度冷卻期間，從熔融狀態的In-Sn-Ag合金結晶出Ag2In。當結晶Ag2In在熔融In-Sn-Ag合金中遷移時，結晶Ag2In與另一結晶Ag2In結合而長大。長大的Ag2In為低延展性的原因。在以低於In-Sn-Ag合金之固相溫度的溫度冷卻期間，介金屬化合物AgIn2從固態的In-Sn-Ag合金析出。析出的AgIn2在固體In-Sn-Ag合金中不遷移且維持均勻分散的狀態。由第4A圖之In-Sn-1Ag合金的元素分布圖以及第3圖的高速剪切試驗結果發現，包含均勻分散AgIn2的In-Sn-Ag合金有高強度及延展性。
第11圖為使用回焊裝置回焊In-Sn-1Ag合金於銅片上的溫度曲線圖。第4A圖圖示用遵循第11圖之溫度曲線圖的回焊製備的樣品之橫截面的元素分布圖。
在第11圖中，橫軸為時間(秒)，以及縱軸為溫度(℃)。In-Sn-1Ag合金有約113℃的固相溫度。在第 11圖中，S1表示高於固相溫度的溫度範圍，以及S2表示低於固相溫度的溫度範圍。在第11圖中，In-Sn-1Ag合金在溫度範圍S1內處於熔融狀態，以及In-Sn-1Ag合金在溫度範圍S2內處於固態。
AgIn2在S2中析出。在溫度範圍S2內的冷卻步驟中，當回焊裝置的內部溫度大約小於50℃時，AgIn2的析出不充分。因此，回焊裝置的冷卻控制下降到約50℃。當回焊裝置的內部溫度在溫度範圍S2內且大於50℃時，由回焊裝置取出銅片上的In-Sn-1Ag合金會快速冷卻，以及可減少AgIn2的析出。
在回焊加熱步驟開始後約190秒，回焊裝置的內部溫度到達在溫度範圍S1內的約122℃，以及In-Sn-1Ag合金處於熔融狀態。在In-Sn-1Ag合金加熱及融化後，停止回焊裝置的加熱，或減少加熱溫度。回焊裝置的內部溫度降到在溫度範圍S2內的溫度，藉此冷卻及凝固In-Sn-1Ag合金。在回焊裝置的內部溫度到達約50℃後，銅片上的In-Sn-1Ag合金由回焊裝置取出且讓它自然冷卻。
如第11圖所示，In-Sn-1Ag合金在溫度範圍S1內之冷卻步驟的平均冷卻速率高於In-Sn-1Ag合金在溫度範圍S2內之冷卻步驟的平均冷卻速率。可控制冷卻步驟在回焊裝置中的冷卻速率使得In-Sn-1Ag合金的AgIn2含量高於In-Sn-1Ag合金的Ag2In含量。In-Sn-1Ag合金在溫度範圍S1內之冷卻步驟的平均冷卻速率最好不小於1.0℃/s以便減少In-Sn-1Ag合金的Ag2In含量。In-Sn-1Ag合金在 溫度範圍S2內之冷卻步驟的平均冷卻速率最好為低於在溫度範圍S1內之平均冷卻速率(1.0℃/s)的0.4℃/s，以便增加In-Sn-1Ag合金的AgIn2含量。
基於得自第11圖In-Sn-1Ag合金在銅片上之溫度曲線圖的實驗結果，在連接介質32固相溫度以上之冷卻步驟的平均冷卻速率大於在連接介質32固相溫度以下之冷卻步驟的平均冷卻速率。在這些冷卻條件下的冷卻造成第1A圖電子裝置1之接合部31的AgIn2含量高於Ag2In含量以及有高強度及延展性的接合部31。
在圖示於第9圖的步驟之後，移除焊劑51的殘留物。例如，藉由以約70℃將第9圖的結構浸入二甲苯與異丙醇的混合有機溶劑一小時，可移除焊劑51的殘留物。然後，乾燥已移除焊劑51殘留物的第9圖結構，例如，以120℃持續2小時且填滿底膠41，從而完成圖示於第10圖的電子裝置1。在半導體元件11、電路板22之間的底膠41增加其間的接合強度以及改善電子裝置1的連接可靠性。以上為用於製造根據第一具體實施例之電子裝置的方法。
如上述，在根據第一具體實施例的電子裝置1中，在電子組件之間的接合部係由熔點約為113℃且Ag2In含量低於AgIn2含量的In-Sn-Ag合金構成。因此，可用低溫度的回焊將電子組件接合在一起。這減少電子組件的翹曲，以及接合部有高延展性及強度，甚至在衝擊或應力下。因此，接合部沒有缺陷，例如裂縫，而且電子裝置 有高度的連接可靠性。
(第二具體實施例)本具體實施例係有關於一種電子裝置，其中電子組件係分階段安裝。
以下描述根據第二具體實施例之電子裝置的結構。第12A圖為根據第二具體實施例之電子裝置的橫截面圖。
請參考第12A圖，電子裝置100包含半導體元件101，半導體元件101上的電極102，中介層110，中介層110上的電極111及電極121，電路板120，電路板120上的電極131，第一接合部150，第二接合部160，底膠130，以及底膠140。在電子裝置100中，半導體元件101經由第一接合部150電氣連接至中介層110。在半導體元件101、中介層110之間的空間填滿底膠130。中介層110經由第二接合部160電氣連接至電路板120。在中介層110、電路板120之間的空間填滿底膠140。光學組件170耦合至半導體元件101。以下詳述電子裝置100的結構。
第12B圖的放大圖圖示被第12A圖中之點線A包圍的部份。第12C圖的放大圖圖示被第12A圖中之點線B包圍的部份。首先，以下描述被點線A包圍之部份的放大圖。阻障金屬膜105配置於由銅製成的電極102中之每一者上，電極102配置於半導體元件101的表面上。阻障金屬膜105依序包含在銅電極102上的鎳膜103及金膜104。阻障金屬膜115配置於由銅製成的電極111中之每一者上，電極111配置於中介層110的表面上。阻障金 屬膜115依序包含在銅電極111上的鎳膜112及金膜113。
以下描述被點線B包圍之部份的放大圖。阻障金屬膜125配置於由銅製成的電極121中之每一者上，電極121配置於中介層110的表面上。阻障金屬膜125依序包含在銅電極121上的鎳膜122及金膜123。阻障金屬膜135配置於由銅製成的電極131中之每一者上，電極131配置於電路板120的表面上。阻障金屬膜135依序包含在銅電極131上的鎳膜132及金膜133。
在銅電極102及銅電極111上的阻障金屬膜105及阻障金屬膜115可抑制連接介質151擴散進入銅電極102及銅電極111，從而改善第一接合部150的連接可靠性。
在銅電極121及銅電極131上的阻障金屬膜125及阻障金屬膜135可抑制連接介質161擴散進入銅電極121及銅電極131，從而改善第二接合部160的連接可靠性。
半導體元件101經由第一接合部150電氣連接至中介層110。例如，第一接合部150由熔點為138℃的Sn-58Bi合金，熔點為227℃的Sn-0.7Cu合金，熔點為217℃的Sn-3Ag-0.5Cu合金，或熔點為221℃的Sn-3.5Ag合金構成。
電路板120經由第二接合部160電氣連接至中介層110。第二接合部160有約113℃的熔點且由Ag2In含量低於AgIn2含量的In-Sn-Ag合金構成。
由於根據第二具體實施例之電子裝置100的第二接合部由Ag2In含量低於AgIn2含量的In-Sn-Ag合金構成，電子裝置100有高強度及延展性。儘管光學組件170很容易受熱，然而由Ag2In含量低於AgIn2含量之In-Sn-Ag合金構成的第二接合部160允許低溫安裝，因此可改善光學組件170的連接可靠性。
儘管根據第二具體實施例的電子裝置100包含阻障金屬膜，然而可省略阻障金屬膜。接合部在沒有阻障金屬膜下可直接配置於銅電極上。儘管半導體元件及中介層在本具體實施例是分階段裝在電路板上，然而其他的具體實施例也有可能。描述於本文的具體實施例可應用於各種電子組件。例如，與用於首次安裝之接合材料接合的電子組件可為半導體元件及封裝基板，以及與用於二次安裝之接合材料接合的電子組件可為封裝基板及電路板。
(用於製造根據第二具體實施例之電子裝置的方法)
以下參考第13圖至第21圖描述用於製造根據第二具體實施例之電子裝置的方法。第13圖至第21圖圖示用於製造根據第二具體實施例之電子裝置的方法。
如第13圖所示，例如，主要由銅構成的銅電極102用無電電鍍法形成於半導體元件101的表面上。如同第一具體實施例，在半導體元件11的銅電極12上可形成阻障金屬膜。銅電極102上的阻障金屬膜105可抑制連接介質151擴散進入銅電極102以及改善第一接合部150 的連接可靠性。在下述用於製造根據第二具體實施例之電子裝置的方法中，為求簡化附圖省略在銅電極102上的阻障金屬膜。
如第14圖所示，主要由銅構成的銅電極111用無電電鍍法形成於中介層110的表面上。主要由銅構成的銅電極121用無電電鍍法形成於中介層110的另一表面上。如同第一具體實施例，在半導體元件11的銅電極12上可形成阻障金屬膜。銅電極111上的阻障金屬膜115可抑制連接介質151擴散進入銅電極111以及改善第一接合部150的連接可靠性。銅電極121上的阻障金屬膜125可抑制連接介質161擴散進入銅電極121以及改善第二接合部160的連接可靠性。在下述用於製造根據第二具體實施例之電子裝置的方法中，為求簡化附圖省略在銅電極111及銅電極121上的阻障金屬膜。
用無電電鍍法或用電鍍法使用阻障金屬膜成為種子層，形成用於首次安裝151由熔點為138℃之Sn-58Bi合金構成的連接介質於銅電極111上。在用於首次安裝151之連接介質用電鍍法形成的情形下，在用於首次安裝151之連接介質形成後，移除種子層。
如第15圖所示，在第13圖的半導體元件101用覆晶接合器(未圖示)固持時，半導體元件101的電極102與中介層110的電極111被適當地定位。然後，焊劑136施加至中介層110以使半導體元件101暫時附接至中介層110。
如第16圖所示，然後以不小於Sn-58Bi合金之熔點(138℃)的溫度回焊用於首次安裝151由Sn-58Bi合金構成的連接介質，例如，在160℃至180℃之間，以使半導體元件101接合至中介層110。在半導體元件101與中介層110接合在一起後，用與第一具體實施例一樣的方式，移除焊劑136，以及澆注底膠130於其間。在半導體元件101、中介層110之間的底膠130增加其間的接合強度以及改善電子裝置100的連接可靠性。於是，完成首次安裝。
如第17圖所示，光學組件170用光學黏著劑(未圖示)接合至半導體元件110。藉由用超紫外線照射法固化光學黏著劑使光學組件170接合至半導體元件110。
如第18圖所示，主要由銅構成的銅電極131用無電電鍍法形成於電路板120的表面上。如同第一具體實施例，在半導體元件11的銅電極12上可形成阻障金屬膜。在銅電極131上的阻障金屬膜135可抑制連接介質161擴散進入銅電極131以及改善第二接合部160的連接可靠性。在下述用於製造根據第二具體實施例之電子裝置的方法中，為求簡化附圖省略在銅電極131上的阻障金屬膜。
用於二次安裝161由In-Sn-Ag構成且厚度有約10至15微米之間的連接介質沉積於銅電極131上。用於二次安裝161由In-Sn-Ag構成的連接介質最好包含不小於43且不大於60重量%的In且不大於3重量%的Ag。當用於二次安裝161由In-Sn-Ag構成的連接介質包含不小 於43且不大於60重量%的In且不大於3重量%的Ag時，回焊後的連接介質161可能包含比Ag2In還多的AgIn2，以及第12A圖之電子裝置100的第二接合部160有高強度及延展性。
如第19圖所示，在其中半導體元件101與中介層110接合在一起的第17圖中的結構99用覆晶接合器(未圖示)固持時，結構99的電極121與電路板120的電極131被適當地定位。然後，焊劑141施加至電路板120以使結構99暫時附接至電路板120。
如第20圖所示，用於二次安裝161由包含不小於43且不大於60重量%之In且不大於3重量%之Ag的In-Sn-Ag合金構成的連接介質隨後以不小於用於二次安裝161之連接介質之熔點(113℃)的溫度回焊，例如，在115℃至130℃之間以使結構99接合至電路板120。用於二次安裝161之連接介質的熔化溫度的上限溫度低於使用於首次安裝之用於首次安裝151之連接介質的熔點。在使用於首次安裝之用於首次安裝151之連接介質的熔點以上，用於首次安裝151之連接介質會再度熔化，導致定位錯誤以及不良的連接可靠性。
在結構99用回焊接合至電路板120後，在描述於第一具體實施例的冷卻條件下進行冷卻。更具體的是，溫度在用於二次安裝161之連接介質的固相溫度以上時的平均冷卻速率最好不小於，例如1.0℃/s。溫度在用於二次安裝161之連接介質的固相溫度以下時的平均冷卻速 率可為0.4℃/s，這低於溫度在用於二次安裝161之連接介質的固相溫度之上的冷卻速率(小於1.0℃/s)。在這些冷卻條件下的冷卻造成第11A圖電子裝置100之第二接合部160的AgIn2含量高於Ag2In含量以及有高強度及延展性的第二接合部160。
在圖示於第20圖的步驟之後，移除焊劑141，以及澆注底膠140。於是，完成圖示於第21圖的電子裝置100。在中介層110、電路板120之間的底膠140增加其間的接合強度以及改善電子裝置100的連接可靠性。上述為用於製造根據第二具體實施例之電子裝置100的方法。
如上述，在根據第二具體實施例的電子裝置100中，在電子組件之間的接合部係由熔點約113℃且Ag2In含量低於AgIn2含量的In-Sn-Ag合金構成。因此，可用低溫度的回焊將電子組件接合在一起。這減少電子組件的翹曲，以及接合部有高延展性及強度，甚至在衝擊或應力下。因此，接合部沒有缺陷，例如裂縫，以及電子裝置有高度的連接可靠性。此外，例如，當分階段接合包含耐熱性低之組件的電子組件(例如，光學組件)時，可製造有高度連接可靠性的電子裝置而對光學組件及電子組件沒有熱影響。
描述於本文的具體實施例沒有限制性且可以不同方式改變而不脫離該等具體實施例的要旨。
1‧‧‧電子裝置
11‧‧‧半導體元件
12‧‧‧電極
13‧‧‧鎳膜
14‧‧‧金膜
15‧‧‧阻障金屬膜
21‧‧‧電極
22‧‧‧電路板
23‧‧‧鎳膜
24‧‧‧金膜
25‧‧‧阻障金屬膜
31‧‧‧接合部
41‧‧‧底膠
A‧‧‧點線

Claims (20)

  1. 一種電子裝置，其係包含：第一電子組件；第二電子組件；以及In-Sn-Ag合金，其連接該第一電子組件與該第二電子組件，該In-Sn-Ag合金包含AgIn2與Ag2In，Ag2In含量低於AgIn2含量。
  2. 如申請專利範圍第1項所述之電子裝置，其更包含：第一電極，其設在該第一電子組件；以及第二電極，其設在該第二電子組件，該In-Sn-Ag合金連接該第一電極與該第二電極。
  3. 如申請專利範圍第1項所述之電子裝置，其中該In-Sn-Ag合金包含不小於43重量%且不大於60重量%的In。
  4. 如申請專利範圍第1項所述之電子裝置，其中該In-Sn-Ag合金包含不大於3重量%的Ag。
  5. 如申請專利範圍第1項所述之電子裝置，其更包含：第三電子組件；以及合金，其連接該第二電子組件與該第三電子組件的，該合金由不同於該In-Sn-Ag合金的材料製成。
  6. 如申請專利範圍第5項所述之電子裝置，其更包含：第三電極，其設在該第三電子組件，該合金連接該第二電極與該第三電極。
  7. 如申請專利範圍第5項所述之電子裝置， 其中該材料的熔點高於該In-Sn-Ag合金的熔點。
  8. 如申請專利範圍第1項所述之電子裝置，其中該第一電子組件為半導體元件，而該第二電子組件為電路板。
  9. 如申請專利範圍第1項所述之電子裝置，其中該第一電子組件為半導體元件，而該第二電子組件為封裝基板。
  10. 如申請專利範圍第1項所述之電子裝置，其中該第一電子組件為半導體元件，而該第二電子組件為中介層。
  11. 如申請專利範圍第1項所述之電子裝置，其中該第一電子組件為封裝基板，而該第二電子組件為電路板。
  12. 如申請專利範圍第1項所述之電子裝置，其中該第一電子組件為中介層，而該第二電子組件為封裝基板。
  13. 如申請專利範圍第9項所述之電子裝置，其中該第三電子組件為電路板。
  14. 如申請專利範圍第10項所述之電子裝置，其中該第三電子組件為電路板。
  15. 如申請專利範圍第12項所述之電子裝置，其中該第三電子組件為電路板。
  16. 如申請專利範圍第8項所述之電子裝置，其中該第三電子組件為封裝基板。
  17. 如申請專利範圍第10項所述之電子裝置，其中該第三電子組件為封裝基板。
  18. 一種製造電子裝置的方法，其係包含下列步驟：經由In-Sn-Ag合金來連接第一電子組件與第二電子組件，該In-Sn-Ag合金包含不小於43重量%且不大於60重量%的In，該In-Sn-Ag合金包含不大於3重量%的Ag；用不小於該In-Sn-Ag合金之固相溫度的溫度，以第一冷卻速率冷卻連接該第一電子組件與該第二電子組件的該In-Sn-Ag合金；以及用不大於該In-Sn-Ag合金之固相溫度的溫度，以第二冷卻速率冷卻連接該第一電子組件與該第二電子組件的該In-Sn-Ag合金，該第二冷卻速率低於該第一冷卻速率。
  19. 如申請專利範圍第18項所述之製造電子裝置的方法，其中該第一冷卻速率不小於1℃/s。
  20. 如申請專利範圍第18項所述之製造電子裝置的方法，其中該第二冷卻速率小於1℃/s。
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