CN108475678B - 自对准到具有侧壁电介质的场释放氧化物的漂移区注入 - Google Patents

自对准到具有侧壁电介质的场释放氧化物的漂移区注入 Download PDF

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CN108475678B
CN108475678B CN201780007246.3A CN201780007246A CN108475678B CN 108475678 B CN108475678 B CN 108475678B CN 201780007246 A CN201780007246 A CN 201780007246A CN 108475678 B CN108475678 B CN 108475678B
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oxide
region
layer
field
doped region
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CN108475678A (zh
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H·L·爱德华兹
B·胡
J·R·托德
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Texas Instruments Inc
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Texas Instruments Inc
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
CN201780007246.3A 2016-01-21 2017-01-23 自对准到具有侧壁电介质的场释放氧化物的漂移区注入 Active CN108475678B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/003,776 US9583612B1 (en) 2016-01-21 2016-01-21 Drift region implant self-aligned to field relief oxide with sidewall dielectric
US15/003,776 2016-01-21
PCT/US2017/014581 WO2017127813A1 (en) 2016-01-21 2017-01-23 Drift region implant self-aligned to field relief oxide with sidewall dielectric

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CN108475678A CN108475678A (zh) 2018-08-31
CN108475678B true CN108475678B (zh) 2023-08-15

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US (4) US9583612B1 (OSRAM)
EP (1) EP3430647A4 (OSRAM)
JP (2) JP7089144B2 (OSRAM)
CN (1) CN108475678B (OSRAM)
WO (1) WO2017127813A1 (OSRAM)

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US10424647B2 (en) 2017-10-19 2019-09-24 Texas Instruments Incorporated Transistors having gates with a lift-up region
US10566200B2 (en) * 2018-04-03 2020-02-18 Texas Instruments Incorporated Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings
US11152505B2 (en) * 2018-06-28 2021-10-19 Texas Instruments Incorporated Drain extended transistor
US10707296B2 (en) 2018-10-10 2020-07-07 Texas Instruments Incorporated LOCOS with sidewall spacer for different capacitance density capacitors
US10529812B1 (en) 2018-10-10 2020-01-07 Texas Instruments Incorporated Locos with sidewall spacer for transistors and other devices
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