CN108430911B - 具有减小的寄生效应的纳米线晶体管和用于制作这种晶体管的方法 - Google Patents

具有减小的寄生效应的纳米线晶体管和用于制作这种晶体管的方法 Download PDF

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CN108430911B
CN108430911B CN201680076411.6A CN201680076411A CN108430911B CN 108430911 B CN108430911 B CN 108430911B CN 201680076411 A CN201680076411 A CN 201680076411A CN 108430911 B CN108430911 B CN 108430911B
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layer
semiconductor
nanowire
metal gate
gate
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CN108430911A (zh
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M·巴达洛格鲁
V·麦考森
S·S·宋
J·J·徐
M·M·诺瓦克
C·F·耶普
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Qualcomm Inc
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Abstract

提供了一种纳米线(130)晶体管，其包括具有用于使替代金属栅极(405)与寄生沟道绝缘的局部隔离区域(120)的阱注入以及在延伸区域中的氧化帽，其抑制寄生的栅极到源极和栅极到漏极电容。用于制作器件的方法包括形成交替的选择性可蚀刻的层(例如，Si和SiGe)的鳍；用蚀刻停止掺杂剂(碳)来掺杂这些层的(源极/漏极)延伸区域；执行针对一种材料的选择性蚀刻；以及选择性氧化对应于牺牲层的延伸区域(215)，由此形成氧化帽(125)。

Description

具有减小的寄生效应的纳米线晶体管和用于制作这种晶体管 的方法
相关申请的交叉引用
本申请要求2015年12月28日提交的美国专利申请No.14/980,850的权益。
技术领域
本申请涉及晶体管器件，并且更具体地涉及具有减小的寄生电容和沟道效应的纳米线器件。
背景技术
在先进的工艺节点中，传统的平面晶体管架构遭受诸如过度泄漏的许多问题。结果，在这些先进的节点中通常使用诸如鳍场效应晶体管(finFET)工艺的三维架构。finFET器件中的“鳍”包括半导体衬底上的三维条。因此鳍具有邻接衬底表面的下表面和在衬底表面上方伸出的三个其余表面。然后，将栅极沉积在鳍之上，使得栅极与鳍的这三个其余表面直接相邻。与之相对，在传统的平面结构中，栅极仅与沟道的一个表面直接相邻。因此，在finFET器件中可以更有效地切断沟道，从而减少漏电流并使先进的工艺节点成为可能。
尽管finFET因此是有利的，但是栅极不能直接控制邻近衬底表面的鳍表面。为了提供更好的栅极控制，已经开发了环绕栅极架构，其中鳍被转变成从衬底表面悬置的一个或多个纳米线。因此，可以将环绕栅极器件表示为纳米线器件或晶体管。为了开始形成纳米线晶体管，在半导体衬底中形成阱注入(well implant)。然后，晶圆厂在阱注入上交替沉积Si和SiGe层。然后蚀刻这些交替层以形成鳍。然后，晶圆厂在鳍周围沉积浅沟槽隔离氧化物填充物，接着形成伪栅极。在伪栅极形成之后，晶圆厂执行延伸注入、间隔物沉积、源极/漏极外延(epi)生长、结注入、层间电介质(ILD0)填充，然后去除伪栅极。随着伪栅极的去除，然后可以通过选择性地蚀刻鳍中的Si层或者选择性地蚀刻SiGe层来形成纳米线。如果SiGe层被去除，则所得到的纳米线是硅。相反，如果硅层被选择性地蚀刻，则纳米线是SiGe。然后可以在纳米线周围沉积栅极结构。
尽管得到的纳米线器件比可比的finFET器件具有更好的栅极控制，但是在栅极沉积之前穿过间隔物之间的窗口的硅锗(或硅)层的选择性蚀刻在间隔物之下产生底切。鉴于SiGe或Si层的底切，随后的栅极到源极和栅极到漏极寄生电容相对较高。此外，栅极下方的阱注入中的底部寄生沟道不能被很好地控制，因为不存在用于该底部寄生沟道的环绕栅极接触。因此，会导致不希望的泄漏电流。另外，在栅极和底部寄生沟道之间存在不希望有的寄生电容。
因此，本领域需要具有减小的寄生电容和减小的寄生沟道效应的改进的纳米线器件架构。
发明内容
为了提供纳米线器件中的寄生电容的改善的减小，局部隔离区域形成在阱注入中，其在替代金属栅极被充电时抑制寄生沟道的形成。另外，纳米线器件中的延伸区域被注入有抑制延伸区域中的第一半导体层的选择性蚀刻的蚀刻停止掺杂剂。蚀刻停止掺杂剂还使得延伸区域中的第一半导体层容易受到选择性氧化的影响，选择性氧化形成氧化帽以使替代金属栅极与漏极和源极区域绝缘。
附图说明
图1A示出了根据本公开的一个方面的纳米线晶体管的纵向截面。
图1B是沿虚线A:A截取的图1A的纳米线晶体管的横向截面。
图2是在选择性蚀刻过程之前的一对鳍的横向截面。
图3是在形成伪栅极、间隔物和延伸区域之后图2中的一个鳍的纵向截面。
图4是在选择性蚀刻工艺和在延伸区域中形成氧化帽之后的图3的鳍的纵向截面。
图5是在选择性蚀刻工艺之后图2的鳍的横向截面。
图6是根据本公开的一个方面的制造方法的流程图。
通过参考下面的详细描述可以最好地理解本公开的实施例及其优点。应该理解的是，相似的附图标记用于标识在一个或多个附图中示出的相似元件。
具体实施方式
为了避免选择性蚀刻纳米线期间的底切，公开了一种延伸注入，其通过注入蚀刻停止掺杂剂而使得延伸区域抵抗选择性蚀刻。蚀刻停止掺杂剂的相同延伸注入使得延伸区域在形成替代金属栅极之前易受选择性氧化的影响。因此，由于氧化层的较低k值以及减少的将栅极与源极/漏极区域隔开的底切，所得到的栅极到源极和栅极到漏极的寄生电容相对较低。另外，在鳍中沉积外延层之前，可以通过氧注入在阱注入中形成局部隔离区域，以便在替代金属栅极和形成在阱注入中的任何寄生沟道之间提供减小的寄生电容。
示例纳米线晶体管100在图1A中沿着鳍105的纵向轴线的横截面图中示出。如本文将进一步讨论的，鳍105包括交替的第一半导体层和第二半导体层。例如，第一半导体层可以包括硅(Si)层，并且第二半导体层可以包括硅锗(SiGe)层。取决于在制造纳米线晶体管100期间是否选择性地蚀刻第一半导体层或第二半导体层，纳米线130可以来自第一半导体层或第二半导体层。选择性蚀刻工艺仅选择性地蚀刻第一半导体层或第二半导体层以形成纳米线130。如本文所使用的，被选择性蚀刻的半导体层也将被称为选择性蚀刻半导体层，而其余半导体层在本文将被表示为纳米线层。例如，在Si纳米线实施例中，硅层将是纳米线层，而SiGe层将是选择性蚀刻层。相反，在SiGe纳米线实施例中，SiGe层将是纳米线层，而Si层将是选择性蚀刻层。
包括金属栅极填充物145的替代金属栅极围绕纳米线130，并且通过内部功函数层150和外部高k电介质层140与纳米线130分开。高k电介质层140因此接触纳米线130，同时功函数层150将金属栅极填充物145与高k电介质层140分离。鳍105沿与纳米线130相同的方向纵向延伸。相比之下，包括金属栅极填充物145的替代金属栅极、功函数层150和k电介质层140穿过鳍105横向延伸，与由纳米线130限定的纵轴成直角。关于替代金属栅极横跨鳍105的横向延伸，替代金属栅极位于沉积在鳍105上方的一对间隔物层115之间。延伸区域110在纳米线130的任一端和对应的漏极/源极区域155处直接位于间隔层115之下。延伸区域110因此位于纳米线130和漏极/源极区域155之间。如将在本文中进一步讨论的，用蚀刻停止掺杂剂注入延伸区域110，以便抵抗形成至少一个纳米线130的选择性蚀刻。选择性刻蚀的半导体层因此抵抗在纳米线晶体管100的沟道部分中形成纳米线130的选择性刻蚀。例如，在Si纳米线实施例中，SiGe层(在下面进一步讨论)是选择性刻蚀的半导体层。这样的选择性蚀刻也倾向于蚀刻延伸区域110内的SiGe层。但是，注入延伸区域110的蚀刻停止掺杂剂抑制硅纳米线实施例中延伸区域110中的SiGe层的选择性蚀刻。
延伸区域110内的选择性蚀刻的抑制导致替代金属栅极不延伸到延伸区域110中，而是限于延伸区域110之间的沟道区域。这对于减少纳米线晶体管100中不希望的栅极到源极和栅极到漏极的寄生电容是十分有利的。如将要进一步解释的那样，金属栅极填充物145以及其对应的内层150和外层140被沉积到由间隔物115限定的伪栅极开口中。为了进一步减少这些寄生电容，在沉积替代金属栅极之前，延伸区域110被通过伪栅极开口氧化以在选择性蚀刻半导体层中形成氧化帽125。然后，金属栅极填充物145及其内层150和外层140最终通过伪栅极开口沉积，使得氧化帽125位于纳米线130的两个纵向端部和延伸区域110的其余部分之间。因此，不仅防止金属栅极填充物145延伸到延伸区域110中，其也通过氧化帽125与延伸区域110绝缘，从而进一步减少任何得到的栅极到源极和栅极到漏极寄生电容。
纳米线晶体管100沿着虚线A：A截取的截面图在图1B中示出。与平面的和finFET方法相比，纳米线130完全被金属栅极填充物145围绕，使得形成在每个纳米线130中的所得到的沟道可以被更好地控制。在纳米线晶体管100中，存在两个鳍105，从而实际上存在四个纳米线130。应理解的是，在替代实施例中可以实现更少或更多数量的纳米线130。鳍105形成在衬底160上。鳍105由阱注入上的第一和第二半导体层的沉积形成。在该沉积之前，在阱注入中的氧注入形成整体局部隔离区域。然后蚀刻沉积的层以形成鳍105。该相同的蚀刻从先前形成在阱注入中的整体局部隔离区域形成局部隔离区域120。浅沟槽隔离(STI)氧化物区域165可以隔离鳍105。局部隔离区域120是非常有利的，因为它们使替代金属栅极与阱注入绝缘，以减少否则会在替代金属栅极和阱注入之间形成的任何不希望的寄生电容。参考以下示例性制造方法，可以更好地理解这些有利特征。
制造方法
为了开始制造，诸如硅衬底或绝缘体上硅(SOI)衬底的合适衬底接收如图2所示的阱注入200。然后，可以执行氧注入(例如通过注氧隔离(SiMOX)工艺)，以形成将最终被图案化成局部隔离区域120的整体局部隔离区域。然后，沉积选择性蚀刻的半导体层215以便与纳米线半导体层210交替。下面的讨论将假设纳米线半导体层210是Si层并且选择性蚀刻的半导体层215是SiGe层。在一个实施例中，层210和215可以被外延沉积。取决于所得到的纳米线晶体管将是p沟道金属氧化物(PMOS)器件还是n沟道(NMOS)器件，层210和215也可以是p型或n型掺杂的。然后可以在层210和215上执行浅沟槽隔离(STI)工艺以形成鳍105和STI区域165。例如，鳍105可以是从层210和215湿法蚀刻或干法蚀刻的。
如图3所示，然后例如氧化物材料的伪栅极330可以被横向沉积在每个鳍105上，接着向伪栅极330的每一侧进行成角度的延伸注入以形成延伸区域110。该延伸注入也包括用于选择性蚀刻层215的蚀刻停止掺杂剂。例如，对于选择性蚀刻层215包括SiGe层的实施例，碳可以用作蚀刻停止掺杂剂。延伸注入也将蚀刻停止掺杂剂注入到延伸区域110中的纳米线层210中，但是这些层已经抵抗将最终用于形成纳米线的选择性蚀刻过程，使得这种掺杂是无害的。然后可以在伪栅极330的任一侧上沉积间隔物115。间隔物115可以包括诸如氮化硅的合适材料。
现在参照图4，源极/漏极区域155可以外延沉积在延伸区域110上，接着进行源极/漏极区域155的结注入。层间电介质(ILD)填充步骤形成ILD区域400。在去除伪栅极之后，纳米线130可以通过在间隔物115之间产生的伪栅极开口或窗口410被选择性蚀刻。选择性蚀刻的半导体层215通过伪栅极开口410被选择性蚀刻以从纳米线层210形成纳米线130(图3)。例如，如果选择性蚀刻的半导体层215包括SiGe层，则可以使用酸性湿法蚀刻，如HCL、羧酸、HF或硝酸。替代地，如果选择性蚀刻的半导体层215是Si层，则可以使用碱性湿法蚀刻，如氢氧化铵或氢氧化钾水溶液。但是注入到延伸区域110中的蚀刻停止掺杂剂防止了延伸区域110中的选择性蚀刻层215被用于形成纳米线130的选择性蚀刻工艺蚀刻。因此，选择性蚀刻层215仅在伪栅极下方的区域405中被去除。在选择性蚀刻工艺之后，氧化帽125通过穿过伪栅极开口410的选择性氧化而形成。注入到延伸区域110中的蚀刻停止掺杂剂使得延伸区域110中的选择性蚀刻层215对该选择性氧化敏感。相比之下，纳米线130对形成氧化帽125的这种选择性氧化具有抵抗性。图5是横跨两个鳍105的横向横截面图，示出了在选择性刻蚀工艺之后纳米线130的隔离。
再次参考图1A和1B，替代金属栅极工艺可以开始于穿过图4的伪栅极开口410沉积的高k电介质层140。例如，高k电介质层140可以包括合适的材料，例如通过原子层沉积工艺沉积的二氧化铪、二氧化锆、硅酸铪或硅酸锆。然后沉积功函数层150。功函数层150可以包括氮化钛、氮化钽、钛铝或其他合适的材料。最后，沉积金属栅极填充物145。金属栅极填充物145可以包括钨或铝。与高k电介质层140一样，可以使用诸如原子级沉积或化学气相沉积的合适工艺来沉积金属栅极填充物145和功函数层150。
制造方法可以参考图6中所示的流程图进行总结。该方法包括氧化阱注入以形成局部隔离区域的动作600。图1A和1B中的局部隔离区域120的形成是动作600的一个例子。此外，该方法包括在局部隔离区域上形成鳍的动作605，该鳍包括交替的第一半导体的层和第二半导体的层，其中第一半导体的初始层邻接局部隔离区域，并且其中鳍从第一延伸区域延伸到第二延伸区域。图3中的鳍105及其层210和215的形成是动作605的示例。在这方面，图1A中的一个延伸区域110可以被认为是第一延伸区域，而延伸区域110中的其余延伸区域可以被认为是第二延伸区域。
而且，该方法包括在第一延伸区域和第二延伸区域中注入蚀刻停止掺杂剂的动作610。参考图3，讨论了蚀刻停止掺杂剂在第一和第二延伸区域中的注入。最后，该方法包括形成伪栅极开口以暴露鳍的栅极区域的动作615以及选择性地蚀刻在鳍的栅极区域中的第一半导体的层的动作620，以从栅极区域中的第二半导体的层形成纳米线，其中注入的蚀刻停止掺杂剂抑制在第一延伸区域和第二延伸区域中对第一半导体的层的选择性蚀刻。参考图4，讨论了伪栅极开口410的形成和第一半导体层的选择性蚀刻。
如现有技术中的那些技术人员现在将意识到的并且取决于手头的特定应用，可以对这些装置的材料、装置、配置和使用方法进行许多修改，替换和变化本公开内容不脱离其范围。鉴于此，本公开的范围不应限于在此说明和描述的特定实施例的范围，因为它们仅仅是通过其一些示例的方式，而是应该与此后所附权利要求及其功能等同完全相称。

Claims (13)

1.一种制造纳米线晶体管的方法，包括：
对阱注入进行氧化以形成局部隔离区域；
在所述局部隔离区域上形成包括交替的第一半导体的层和第二半导体的层的鳍，其中所述第一半导体的初始层邻接所述局部隔离区域，并且其中所述鳍从第一延伸区域延伸到第二延伸区域；
在所述第一延伸区域和所述第二延伸区域中注入蚀刻停止物；
形成伪栅极开口以暴露所述鳍的栅极区域；
选择性地蚀刻在所述鳍的所述栅极区域中的所述第一半导体的所述层，以从所述栅极区域中的所述第二半导体的所述层形成纳米线，其中经注入的所述蚀刻停止物抑制在所述第一延伸区域和第二延伸区域中对所述第一半导体的所述层的选择性蚀刻；
选择性氧化所述第一半导体的所述层，使得所述第一半导体的每一层包括从所述伪栅极开口延伸到所述第一延伸区域和所述第二延伸区域中的氧化帽；以及
在所述纳米线周围形成替代金属栅极。
2.根据权利要求1所述的方法，其中所述第一半导体是硅，并且所述第二半导体是硅锗。
3.根据权利要求1所述的方法，其中所述第一半导体是硅锗，并且所述第二半导体是硅。
4.根据权利要求3所述的方法，其中注入所述蚀刻停止物包括注入碳。
5.根据权利要求1所述的方法，其中沉积所述替代金属栅极包括沉积初始高k电介质层。
6.根据权利要求5所述的方法，其中沉积所述替代金属栅极还包括沉积后续功函数层。
7.根据权利要求6所述的方法，其中沉积所述替代金属栅极还包括沉积金属栅极填充物。
8.根据权利要求1所述的方法，其中形成所述鳍包括：沉积所述第一半导体的所述初始层、所述第二半导体的第二层、所述第一半导体的第三层和所述第二半导体的第四层。
9.一种纳米线晶体管，包括：
纳米线，从第一延伸区域中的第一半导体层延伸到第二延伸区域中的所述第一半导体层，所述第一延伸区域和所述第二延伸区域均包括与所述第一半导体层相邻的第二半导体层以及蚀刻停止掺杂剂；
在所述第一延伸区域的第一表面上的第一间隔物；
在所述第二延伸区域的第一表面上的第二间隔物；
围绕所述纳米线的替代金属栅极，其中所述第一延伸区域中的所述第二半导体层和所述第二延伸区域中的所述第二半导体层各自包括邻接所述替代金属栅极的氧化端，并且其中所述氧化端由所述第二半导体层的材料的氧化物构成；
衬底；以及
在所述衬底中与所述替代金属栅极相邻的阱注入，其中所述阱注入包括氧化局部隔离区域，所述氧化局部隔离区域位于所述阱注入的其余部分与所述替代金属栅极之间。
10.根据权利要求9所述的纳米线晶体管，其中所述第二半导体层包括硅锗层，所述硅锗层包括所述蚀刻停止掺杂剂。
11.根据权利要求9所述的纳米线晶体管，其中所述蚀刻停止掺杂剂包括碳。
12.根据权利要求9所述的纳米线晶体管，其中所述替代金属栅极包括：
与所述纳米线相邻的外部高k层；
金属栅极填充物；以及
在所述外部高k层和所述金属栅极填充物之间的功函数层。
13.根据权利要求9所述的纳米线晶体管，其中所述纳米线包括硅，并且其中所述第二半导体层包括硅锗。
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