US10381272B1 - Techniques for forming multiple work function nanosheet device - Google Patents

Techniques for forming multiple work function nanosheet device Download PDF

Info

Publication number
US10381272B1
US10381272B1 US16/003,969 US201816003969A US10381272B1 US 10381272 B1 US10381272 B1 US 10381272B1 US 201816003969 A US201816003969 A US 201816003969A US 10381272 B1 US10381272 B1 US 10381272B1
Authority
US
United States
Prior art keywords
nanowire stack
type
work function
function metal
device structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US16/003,969
Inventor
Min Gyu Sung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Varian Semiconductor Equipment Associates Inc
Original Assignee
Varian Semiconductor Equipment Associates Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Varian Semiconductor Equipment Associates Inc filed Critical Varian Semiconductor Equipment Associates Inc
Priority to US16/003,969 priority Critical patent/US10381272B1/en
Assigned to VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. reassignment VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SUNG, MIN GYU
Application granted granted Critical
Publication of US10381272B1 publication Critical patent/US10381272B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Definitions

  • the present embodiments relate to semiconductor device structures, and more particularly, to structures and processing for three dimensional transistor devices.
  • HGAA structures are often referred to as a nanosheet device because the HGAA transistor formation entails formation of multilayers of nanometer-thick sheets of two different semiconductor materials grown in an epitaxial heterostructure, such as a stack of alternating silicon and silicon:germanium alloy (SiGe) layers, arranged in a vertical configuration.
  • an epitaxial heterostructure such as a stack of alternating silicon and silicon:germanium alloy (SiGe) layers
  • CMOS complementary metal oxide semiconductor
  • PFET p-type FET
  • NFET n-type FET
  • This approach may entail formation of the first work function metal across the whole device, while the first work function metal is subsequently selectively removed from the NFET portion of a CMOS device, to be replaced with the appropriate, second work function metal on NFET gates.
  • operable techniques do not exist for selectively removing the first work function metal from NFET regions while not damaging PFET regions.
  • a method of forming a three-dimensional transistor device may include performing a first blanket deposition of a first work function metal over a first nanowire stack, having a first polarity, and over a second nanowire stack having a second polarity, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate.
  • the method may also include directing angled oxygen ions at the CMOS nanosheet device structure.
  • CMOS complementary metal oxide semiconductor
  • the method may further include performing a vertical etch to selectively remove the first work function metal between the first nanowire stack and the second nanowire stack.
  • a method of forming a three-dimensional transistor device may include performing a first blanket deposition of a P-type work function metal over a P-type nanowire stack and over an N-type nanowire stack, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate.
  • the method may include directing angled oxygen ions at the CMOS nanosheet device structure.
  • an oxide may be formed in the P-type work function metal along a top region of the P-type nanowire stack and the N-type nanowire stack, while an oxide is not formed in the P-type work function metal at a bottom of a trench between the P-type nanowire stack and the P-type nanowire stack.
  • the method may also include performing a vertical etch to remove the P-type work function metal between the P-type nanowire stack and the N-type nanowire stack, while not removing the P-type work function metal above the P-type nanowire stack and the N-type nanowire stack.
  • a method of forming a three-dimensional transistor device may include directing angled oxygen ions at a CMOS nanosheet device structure, where the CMOS device structure includes a titanium nitride layer disposed over a P-type nanowire stack and over an N-type nanowire stack.
  • titanium oxide may be formed in the titanium nitride layer along a top region of the N-type nanowire stack and the P-type nanowire stack, while titanium oxide is not formed in the titanium nitride layer at a bottom of a trench between the P-type nanowire stack and the P-type nanowire stack.
  • the method may include performing a first block patterning operation to expose N-type regions in the CMOS nanosheet device structure.
  • the method may also include performing a vertical etch to selectively remove the titanium nitride layer between the P-type nanowire stack and the N-type nanowire stack, wherein the titanium oxide is not removed along the top region.
  • FIG. 1A to FIG. 1D depict side different cross-sectional views of a semiconductor device structure, at one stage of fabrication, according to embodiments of the disclosure
  • FIG. 1E depicts a top plan view of one embodiment of the device structure of FIGS. 1A-1D , with various details omitted, illustrating the location of the cross-sectional views of FIG. 1A to FIG. 1D ;
  • FIG. 2A to FIG. 2D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 3A to FIG. 3D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 3E depicts a top plan view of one embodiment of the device structure of FIGS. 3A-3D , with various details omitted, illustrating the location of the cross-sectional views of FIG. 3A to FIG. 3D ;
  • FIG. 4A to FIG. 4D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 5A to FIG. 5D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 6A to FIG. 6D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 7A to FIG. 7D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 7E depicts a top plan view of one embodiment of the device structure of FIGS. 7A-7D , with various details omitted, illustrating the location of the cross-sectional views of FIG. 7A to FIG. 7D ;
  • FIG. 8A to FIG. 8D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 8E to FIG. 8F depict side cross-sectional views of a reference fabrication operation, corresponding to the operation stage of FIGS. 8A-8D ;
  • FIG. 9A to FIG. 9D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 10A to FIG. 10D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 11A to FIG. 11D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D , at another stage of fabrication;
  • FIG. 12 illustrates an exemplary process flow, according to embodiment of the disclosure.
  • the present embodiments provide novel techniques to form semiconductor devices, including three-dimensional transistors, formed in a semiconductor substrate.
  • three dimensional transistors such as HGAA transistors
  • HGAA transistors may be arranged in circuitry to form various types of logic devices, as well as memory devices.
  • An HGAA structure implemented in a CMOS architecture may be referred to herein as a “CMOS nanosheet device” where the CMOS nanosheet device includes both NFET and PFET transistor regions, arranged in stacks of semiconductor nanowires.
  • Such stacks may be referred to herein as nanowire stacks, where a nanowire stack of a first polarity may be a P-type nanowire stack, and a nanowire stack of a second polarity may be an N-type nanowire stack.
  • FIG. 1E depicts a top plan view of one embodiment of the device structure of FIGS. 1A-1D , with various details omitted, illustrating the location of the cross-sectional views of FIG. 1A to FIG. 1D .
  • the cut along the A-A section of FIG. 1A illustrates the structure of the semiconductor device structure 100 along an active P-type region, intersecting two adjacent gate regions.
  • the cut along the B-B section of FIG. 1B is parallel to the A-A cut, while located off the active regions, along isolation structures.
  • FIG. 1C is located along a gate structure, orthogonal to the A-A cut, intersecting two different active regions, a PFET region, and an NFET region, as shown.
  • the cut along the D-D section is parallel to the C-C section and intersects two active regions, while not along a gate.
  • FIG. 1E as described with respect to FIGS. 1A-1D also applies to the various views of the respective FIGS. 2A-2D, 3A-3D , . . . 11 A- 11 D to follow.
  • the device structure represents an intermediate stage of formation of a CMOS nanosheet device, generally fabricated according to known approaches.
  • the semiconductor device structure 100 has been fabricated to the point where nanowire structures have been formed and coated with a gate insulator and work function metal.
  • the work function metal coating the structures in FIG. 1A may be preserved in the appropriate devices having the polarity suited to the work function metal. Different portions of the same work function metal may be removed from other devices having the opposite polarity in subsequent operations.
  • the semiconductor device structure 100 includes a semiconductor base 102 , which base may be monocrystalline, such as monocrystalline silicon.
  • the semiconductor device structure 100 further includes a first nanowire stack 115 of a first polarity and a second nanowire stack 117 of a second polarity (see FIG. 1C ).
  • the first nanowire stack 115 and the second nanowire stack 117 may include a plurality of nanowires, shown as nanowires 106 , which nanowires may be monocrystalline silicon as in known devices.
  • the PFET region may represent the top active region shown and the left active region shown, respectively.
  • a difference between nanowires of the first nanowire stack 115 and the second nanowire stack 117 may thus be in the polarity of the doping of the nanowire.
  • the semiconductor device structure 100 may further include a source/drain region 104 , such as an epitaxially grown semiconductor.
  • the source/drain region 104 in the PFET region (shown in FIG. 1A ) will also vary in polarity from a source/drain region 104 of the NFET region (not shown in the figures).
  • the semiconductor device structure 100 further includes insulator regions 108 , arranged as shown, which regions may be oxide according to various embodiments.
  • the semiconductor device structure 100 may also include a silicon nitride liner 110 , a gate dielectric 112 , and a first work function metal 114 .
  • the first work function metal 114 may be assumed to be a P-type work function metal (also referred to as “PFET work function metal”).
  • the first work function metal 114 may be TiN, suitable for use in transistor gates of P-type transistors.
  • the first work function metal 114 may extend around the nanowires 106 in the NFET region.
  • practical work function metal deposition processes may generate blanket deposition of a metal, covering the device structures of both NFET regions (n-type regions) and PFET regions (p-type regions).
  • the second nanowire stack 117 for use in NFET transistors, may unavoidably be coated with a work function metal appropriate for PFETS, while not appropriate for NFETs.
  • FIGS. 2A-2D there is shown a subsequent instance where angled oxygen ions 116 are directed to the CMOS nanosheet device structure of FIGS. 1A-1D .
  • an oxide layer 118 is formed in the first work function metal 114 along a top region 119 of the first nanowire stack 115 and the second nanowire stack 117 , and wherein an oxide layer 118 is not formed in the first work function metal at a bottom 121 of a trench 124 between the first nanowire stack 115 and the second nanowire stack 117 .
  • the first work function metal 114 may be TiN, where exposure to oxygen ions may form the oxide layer 118 as titanium dioxide.
  • titanium nitride metal may be selectively etched with respect to titanium dioxide.
  • the angled oxygen ions 116 may form a non-zero angle of incidence ( ⁇ ) with respect to a perpendicular 123 to a plane 125 of the substrate.
  • ⁇ non-zero angle of incidence
  • a value of the non-zero angle of incidence may range between 10 degrees and 80 degrees.
  • dose of the angled oxygen ions 116 may range from 1E16/cm 2 to 2E17/cm 2 . The embodiments are not limited in this context.
  • an energy of the angled oxygen ions may be 2 keV or less, such as 1 keV.
  • the embodiments are not limited in this context.
  • Such a dose may and ion energy may be suitable to form an oxide layer having an appropriate thickness.
  • the thickness of the oxide layer 118 may range from 1 nm to 4 nm.
  • the value of the non-zero angle of incidence may be adjusted to ensure angled oxygen ions 116 do not strike the bottom 121 of trench 124 .
  • the first work function metal 114 may remain intact and unoxidized at the bottom 121 of trench 124 as well as at the bottom of trenches of FIG. 2A and FIG. 2B , while the top region 119 is impacted by the angled oxygen ions 116 and is transformed at least in part into the oxide layer 118 .
  • the angled oxygen ions 116 may be provided using a known beamline ion implanter, where the substrate 101 containing the semiconductor device structure 100 is tilted with respect to an oxygen-containing ion beam.
  • the substrate 101 may be tilted in different exposures to provide angled oxygen ions 116 from opposite directions, as suggested in FIG. 2C .
  • the angled oxygen ions 116 may be provided using a compact ion beam source, such as a plasma chamber equipped with an extraction plate, arranged to direct an angled oxygen beam to the substrate 101 , as known in the art.
  • FIGS. 3A-3D there is shown a subsequent instance where a block patterning is performed to form a mask 120 , where the mask 120 covers PFET regions of the semiconductor device structure 100 .
  • the mask 120 may be formed by known lithographic techniques where the mask material is an optical proximity layer, for example.
  • the mask 120 may be shifted so as to not completely cover the first nanowire stack 115 . This shifting ensures the trench 124 is fully exposed.
  • FIGS. 4A-4D there is shown a subsequent instance where a vertical etch is performed to selectively remove the first work function metal 114 between the first nanowire stack 115 and the second nanowire stack 117 .
  • the mask 120 is in place.
  • a directional reactive ion etch may be performed, shown by ions 122 , where the ions are directed along the Z-axis so as to reach the bottom 121 of trench 124 .
  • the ions 122 may be provided in a known reactive ion etch mixture used to selectively etch the first work function metal 114 with respect to the oxide layer 118 .
  • etch chemistry to selectively etch TiN with respect to titanium dioxide, such as C12-based plasmas is known.
  • the oxide layer 118 acts as a hard mask for the reactive ion etching operation shown. Because the trench 124 is fully exposed, the ions 122 serve as a self-aligned reactive ion etch, where any exposed regions of the first work function metal 114 , impacted by the ions 122 , may be etched, while exposed regions of the oxide layer 118 are not etched, or are etched to a lesser extent. As such, the first work function metal 114 may be removed from the bottom 121 of trench 124 , while the oxide layer 118 is preserved, at least in part, in the top regions 119 .
  • the first work function metal 114 is preserved in the PFET regions, covered by the oxide layer 118 or mask 120 , including the first nanowire stack 115 (as is also preserved in the NFET regions, second nanowire stack 117 ), while being removed from the region between nanowire stacks.
  • the removal of the first work function metal at the bottom 121 of trench 124 exposes the subjacent layer, meaning the gate dielectric 112 , between the first nanowire stack 115 and the second nanowire stack 117 .
  • FIGS. 5A-5D illustrate an instance where the mask 120 is selectively removed, such as using a known wet or dry etchant or solvent. Subsequently to the operation of FIGS.
  • FIGS. 6A-6D illustrate an optional operation where the oxide layer 118 is selectively removed.
  • FIGS. 7A-7D illustrate an operation where a second block pattern operation is performed to protect first polarity regions of the CMOS nanosheet device structure, after the performing the vertical etch. Said differently, the PMOS region is protected by forming a mask 130 , where open areas of the mask 130 are formed to expose NFET areas.
  • FIGS. 8A-8D illustrate an operation where the first work function metal 114 is removed from areas not protected by the mask 130 , namely NFET regions.
  • a known etch may be performed to selectively remove the first work function metal 114 in an isotropic manner.
  • the etchant used may etch TiN in one embodiment, while not etching the gate dielectric 112 .
  • the second nanowire stack 117 where NFET devices are to be formed no longer is coated with the first work function metal 114 .
  • FIGS. 9A-9D illustrate an instance where the mask 130 is selectively removed, such as using a known wet or dry etchant or solvent.
  • FIGS. 10A-10D illustrate an instance after a second work function metal 132 is deposited, followed by deposition of a gate conductor 134 .
  • the second work function metal 132 may be a known N-type work function metal.
  • the N-type work function metal may be TiAlC or other known N-type work function metal.
  • the gate conductor 134 may be tungsten metal.
  • the gate conductor 134 may be planarized, such as using a chemical mechanical polishing operation, as shown in FIG. 10B .
  • an appropriate work function metal now surrounds the first nanowire stack 115 (PFET) and the second nanowire stack 117 (NFET).
  • FIGS. 11A-11D illustrate a subsequent instance after a capping layer 136 has been deposited, such as silicon nitride.
  • Table I illustrates a reference flow where the angled oxidation of the present embodiments is not performed, as well as a flow using angled oxidation.
  • the operations listed in rows 1-9 are comparable to one another or are the same, where such operations are known in the art.
  • the flow in each case includes nanosheet stack (NS) patterning, shallow trench oxidation (STI) filling, dummy gate patterning, as well as recess of the patterned nanosheets, and inner spacer formation.
  • the nanosheet stacks may be a series of alternating layers of silicon and SiGe as known in the art.
  • a source/drain epitaxial growth process is performed, followed by removal of dummy gate material, such as polysilicon.
  • SiGe sheets are selectively removed from the nanosheet stacks, leaving isolated nanowires, such as silicon nanowires.
  • isolated nanowires are then coated with a gate oxide or gate dielectric and first work function metal, both in NFET and PFET regions.
  • angled oxidation flow A difference in the flow emerges in the operations shown in rows 10-13, just used in the angled oxidation flow.
  • angled O 2 implantation may be directed to the nanosheet stacks as discussed above, followed by a first block patterning operation, and vertical reactive ion etching to remove first work function metal from the bottom of trenches between nanosheet stacks, and second block patterning as described above.
  • the reference flow uses just one block patterning operation at row 14, while the operations of rows 15-17 are similar (not identical) to one another in both flows.
  • FIG. 8E An advantage of the angled oxidation flow may be highlighted by consideration of a side effect of the reference flow, as illustrated in FIG. 8E and FIG. 8F .
  • the FIG. 8F is meant to illustrate the resulting structure when the operation shown in FIGS. 8A-8D (row 15 of table I.) is performed using the reference flow, where no angled oxidation is performed.
  • no oxide layer hard mask has been formed, where the oxide layer hard mask (oxide layer 118 ) facilitates the selective removal of the first work function metal 114 from the bottom of trench 124 as shown in FIG. 4C , discussed above.
  • first work function metal 114 remains in place in the bottom of trench 124 , a subsequent process to remove the first work function metal 114 (such as TiN) from the NFET regions may inadvertently attack the PFET nanosheet stack, meaning first nanowire stack 115 .
  • This inadvertent damage is illustrated in FIG. 8F , showing the resulting structure after an etch 150 is performed to remove first work function metal 114 from the NFET region.
  • the etch 150 may be an isotropic etch configured to remove first work function metal 114 from all surfaces, given the three-dimensional nature of the nanosheet stacks. As shown in FIG.
  • a mask 140 is formed over the first nanowire stack 115 , while the second nanosheet stack is exposed, to allow removal of the first work function metal 114 from the NFET region.
  • the mask 140 does not extend down to the gate dielectric 112 . Accordingly, when exposed to an isotropic etchant to remove the first work function metal 114 , the isotropic etchant may attack under the mask 140 , generating the exposed nanosheet regions 142 . These exposed regions, bereft of work function metal, may cause failure of the PFET transistors to be formed.
  • the angled oxidation flow by removing the first work function metal 114 at the bottom of trench 124 , permits the mask 130 to contact the gate dielectric 112 , and to block any path of etchant to the first work function metal 114 in the PFET region, as shown.
  • FIG. 12 depicts an exemplary process flow 200 , according to embodiments of the disclosure.
  • a blanket deposition of a PFET work function metal is performed over NFET and PFET nanowire stacks of a CMOS nanosheet device structure.
  • the PFET work function metal may be TiN, such as a TIN layer, according to some embodiments. As such, both PFET nanowire stacks and NFET nanowire stacks may be coated with the PFET work function metal
  • angled oxygen ions are directed at the CMOS nanosheet device structure, wherein an oxide layer is formed in the PFET work function metal along tops of the NFET nanowire stack and PFET nanowire stack.
  • the oxide layer may extend through an entire thickness of the (former) PFET work function metal, or may form in a top portion of the PFET work function metal.
  • a thickness of the oxide layer may range between 1 nm and 4 nm.
  • a first block patterning operation is performed to expose NFET regions of the CMOS nanosheet device structure.
  • the block patterning may be performed wherein the covered portions of a mask are shifted to partially expose PFET nanosheet stacks, to ensure trench regions between PFET nanosheet stacks and adjacent NFET nanosheet stacks are exposed.
  • a vertical etching operation is performed to remove the PFET work function metal between PFET and NFET nanowire stacks, while not removing PFET work function metal above the PFET nanowire stacks and NFET nanowire stacks.
  • the vertical etching may involve directional reactive ion etching to selectively remove the PFET work function metal, such as TiN, while the oxide layer such as TiO 2 , remains in place, acting as a hard mask to protect subjacent regions.
  • the vertical etching may constitute a self-aligned etch process, etching just device regions such as trenches, where subjacent device structures, including the PFET work function metal is not covered by an oxide layer. As such, a gate dielectric in the bottom of the trenches may be exposed.
  • a second block patterning operation is performed to protect PFET regions of the CMOs nanosheet device structure, such as PFET nanowire stacks where transistors are formed.
  • the second block patterning operation may entail forming a mask covering the PFET nanowire stacks and extends over a portion of a trench between a PFET nanowire stack and adjacent NFET nanowire stack. Accordingly, the edge of the mask may extend to contact a gate dielectric in the trench.
  • the PFET work function metal is removed from the NFET nanowire stack(s) while not etching the PFET work function metal from the PFET nanowire stack(s).
  • the removal may be performed using an isotropic etch.
  • any PFET work function metal on the PFET nanowire stacks may be protected by the mask, wherein the isotropic etch does not attack the PFET nanowire stack.
  • an NFET work function metal is deposited in the NFET nanowire stack, so as to form a proper NFET transistor gate.
  • the present embodiments provide various advantages over known HGAA device processes.
  • the present approaches enable formation of dual work function metal CMOS devices in a nanosheet device structure.
  • the present embodiments further provide simplified self-aligned processes for achieving dual work function metal gate structures for CMOS nanosheet devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A method of forming a three-dimensional transistor device may include performing a first blanket deposition of a first work function metal over a first nanowire stack, having a first polarity, and over a second nanowire stack having a second polarity, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate. The method may include directing angled oxygen ions at the CMOS nanosheet device structure. As a result an oxide may be formed in the first work function metal along a top region of the first nanowire stack and the second nanowire stack, while an oxide is not formed in the first work function metal at a bottom of a trench between the first nanowire stack and the second nanowire stack. The method may include performing a vertical etch to selectively remove the first work function metal between the first nanowire stack and the second nanowire stack.

Description

FIELD
The present embodiments relate to semiconductor device structures, and more particularly, to structures and processing for three dimensional transistor devices.
BACKGROUND
As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), or horizontal gate all around (HGAA) transistor devices involves challenging processing issues. HGAA structures are often referred to as a nanosheet device because the HGAA transistor formation entails formation of multilayers of nanometer-thick sheets of two different semiconductor materials grown in an epitaxial heterostructure, such as a stack of alternating silicon and silicon:germanium alloy (SiGe) layers, arranged in a vertical configuration.
To form complementary metal oxide semiconductor (CMOS) devices, in many approaches the p-type FET (PFET) device is formed with a gate having a first work function metal, while the n-type FET (NFET) is formed with a gate having a second work function metal. This approach may entail formation of the first work function metal across the whole device, while the first work function metal is subsequently selectively removed from the NFET portion of a CMOS device, to be replaced with the appropriate, second work function metal on NFET gates. For nanosheet devices, operable techniques do not exist for selectively removing the first work function metal from NFET regions while not damaging PFET regions.
With respect to these and other considerations, the present disclosure is provided.
BRIEF SUMMARY
In an embodiment a method of forming a three-dimensional transistor device is provided. The method may include performing a first blanket deposition of a first work function metal over a first nanowire stack, having a first polarity, and over a second nanowire stack having a second polarity, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate. The method may also include directing angled oxygen ions at the CMOS nanosheet device structure. As a result an oxide may be formed in the first work function metal along a top region of the first nanowire stack and the second nanowire stack, while an oxide is not formed in the first work function metal at a bottom of a trench between the first nanowire stack and the second nanowire stack. The method may further include performing a vertical etch to selectively remove the first work function metal between the first nanowire stack and the second nanowire stack.
In a further embodiment, a method of forming a three-dimensional transistor device, may include performing a first blanket deposition of a P-type work function metal over a P-type nanowire stack and over an N-type nanowire stack, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate. The method may include directing angled oxygen ions at the CMOS nanosheet device structure. As such, an oxide may be formed in the P-type work function metal along a top region of the P-type nanowire stack and the N-type nanowire stack, while an oxide is not formed in the P-type work function metal at a bottom of a trench between the P-type nanowire stack and the P-type nanowire stack. The method may also include performing a vertical etch to remove the P-type work function metal between the P-type nanowire stack and the N-type nanowire stack, while not removing the P-type work function metal above the P-type nanowire stack and the N-type nanowire stack.
In another embodiment, a method of forming a three-dimensional transistor device is provided. The method may include directing angled oxygen ions at a CMOS nanosheet device structure, where the CMOS device structure includes a titanium nitride layer disposed over a P-type nanowire stack and over an N-type nanowire stack. As such, titanium oxide may be formed in the titanium nitride layer along a top region of the N-type nanowire stack and the P-type nanowire stack, while titanium oxide is not formed in the titanium nitride layer at a bottom of a trench between the P-type nanowire stack and the P-type nanowire stack. The method may include performing a first block patterning operation to expose N-type regions in the CMOS nanosheet device structure. The method may also include performing a vertical etch to selectively remove the titanium nitride layer between the P-type nanowire stack and the N-type nanowire stack, wherein the titanium oxide is not removed along the top region.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A to FIG. 1D depict side different cross-sectional views of a semiconductor device structure, at one stage of fabrication, according to embodiments of the disclosure;
FIG. 1E depicts a top plan view of one embodiment of the device structure of FIGS. 1A-1D, with various details omitted, illustrating the location of the cross-sectional views of FIG. 1A to FIG. 1D;
FIG. 2A to FIG. 2D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 3A to FIG. 3D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 3E depicts a top plan view of one embodiment of the device structure of FIGS. 3A-3D, with various details omitted, illustrating the location of the cross-sectional views of FIG. 3A to FIG. 3D;
FIG. 4A to FIG. 4D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 5A to FIG. 5D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 6A to FIG. 6D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 7A to FIG. 7D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 7E depicts a top plan view of one embodiment of the device structure of FIGS. 7A-7D, with various details omitted, illustrating the location of the cross-sectional views of FIG. 7A to FIG. 7D;
FIG. 8A to FIG. 8D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 8E to FIG. 8F depict side cross-sectional views of a reference fabrication operation, corresponding to the operation stage of FIGS. 8A-8D;
FIG. 9A to FIG. 9D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 10A to FIG. 10D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication;
FIG. 11A to FIG. 11D depict respective side cross-sectional views of the semiconductor device structure of FIG. 1A to FIG. 1D, at another stage of fabrication; and
FIG. 12 illustrates an exemplary process flow, according to embodiment of the disclosure.
 DETAILED DESCRIPTION
The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, where some embodiments are shown. The subject matter of the present disclosure may be embodied in many different forms and are not to be construed as limited to the embodiments set forth herein. These embodiments are provided so this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. In the drawings, like numbers refer to like elements throughout.
The present embodiments provide novel techniques to form semiconductor devices, including three-dimensional transistors, formed in a semiconductor substrate. As is known, three dimensional transistors, such as HGAA transistors, may be arranged in circuitry to form various types of logic devices, as well as memory devices. An HGAA structure implemented in a CMOS architecture may be referred to herein as a “CMOS nanosheet device” where the CMOS nanosheet device includes both NFET and PFET transistor regions, arranged in stacks of semiconductor nanowires. Such stacks may be referred to herein as nanowire stacks, where a nanowire stack of a first polarity may be a P-type nanowire stack, and a nanowire stack of a second polarity may be an N-type nanowire stack.
Turning now to FIG. 1A to FIG. 1D there are shown different side cross-sectional views of a semiconductor device structure 100, at one stage of fabrication, according to embodiments of the disclosure. FIG. 1E depicts a top plan view of one embodiment of the device structure of FIGS. 1A-1D, with various details omitted, illustrating the location of the cross-sectional views of FIG. 1A to FIG. 1D. The cut along the A-A section of FIG. 1A illustrates the structure of the semiconductor device structure 100 along an active P-type region, intersecting two adjacent gate regions. The cut along the B-B section of FIG. 1B is parallel to the A-A cut, while located off the active regions, along isolation structures. The cut along the C-C section of FIG. 1C is located along a gate structure, orthogonal to the A-A cut, intersecting two different active regions, a PFET region, and an NFET region, as shown. The cut along the D-D section is parallel to the C-C section and intersects two active regions, while not along a gate. The same convention shown in FIG. 1E as described with respect to FIGS. 1A-1D also applies to the various views of the respective FIGS. 2A-2D, 3A-3D, . . . 11A-11D to follow.
At the instance of FIG. 1A the device structure represents an intermediate stage of formation of a CMOS nanosheet device, generally fabricated according to known approaches. In FIG. 1A, the semiconductor device structure 100 has been fabricated to the point where nanowire structures have been formed and coated with a gate insulator and work function metal. As detailed below, because the semiconductor device structure 100 is to form a CMOS device, the work function metal coating the structures in FIG. 1A may be preserved in the appropriate devices having the polarity suited to the work function metal. Different portions of the same work function metal may be removed from other devices having the opposite polarity in subsequent operations. As shown in FIG. 1A, the semiconductor device structure 100 includes a semiconductor base 102, which base may be monocrystalline, such as monocrystalline silicon. The semiconductor device structure 100 further includes a first nanowire stack 115 of a first polarity and a second nanowire stack 117 of a second polarity (see FIG. 1C). The first nanowire stack 115 and the second nanowire stack 117 may include a plurality of nanowires, shown as nanowires 106, which nanowires may be monocrystalline silicon as in known devices. In the example of FIG. 1E and FIG. 1C, the PFET region may represent the top active region shown and the left active region shown, respectively. A difference between nanowires of the first nanowire stack 115 and the second nanowire stack 117 may thus be in the polarity of the doping of the nanowire. The semiconductor device structure 100 may further include a source/drain region 104, such as an epitaxially grown semiconductor. The source/drain region 104 in the PFET region (shown in FIG. 1A) will also vary in polarity from a source/drain region 104 of the NFET region (not shown in the figures). The semiconductor device structure 100 further includes insulator regions 108, arranged as shown, which regions may be oxide according to various embodiments.
The semiconductor device structure 100 may also include a silicon nitride liner 110, a gate dielectric 112, and a first work function metal 114. In the example shown, the first work function metal 114 may be assumed to be a P-type work function metal (also referred to as “PFET work function metal”). In particular embodiments, the first work function metal 114 may be TiN, suitable for use in transistor gates of P-type transistors. As shown in FIG. 1C, the first work function metal 114 may extend around the nanowires 106 in the NFET region. Notably, practical work function metal deposition processes may generate blanket deposition of a metal, covering the device structures of both NFET regions (n-type regions) and PFET regions (p-type regions). Thus, the second nanowire stack 117, for use in NFET transistors, may unavoidably be coated with a work function metal appropriate for PFETS, while not appropriate for NFETs.
Turning to FIGS. 2A-2D, there is shown a subsequent instance where angled oxygen ions 116 are directed to the CMOS nanosheet device structure of FIGS. 1A-1D. As such, an oxide layer 118 is formed in the first work function metal 114 along a top region 119 of the first nanowire stack 115 and the second nanowire stack 117, and wherein an oxide layer 118 is not formed in the first work function metal at a bottom 121 of a trench 124 between the first nanowire stack 115 and the second nanowire stack 117.
As noted, the first work function metal 114 may be TiN, where exposure to oxygen ions may form the oxide layer 118 as titanium dioxide. Advantageously, as discussed further below, titanium nitride metal may be selectively etched with respect to titanium dioxide. As shown in FIG. 2C, the angled oxygen ions 116 may form a non-zero angle of incidence (θ) with respect to a perpendicular 123 to a plane 125 of the substrate. In various embodiments a value of the non-zero angle of incidence may range between 10 degrees and 80 degrees. In some embodiments of dose of the angled oxygen ions 116 may range from 1E16/cm2 to 2E17/cm2. The embodiments are not limited in this context. In some embodiments, an energy of the angled oxygen ions may be 2 keV or less, such as 1 keV. The embodiments are not limited in this context. Such a dose may and ion energy may be suitable to form an oxide layer having an appropriate thickness. For example, in various non-limiting embodiments, the thickness of the oxide layer 118 may range from 1 nm to 4 nm.
Depending upon the aspect ratio of the trench 124, meaning the ratio of trench height along the Z-axis (of the Cartesian coordinate system shown) to trench width along the Y-axis, the value of the non-zero angle of incidence may be adjusted to ensure angled oxygen ions 116 do not strike the bottom 121 of trench 124. In this manner, the first work function metal 114 may remain intact and unoxidized at the bottom 121 of trench 124 as well as at the bottom of trenches of FIG. 2A and FIG. 2B, while the top region 119 is impacted by the angled oxygen ions 116 and is transformed at least in part into the oxide layer 118.
According to some embodiments, the angled oxygen ions 116 may be provided using a known beamline ion implanter, where the substrate 101 containing the semiconductor device structure 100 is tilted with respect to an oxygen-containing ion beam. The substrate 101 may be tilted in different exposures to provide angled oxygen ions 116 from opposite directions, as suggested in FIG. 2C. In other embodiments, the angled oxygen ions 116 may be provided using a compact ion beam source, such as a plasma chamber equipped with an extraction plate, arranged to direct an angled oxygen beam to the substrate 101, as known in the art.
Turning to FIGS. 3A-3D, there is shown a subsequent instance where a block patterning is performed to form a mask 120, where the mask 120 covers PFET regions of the semiconductor device structure 100. The mask 120 may be formed by known lithographic techniques where the mask material is an optical proximity layer, for example. As shown in FIG. 3C, the mask 120 may be shifted so as to not completely cover the first nanowire stack 115. This shifting ensures the trench 124 is fully exposed.
Turning to FIGS. 4A-4D, there is shown a subsequent instance where a vertical etch is performed to selectively remove the first work function metal 114 between the first nanowire stack 115 and the second nanowire stack 117. As shown, the mask 120 is in place. In this manner, a directional reactive ion etch may be performed, shown by ions 122, where the ions are directed along the Z-axis so as to reach the bottom 121 of trench 124. The ions 122 may be provided in a known reactive ion etch mixture used to selectively etch the first work function metal 114 with respect to the oxide layer 118. For example, etch chemistry to selectively etch TiN with respect to titanium dioxide, such as C12-based plasmas, is known. Thus, the oxide layer 118 acts as a hard mask for the reactive ion etching operation shown. Because the trench 124 is fully exposed, the ions 122 serve as a self-aligned reactive ion etch, where any exposed regions of the first work function metal 114, impacted by the ions 122, may be etched, while exposed regions of the oxide layer 118 are not etched, or are etched to a lesser extent. As such, the first work function metal 114 may be removed from the bottom 121 of trench 124, while the oxide layer 118 is preserved, at least in part, in the top regions 119. Accordingly, the first work function metal 114 is preserved in the PFET regions, covered by the oxide layer 118 or mask 120, including the first nanowire stack 115 (as is also preserved in the NFET regions, second nanowire stack 117), while being removed from the region between nanowire stacks. The removal of the first work function metal at the bottom 121 of trench 124 exposes the subjacent layer, meaning the gate dielectric 112, between the first nanowire stack 115 and the second nanowire stack 117. Subsequently to the operations of FIG. 4A, FIGS. 5A-5D illustrate an instance where the mask 120 is selectively removed, such as using a known wet or dry etchant or solvent. Subsequently to the operation of FIGS. 5A-5D, FIGS. 6A-6D illustrate an optional operation where the oxide layer 118 is selectively removed. Subsequently to the operation of FIGS. 6A-6D, FIGS. 7A-7D illustrate an operation where a second block pattern operation is performed to protect first polarity regions of the CMOS nanosheet device structure, after the performing the vertical etch. Said differently, the PMOS region is protected by forming a mask 130, where open areas of the mask 130 are formed to expose NFET areas.
Subsequently to the operation of FIGS. 7A-7D, FIGS. 8A-8D illustrate an operation where the first work function metal 114 is removed from areas not protected by the mask 130, namely NFET regions. A known etch may be performed to selectively remove the first work function metal 114 in an isotropic manner. The etchant used may etch TiN in one embodiment, while not etching the gate dielectric 112. As such, the second nanowire stack 117 where NFET devices are to be formed no longer is coated with the first work function metal 114.
Subsequently to the operation of FIGS. 8A-8D, FIGS. 9A-9D illustrate an instance where the mask 130 is selectively removed, such as using a known wet or dry etchant or solvent. Subsequently to the operation of FIGS. 9A-9D, FIGS. 10A-10D illustrate an instance after a second work function metal 132 is deposited, followed by deposition of a gate conductor 134. The second work function metal 132 may be a known N-type work function metal. In one non-limiting embodiment the N-type work function metal may be TiAlC or other known N-type work function metal. In various embodiments, the gate conductor 134 may be tungsten metal. After deposition, the gate conductor 134 may be planarized, such as using a chemical mechanical polishing operation, as shown in FIG. 10B. As such, an appropriate work function metal now surrounds the first nanowire stack 115 (PFET) and the second nanowire stack 117 (NFET). Subsequently to the operation of FIGS. 10A-10D, FIGS. 11A-11D illustrate a subsequent instance after a capping layer 136 has been deposited, such as silicon nitride.
Table I illustrates a reference flow where the angled oxidation of the present embodiments is not performed, as well as a flow using angled oxidation. The operations listed in rows 1-9 are comparable to one another or are the same, where such operations are known in the art. The flow in each case includes nanosheet stack (NS) patterning, shallow trench oxidation (STI) filling, dummy gate patterning, as well as recess of the patterned nanosheets, and inner spacer formation. Notably, the nanosheet stacks may be a series of alternating layers of silicon and SiGe as known in the art. Subsequently, a source/drain epitaxial growth process is performed, followed by removal of dummy gate material, such as polysilicon. Subsequently, SiGe sheets are selectively removed from the nanosheet stacks, leaving isolated nanowires, such as silicon nanowires. The isolated nanowires are then coated with a gate oxide or gate dielectric and first work function metal, both in NFET and PFET regions.
A difference in the flow emerges in the operations shown in rows 10-13, just used in the angled oxidation flow. In the angled oxidation flow angled O2 implantation may be directed to the nanosheet stacks as discussed above, followed by a first block patterning operation, and vertical reactive ion etching to remove first work function metal from the bottom of trenches between nanosheet stacks, and second block patterning as described above. The reference flow uses just one block patterning operation at row 14, while the operations of rows 15-17 are similar (not identical) to one another in both flows.
TABLE I
Reference Flow Angled Oxidation Flow
 1 NS patterning NS patterning
 2 STI STI
 3 Dummy gate patterning Dummy gate patterning
 4 NS recess NS recess
 5 Inner spacer formation Inner spacer formation
 6 S/D Epi S/D Epi
 7 Poly Si pull Poly Si pull
 8 SiGe sheet removal SiGe sheet removal
 9 Gate oxide/first WF Gate oxide/first WF
metal dep metal dep
10 Angled O2 implantation
11 Block pattern 1
12 RIE to disconnect bottom
first WF metal
13 Block pattern 2
14 Block pattern
15 First WF metal Protected First WF metal
removal removal
16 Second WF and gate Second WF and gate
metal dep metal dep
17 Capping SiN formation Capping SiN formation
An advantage of the angled oxidation flow may be highlighted by consideration of a side effect of the reference flow, as illustrated in FIG. 8E and FIG. 8F. The FIG. 8F is meant to illustrate the resulting structure when the operation shown in FIGS. 8A-8D (row 15 of table I.) is performed using the reference flow, where no angled oxidation is performed. Thus, in the example of FIG. 8E, no oxide layer hard mask has been formed, where the oxide layer hard mask (oxide layer 118) facilitates the selective removal of the first work function metal 114 from the bottom of trench 124 as shown in FIG. 4C, discussed above. Because the first work function metal 114 remains in place in the bottom of trench 124, a subsequent process to remove the first work function metal 114 (such as TiN) from the NFET regions may inadvertently attack the PFET nanosheet stack, meaning first nanowire stack 115. This inadvertent damage is illustrated in FIG. 8F, showing the resulting structure after an etch 150 is performed to remove first work function metal 114 from the NFET region. Notably, the etch 150 may be an isotropic etch configured to remove first work function metal 114 from all surfaces, given the three-dimensional nature of the nanosheet stacks. As shown in FIG. 8E, a mask 140 is formed over the first nanowire stack 115, while the second nanosheet stack is exposed, to allow removal of the first work function metal 114 from the NFET region. Notably, because of the presence of the first work function metal 114 at the bottom of trench 124, the mask 140 does not extend down to the gate dielectric 112. Accordingly, when exposed to an isotropic etchant to remove the first work function metal 114, the isotropic etchant may attack under the mask 140, generating the exposed nanosheet regions 142. These exposed regions, bereft of work function metal, may cause failure of the PFET transistors to be formed. With reference again to FIG. 4C, the angled oxidation flow, by removing the first work function metal 114 at the bottom of trench 124, permits the mask 130 to contact the gate dielectric 112, and to block any path of etchant to the first work function metal 114 in the PFET region, as shown.
FIG. 12 depicts an exemplary process flow 200, according to embodiments of the disclosure. At block 202, a blanket deposition of a PFET work function metal is performed over NFET and PFET nanowire stacks of a CMOS nanosheet device structure. The PFET work function metal may be TiN, such as a TIN layer, according to some embodiments. As such, both PFET nanowire stacks and NFET nanowire stacks may be coated with the PFET work function metal
At block 204, angled oxygen ions are directed at the CMOS nanosheet device structure, wherein an oxide layer is formed in the PFET work function metal along tops of the NFET nanowire stack and PFET nanowire stack. The oxide layer may extend through an entire thickness of the (former) PFET work function metal, or may form in a top portion of the PFET work function metal. In various non-limiting embodiments, a thickness of the oxide layer may range between 1 nm and 4 nm. At the same time, by virtue of the angle of incidence of the angled oxygen ions, an oxide layer is not formed in the PFET work function metal at the bottom of trenches between the NFET nanowire stack and PFET nanowire stack.
At block 206, a first block patterning operation is performed to expose NFET regions of the CMOS nanosheet device structure. The block patterning may be performed wherein the covered portions of a mask are shifted to partially expose PFET nanosheet stacks, to ensure trench regions between PFET nanosheet stacks and adjacent NFET nanosheet stacks are exposed.
At block 208, a vertical etching operation is performed to remove the PFET work function metal between PFET and NFET nanowire stacks, while not removing PFET work function metal above the PFET nanowire stacks and NFET nanowire stacks. The vertical etching may involve directional reactive ion etching to selectively remove the PFET work function metal, such as TiN, while the oxide layer such as TiO2, remains in place, acting as a hard mask to protect subjacent regions. As such, the vertical etching may constitute a self-aligned etch process, etching just device regions such as trenches, where subjacent device structures, including the PFET work function metal is not covered by an oxide layer. As such, a gate dielectric in the bottom of the trenches may be exposed.
At block 210, a second block patterning operation is performed to protect PFET regions of the CMOs nanosheet device structure, such as PFET nanowire stacks where transistors are formed. The second block patterning operation may entail forming a mask covering the PFET nanowire stacks and extends over a portion of a trench between a PFET nanowire stack and adjacent NFET nanowire stack. Accordingly, the edge of the mask may extend to contact a gate dielectric in the trench.
At block 212, the PFET work function metal is removed from the NFET nanowire stack(s) while not etching the PFET work function metal from the PFET nanowire stack(s). The removal may be performed using an isotropic etch. As such, any PFET work function metal on the PFET nanowire stacks may be protected by the mask, wherein the isotropic etch does not attack the PFET nanowire stack.
At block 214, an NFET work function metal is deposited in the NFET nanowire stack, so as to form a proper NFET transistor gate.
The present embodiments provide various advantages over known HGAA device processes. For one advantage, the present approaches enable formation of dual work function metal CMOS devices in a nanosheet device structure. For another advantage, the present embodiments further provide simplified self-aligned processes for achieving dual work function metal gate structures for CMOS nanosheet devices.
The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are in the tended to fall within the scope of the present disclosure. Furthermore, the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, while those of ordinary skill in the art will recognize the usefulness is not limited thereto and the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Thus, the claims set forth below are to be construed in view of the full breadth and spirit of the present disclosure as described herein.

Claims (19)

What is claimed is:
1. A method of forming a three-dimensional transistor device, comprising:
performing a first blanket deposition of a first work function metal over a first nanowire stack, having a first polarity, and over a second nanowire stack having a second polarity, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate;
directing angled oxygen ions at the CMOS nanosheet device structure, wherein an oxide is formed in the first work function metal along a top region of the first nanowire stack and the second nanowire stack, and wherein an oxide layer is not formed in the first work function metal at a bottom of a trench between the first nanowire stack and the second nanowire stack; and
performing a vertical etch to selectively remove the first work function metal between the first nanowire stack and the second nanowire stack.
2. The method of claim 1, wherein the vertical etch comprises a reactive ion etching operation, wherein the first work function metal is a TiN layer, wherein the oxide layer comprises titanium dioxide, and wherein the reactive ion etching operation selectively etches the TiN layer with respect to the titanium dioxide.
3. The method of claim 1, further comprising:
performing a first block patterning operation to expose second polarity regions in the CMOS nanosheet device structure, before the direction the performing the vertical etch.
4. The method of claim 3, further comprising:
performing a second block patterning operation to protect first polarity regions of the CMOS nanosheet device structure, after the performing the vertical etch; and
removing the first work function metal from the second nanowire stack while not etching the first work function metal from the first nanowire stack.
5. The method of claim 4, further comprising:
after the removing the first work function metal, performing a second blanket deposition of a second work function metal over the first nanowire stack and the second nanowire stack.
6. The method of claim 1, wherein the angled oxygen ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate.
7. The method of claim 6, wherein a value of the non-zero angle of incidence ranges between 10 degrees and 80 degrees.
8. The method of claim 1, wherein a dose of the angled oxygen ions ranges from 1E16/cm2 to 2E17/cm2.
9. The method of claim 1, wherein an energy of the angled oxygen ions is 2 keV or less.
10. The method of claim 1, wherein a thickness of the oxide layer is 1 nm to 4 nm.
11. A method of forming a three-dimensional transistor device, comprising;
performing a first blanket deposition of a P-type work function metal over a P-type nanowire stack and over an N-type nanowire stack, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate;
directing angled oxygen ions at the CMOS nanosheet device structure, wherein an oxide is formed in the P-type work function metal along a top region of the P-type nanowire stack and the N-type nanowire stack, and wherein an oxide is not formed in the P-type work function metal at a bottom of a trench between the P-type nanowire stack and the P-type nanowire stack; and
performing a vertical etch to remove the P-type work function metal between the P-type nanowire stack and the N-type nanowire stack, while not removing the P-type work function metal above the P-type nanowire stack and the N-type nanowire stack.
12. The method of claim 11, wherein the vertical etch comprises a reactive ion etching operation, wherein the P-type work function metal is a TiN layer, wherein the oxide is titanium dioxide, and wherein the reactive ion etching operation selectively etches the TiN layer with respect to the titanium dioxide.
13. The method of claim 11, further comprising:
performing a first block patterning operation to expose N-type regions in the CMOS nanosheet device structure, before the performing the vertical etch.
14. The method of claim 13, further comprising:
performing a second block patterning operation to protect P-type polarity regions of the CMOS nanosheet device structure, after the performing the vertical etch; and
removing the P-type work function metal from the N-type nanowire stack while not etching the P-type work function metal from the P-type nanowire stack.
15. The method of claim 11, wherein the P-type nanowire stack and the N-type nanowire stack comprise a plurality of silicon nanowires, stacked in a vertical configuration, wherein the trench has an aspect ratio of 1 or greater, wherein a trench depth is greater than or equal to a trench width, defining a spacing between the P-type nanowire stack and the N-type nanowire stack.
16. A method of forming a three-dimensional transistor device, comprising;
directing angled oxygen ions at a CMOS nanosheet device structure, comprising a titanium nitride layer disposed over a P-type nanowire stack and over an N-type nanowire stack, wherein titanium oxide is formed in the titanium nitride layer along a top region of the N-type nanowire stack and the P-type nanowire stack, and wherein the titanium oxide is not formed in the titanium nitride layer at a bottom of a trench between the P-type nanowire stack and the P-type nanowire stack;
performing a first block patterning operation to expose N-type polarity regions in the CMOS nanosheet device structure; and
performing a vertical etch to selectively remove the titanium nitride layer between the P-type nanowire stack and the N-type nanowire stack, wherein the titanium oxide is not removed along the top region.
17. The method of claim 16, further comprising:
performing a first block patterning operation to expose the N-type polarity regions in the CMOS nanosheet device structure, before the performing the vertical etch.
18. The method of claim 17, further comprising:
performing a second block patterning operation to protect P-type regions of the CMOS nanosheet device structure, after the performing the vertical etch; and
removing the titanium nitride layer from the N-type nanowire stack while not etching the titanium nitride layer from the P-type nanowire stack.
19. The method of claim 18, further comprising:
after the removing the titanium nitride layer, performing a second blanket deposition of an N-type work function metal over the P-type nanowire stack and the N-type nanowire stack.
US16/003,969 2018-06-08 2018-06-08 Techniques for forming multiple work function nanosheet device Active US10381272B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/003,969 US10381272B1 (en) 2018-06-08 2018-06-08 Techniques for forming multiple work function nanosheet device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16/003,969 US10381272B1 (en) 2018-06-08 2018-06-08 Techniques for forming multiple work function nanosheet device

Publications (1)

Publication Number Publication Date
US10381272B1 true US10381272B1 (en) 2019-08-13

Family

ID=67543699

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/003,969 Active US10381272B1 (en) 2018-06-08 2018-06-08 Techniques for forming multiple work function nanosheet device

Country Status (1)

Country Link
US (1) US10381272B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114225839A (en) * 2022-01-06 2022-03-25 南京工业大学 Method for preparing specific corner two-dimensional heterojunction material
US11410889B2 (en) * 2019-12-31 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100038721A1 (en) * 2008-08-18 2010-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a single metal that performs n work function and p work function in a high-k/metal gate process
US20160027929A1 (en) * 2014-07-25 2016-01-28 International Business Machines Corporation Perfectly symmetric gate-all-around fet on suspended nanowire
US20170186846A1 (en) * 2015-12-28 2017-06-29 Qualcomm Incorporated Nanowire device with reduced parasitics
US20170222024A1 (en) * 2016-01-28 2017-08-03 International Business Machines Corporation Forming stacked nanowire semiconductor device
US9947804B1 (en) * 2017-07-24 2018-04-17 Globalfoundries Inc. Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100038721A1 (en) * 2008-08-18 2010-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a single metal that performs n work function and p work function in a high-k/metal gate process
US20160027929A1 (en) * 2014-07-25 2016-01-28 International Business Machines Corporation Perfectly symmetric gate-all-around fet on suspended nanowire
US20170186846A1 (en) * 2015-12-28 2017-06-29 Qualcomm Incorporated Nanowire device with reduced parasitics
US20170222024A1 (en) * 2016-01-28 2017-08-03 International Business Machines Corporation Forming stacked nanowire semiconductor device
US9947804B1 (en) * 2017-07-24 2018-04-17 Globalfoundries Inc. Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Loubet, et al., "Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET," 2017 Symposium on VLSI Technology Digest of Technical Papers, T230-T231, 2017 JSAP.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11410889B2 (en) * 2019-12-31 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN114225839A (en) * 2022-01-06 2022-03-25 南京工业大学 Method for preparing specific corner two-dimensional heterojunction material

Similar Documents

Publication Publication Date Title
US10727135B2 (en) FinFET with sloped surface at interface between isolation structures and manufacturing method thereof
US6911383B2 (en) Hybrid planar and finFET CMOS devices
US10971403B2 (en) Structure and method of forming fin device having improved fin liner
US7591659B2 (en) Method and structure for second spacer formation for strained silicon MOS transistors
EP3185286B1 (en) Method and device to improve shallow trench isolation
KR102289284B1 (en) Reduce well dopant loss in finfets through co-implantation
US10403738B1 (en) Techniques for improved spacer in nanosheet device
US10381272B1 (en) Techniques for forming multiple work function nanosheet device
CN109148447B (en) Semiconductor structure and forming method thereof
US20200185228A1 (en) Gate all around device and method of formation using angled ions
CN105990255A (en) Method of fabricating semiconductor device
US10388745B1 (en) Structure and method of forming transistor device having improved gate contact arrangement
US20170200649A1 (en) Transistor with source-drain silicide pullback
TW201901792A (en) Method of reducing fin width in a FINFET SRAM array to mitigate low voltage band bit failure
US11152370B2 (en) Memory structure having transistors and capacitor and manufacturing method thereof
US10629694B1 (en) Gate contact and cross-coupling contact formation
CN110752153B (en) Semiconductor structure and forming method thereof
US7851299B2 (en) Subgroundrule space for improved metal high-k device
US10804156B2 (en) Techniques for forming dual epitaxial source/drain semiconductor device
JP2005340579A (en) Semiconductor device, semiconductor manufacturing method, semiconductor manufacturing device and portable information console unit
US20070281432A1 (en) Transistor and method of providing interlocking strained silicon on a silicon substrate
US10510870B2 (en) Techniques for forming device having etch-resistant isolation oxide
TWI701789B (en) Semiconductor structure and manufacturing method thereof
CN115841951A (en) Method for improving field effect transistor load
CN103855027A (en) Finfet and manufacturing method thereof

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4