JP2005340579A - Semiconductor device, semiconductor manufacturing method, semiconductor manufacturing device and portable information console unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves low power consumption operation and high speed operation by reducing the parasitic capacity of a diffusion layer. <P>SOLUTION: An element separating region 9 is formed in an oblique direction with respect to the surface of the diffusion layer 14 in this semiconductor device whereby a connecting area between the diffusion layer 14 and a well region 8 is reduced, thereby reducing the parasitic capacity. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to, for example, a semiconductor device, a semiconductor manufacturing method, a semiconductor manufacturing device, and a portable information terminal device, and in particular, reduces parasitic capacitance of a diffusion layer and enables low power consumption operation and high speed operation.

  Currently, portable information terminal devices such as mobile phones are widely used. In order to use this portable information terminal device for a long time with a single charge, it is necessary to reduce the power consumption of the LSI used in this device. In order to reduce the power consumption of this LSI, it is effective to reduce the parasitic capacitance of the wiring and diffusion layer. Further, by reducing the parasitic capacitance, high speed operation can be achieved at the same time.

  FIG. 10 shows a conventional diffusion layer wiring. As shown in FIG. 10, in the conventional diffusion layer wiring, a first conductivity type well region 108 is provided in a semiconductor substrate 101, and a second conductivity type diffusion layer 114 is provided in the first conductivity type well region 108. The second conductive type diffusion layer 114 functions as a wiring.

  However, in the conventional diffusion layer wiring shown in FIG. 10, the junction area between the diffusion layer 114 and the well region 108 is large, and due to the parasitic capacitance resulting from this junction, power consumption increases and high speed operation is hindered. There was a problem.

  Therefore, conventionally, as shown in FIG. 11, a configuration has been proposed in which the diffusion layer 114 is sandwiched by the element isolation region 109 to reduce the junction capacitance between the sidewall of the diffusion layer 114 and the well region 108. (See Japanese Patent Laid-Open No. 10-163342: Patent Document 1).

  FIG. 12 shows a conventional etching apparatus, and the diffusion layer wiring of FIG. 11 is manufactured by this etching apparatus. The etching apparatus includes a vacuum chamber 121, a gas inlet 128, a gas exhaust port 129, and a pair of parallel electrodes, an upper electrode 123 and a lower electrode 122, which are arranged to face each other in the vacuum chamber 121, A blocking capacitance 125 and a high frequency generation power supply 126 connected to the lower electrode 122 are provided. The upper electrode 123 is grounded to the earth potential. In the etching apparatus shown in FIG. 12, plasma is generated between the upper electrode 123 and the lower electrode 122, and an electric field perpendicular to the surface of the substrate to be processed 124 installed on the lower electrode 122 is used. Thus, an etching shape in a direction perpendicular to the surface of the substrate to be processed 124 is obtained.

However, the conventional etching apparatus shown in FIG. 12 can etch only in a direction substantially perpendicular to the substrate to be processed 124, and usually the element isolation as in the conventional semiconductor apparatus shown in FIG. The bottom surface of the region 109 is smaller than the top surface of the element isolation region 109. For this reason, the junction area between the diffusion layer 114 and the well region 108 is larger than the surface area of the diffusion layer 114 exposed from the well region 108, and it is difficult to reduce power consumption and to operate at high speed.
Japanese Patent Laid-Open No. 10-163342

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that reduces parasitic capacitance and enables low power consumption operation and high speed operation by forming an element isolation region obliquely with respect to the substrate surface. .

In order to solve the above problems, a semiconductor device of the present invention is
A semiconductor substrate;
An element isolation region;
A first conductivity type well region provided in the semiconductor substrate;
A diffusion layer of a second conductivity type formed in the well region of the first conductivity type,
The element isolation region is formed so that an area in contact between the diffusion layer and the well region is smaller than a surface area of the diffusion layer exposed from the well region.

  Here, the first conductivity type is a P type or an N type. When the first conductivity type is a P type, the second conductivity type is an N type, and the first conductivity type is an N type. In this case, the second conductivity type is a P type.

  According to the semiconductor device of the present invention, the element isolation region is formed so that an area where the diffusion layer and the well region are in contact with each other is smaller than a surface area of the diffusion layer exposed from the well region. The junction area between the diffusion layer and the well region can be reduced. For this reason, the parasitic capacitance between the diffusion layer and the well region can be reduced, and low power consumption operation and high speed operation are possible.

The semiconductor device of the present invention is
A semiconductor substrate;
An element isolation region;
A first conductivity type well region provided in the semiconductor substrate;
A gate insulating film formed on the first conductivity type well region;
A gate electrode formed on the gate insulating film;
A second conductivity type source region and drain region formed in the first conductivity type well region;
A channel region formed between the source region and the drain region,
The element isolation region is formed in an oblique direction so as to have an acute angle with respect to the surface of the well region on the gate electrode side in a cross section in the gate length direction.

  According to the semiconductor device of the present invention, in the field effect transistor, the element isolation region is formed in an oblique direction so as to have an acute angle with respect to the surface of the well region on the gate electrode side in the cross section in the gate length direction. Therefore, the junction area between the source and drain regions and the well region can be reduced as compared with the case where the element isolation region is formed perpendicular to the surface of the well region. For this reason, parasitic capacitance between the source and drain regions and the well region can be reduced, and low power consumption operation and high speed operation are possible.

The semiconductor device of the present invention is
A semiconductor substrate;
An element isolation region;
A second well-type deep well region provided on the semiconductor substrate;
A first well type shallow well region formed in the second well type deep well region;
A gate insulating film formed on the first conductivity type shallow well region;
A gate electrode formed on the gate insulating film and electrically connected to the shallow well region of the first conductivity type through the well contact portion;
A second conductivity type source region and drain region formed in the first conductivity type shallow well region;
A channel region formed between the source region and the drain region,
The element isolation region is formed so that an area where the shallow well region and the deep well region are in contact with each other is smaller than a surface area of the shallow well region exposed from the deep well region.

  According to the semiconductor device of the present invention, in the bulk dynamic threshold transistor (B-DTMOSFET: Bulk Dynamic Threshold Voltage MOSFET), the element isolation region has an area where the shallow well region and the deep well region are in contact with each other. Since it is formed so as to be smaller than the surface area of the shallow well region exposed from the deep well region, the junction area between the shallow well region and the deep well region can be reduced. For this reason, the increase in capacity and parasitic vertical bipolar current caused by the junction can be suppressed, and high-speed operation and low power consumption operation are possible.

In one embodiment of the semiconductor device,
The element isolation region is formed in an oblique direction so as to have an acute angle with respect to the surface of the shallow well region on the gate electrode side in the cross section in the gate length direction,
The junction between the shallow well region and the deep well region is near the lower end of the element isolation region.

  According to the semiconductor device of this embodiment, the junction area between the shallow well region and the deep well region in the B-DTMOSFET can be efficiently reduced.

In one embodiment of the semiconductor device,
In the cross section of the channel region in the gate length direction, an element isolation region formed obliquely with respect to the surface of the shallow well region from one side (right side) of the gate electrode to a direction directly below the gate electrode And an element isolation region formed obliquely with respect to the surface of the shallow well region from the other side (left side) of the gate electrode to a direction directly below the gate electrode is directly below the gate electrode. Connected,
An element formed in an oblique direction with respect to the surface of the shallow well region from one side (right side) of the gate electrode to a direction directly below the gate electrode in a cross section in the gate length direction near the well contact portion. The isolation region and the element isolation region formed in an oblique direction with respect to the surface of the shallow well region from the other side (left side) of the gate electrode to a direction directly below the gate electrode Separated directly below.

  According to the semiconductor device of this embodiment, the junction between the shallow well region and the deep well region under the channel region in the B-DTMOSFET can be eliminated, and the capacitance increase and parasitic vertical bipolar caused by the junction can be eliminated. Since the current can be eliminated, further high speed operation and low power consumption operation are possible.

The semiconductor device of the present invention is
A semiconductor substrate;
An element isolation region;
A first conductivity type well region provided in the semiconductor substrate;
A gate insulating film formed on the first conductivity type well region;
A gate electrode formed on the gate insulating film and electrically connected to the well region of the first conductivity type through the well contact portion;
A second conductivity type source region and drain region formed in the first conductivity type well region;
A channel region formed between the source region and the drain region,
In the cross section in the gate length direction, an element isolation region formed obliquely with respect to the surface of the well region from one side (right side) of the gate electrode to a direction directly below the gate electrode, and the gate electrode The element isolation region formed obliquely with respect to the surface of the well region from the other side (left side) in the direction directly below the gate electrode is connected directly below the gate electrode,
The channel region is electrically isolated from the semiconductor substrate.

  According to the semiconductor device of the present invention, in a bulk dynamic threshold voltage transistor (B-DTMOSFET: Bulk Dynamic Threshold Voltage MOSFET), from one side of the gate electrode in the cross section in the gate length direction, directly below the gate electrode. An element isolation region formed obliquely with respect to the surface of the well region toward the direction, and an oblique direction with respect to the surface of the well region from the other side of the gate electrode toward a direction directly below the gate electrode Since the channel region is electrically isolated from the semiconductor substrate, the parasitic vertical bipolar device is not formed because the channel isolation region is connected to the device isolation region formed immediately below the gate electrode. The parasitic capacitance is reduced, and high speed operation and low power consumption operation are possible. Further, since the deep well region necessary for the B-DTMOSFET is not necessary, the implantation process can be reduced.

The semiconductor manufacturing apparatus of the present invention is
A pair of opposing first and second electrodes;
A high frequency generating power source that is connected to the first electrode or the second electrode and applies high frequency power so as to generate plasma between the first electrode and the second electrode;
An electric field generating means for generating an electric field in a direction perpendicular to a direction connecting the first electrode and the second electrode is provided.

  According to the semiconductor manufacturing apparatus of the present invention, since the first electrode, the second electrode, and the high-frequency power supply are provided, the substrate to be processed disposed on the first electrode or the second electrode In contrast, a plasma etching process can be performed. In addition, since the electric field generating means is provided, a constant electric field in a direction parallel to the substrate to be processed can be formed. In this manner, etching in an oblique direction with respect to the substrate to be processed can be performed. The electric field generating means includes, for example, a pair of first and second electric field generating electrodes facing each other, and the first and second electric field generating electrodes are provided with the substrate to be processed. It arrange | positions so that the said 1st electrode or said 2nd electrode which installs the said to-be-processed substrate may be pinched | interposed in the vicinity of the said 1st electrode or the said 2nd electrode.

The semiconductor manufacturing apparatus of the present invention is
A pair of opposing first and second electrodes;
A high frequency generating power source that is connected to the first electrode or the second electrode and applies high frequency power so as to generate plasma between the first electrode and the second electrode;
Magnetic field generating means for generating a magnetic field in a direction perpendicular to a direction connecting the first electrode and the second electrode is provided.

  According to the semiconductor manufacturing apparatus of the present invention, since the first electrode, the second electrode, and the high-frequency power supply are provided, the substrate to be processed disposed on the first electrode or the second electrode In contrast, a plasma etching process can be performed. Further, since the magnetic field generating means is provided, a constant magnetic field in a direction parallel to the substrate to be processed can be formed. In this manner, etching in an oblique direction with respect to the substrate to be processed can be performed. The magnetic field generating means has, for example, a pair of opposing first and second coils (or magnets), and the first and second coils (or magnets) It arrange | positions so that the said 1st electrode or said 2nd electrode which installs the said to-be-processed substrate may be pinched | interposed in the vicinity of the said 1st electrode or the said 2nd electrode to install.

  The semiconductor manufacturing apparatus according to an embodiment further includes a rotating unit that rotates the first electrode or the second electrode around a direction connecting the first electrode and the second electrode. .

  According to the semiconductor manufacturing apparatus of this embodiment, since the rotating means is provided, the substrate to be processed is installed on the first electrode or the second electrode rotated by the rotating means, and By performing plasma etching while rotating the substrate to be processed, oblique etching in an arbitrary direction can be performed on the substrate to be processed. The first electrode or the second electrode rotated by the rotating means is rotated about an axis that passes through the center of the substrate to be processed and is perpendicular to the surface of the substrate to be processed.

The semiconductor manufacturing method of the present invention is
Arranging a substrate to be processed on an electrode for plasma generation;
And a step of performing a plasma etching process on the substrate to be processed in a state where an electric field parallel to the substrate to be processed is applied in the vicinity of the plasma generating electrode.

  According to the semiconductor manufacturing method of the present invention, since the plasma processing is performed on the substrate to be processed while an electric field in a direction parallel to the substrate to be processed is applied, the etching shape in the oblique direction is good on the substrate to be processed. Formed.

The semiconductor manufacturing method of the present invention is
Arranging a substrate to be processed on an electrode for plasma generation;
And a step of performing a plasma etching process on the substrate to be processed in a state where a magnetic field parallel to the substrate to be processed is applied in the vicinity of the electrode for generating plasma.

  According to the semiconductor manufacturing method of the present invention, since the plasma etching process is performed on the substrate to be processed in a state where a magnetic field parallel to the substrate to be processed is applied, the etching shape in the oblique direction is good on the substrate to be processed. Formed.

  The semiconductor device of the present invention is manufactured using the semiconductor manufacturing method of the present invention.

  According to the semiconductor device of the present invention, since the semiconductor device is manufactured using the semiconductor manufacturing method of the present invention, the element isolation region is formed to have an acute angle with respect to the substrate surface on the gate electrode side in the cross section in the gate length direction. Therefore, the junction capacitance between the source region and the drain region in a normal MOSFET is reduced, and high speed operation and low power consumption operation are possible.

  A portable information terminal device according to the present invention includes the semiconductor device according to the present invention.

  According to the portable information terminal device of the present invention, since the semiconductor device of the present invention is included, high-speed operation and low power consumption operation are possible, and therefore, long-time operation is possible during battery driving.

  According to the semiconductor device of the present invention, the area where the diffusion layer and the well region are in contact with each other is such that the diffusion region exposed from the well region is exposed by the element isolation region formed obliquely with respect to the surface of the diffusion layer. By making it smaller than the surface area, the parasitic capacitance can be reduced, and low power consumption operation and high speed operation are possible.

  In addition, the element isolation region of a B-DTMOSFET (Bulk Dynamic Threshold MOSFET) using a bulk semiconductor substrate has a junction area between the shallow well region and the deep well region, and the shallow well region is the element on the semiconductor substrate. By forming it in an oblique direction so as to be smaller than the area surrounded by the isolation region, particularly at an acute angle with respect to the surface of the shallow well region on the gate electrode side, the parasitic capacitance and the parasitic problem which are problems in the B-DTMOSFET are obtained. Leakage current of the vertical bipolar element can be reduced, and high speed operation and low power consumption operation are possible.

  Further, in the B-DTMOSFET, in the cross section of the channel region in the gate length direction, an element formed in an oblique direction with respect to the surface of the shallow well region from the right side of the gate electrode toward the direction immediately below the gate electrode. The isolation region and the element isolation region formed in an oblique direction with respect to the surface of the shallow well region from the left side of the gate electrode toward the direction directly below the gate electrode are connected directly below the gate electrode, An isolation region formed in an oblique direction with respect to the surface of the shallow well region from the right side of the gate electrode to a direction directly below the gate electrode in a cross section in the gate length direction near the well contact portion; and the gate It is formed in an oblique direction with respect to the surface of the shallow well region from the left side of the electrode to the direction directly below the gate electrode. The element isolation region is isolated immediately below the gate electrode, so that the capacitance between the deep well region and the shallow well region and the parasitic vertical bipolar device, which were problems in the B-DTMOSFET, are significantly reduced. Further high speed operation and low power consumption operation became possible.

  Further, in the B-DTMOSFET, the shallow well region is electrically isolated from the semiconductor substrate by the element isolation region formed in an oblique direction with respect to the surface of the shallow well region, thereby causing a problem in the B-DTMOSFET. The capacitance between the deep well region and the shallow well region and the parasitic vertical bipolar element were not formed at all, and further high-speed operation and low power consumption operation became possible.

  Further, according to the semiconductor manufacturing apparatus of the present invention, ions can be incident on the substrate to be processed from an oblique direction using an electric field or a magnetic field, and the surface of the substrate to be processed, which has been difficult with a conventional plasma etching apparatus, can be obtained. Thus, the etching can be performed in an oblique direction.

  In addition, when a normal MOSFET is formed using the semiconductor manufacturing apparatus, the element isolation region can be formed in an oblique direction so as to be an acute angle with respect to the substrate surface on the gate electrode side, and the source region and the drain region can be parasitic. Since the capacity can be reduced, there is an effect that high speed operation is possible.

  According to the semiconductor manufacturing method of the present invention, since the plasma etching process is performed on the substrate to be processed in a state where an electric field or a magnetic field in a direction parallel to the substrate to be processed is applied, the substrate to be processed is inclined. The etching shape is formed well.

  In addition, according to the portable information terminal device of the present invention, since the semiconductor device of the present invention is used, high-speed operation and low power consumption operation are possible, so that the battery can be used for a long time. There is.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 shows a cross-sectional view of a first embodiment of a semiconductor device of the present invention. In FIG. 1A, the cross-sectional shape of the element isolation region 9 is an inverted V shape, and in FIG. 1B, the cross-sectional shape of the element isolation region 9 is a trapezoidal shape.

  As shown in FIGS. 1A and 1B, the semiconductor device includes a semiconductor substrate 1, an element isolation region 9, a first conductivity type well region 8 provided in the semiconductor substrate 1, And a second conductivity type diffusion layer 14 formed in the first conductivity type well region 8. In the first embodiment, the first conductivity type is P-type, and the second conductivity type is N-type.

  The element isolation region 9 is formed so that the area where the diffusion layer 14 and the well region 8 are in contact with each other is smaller than the surface area of the diffusion layer 14 exposed from the well region 8. Specifically, the element isolation region 9 is formed in an oblique direction with respect to the surface of the well region 8 so that the distance between both sides of the element isolation region 9 increases toward the semiconductor substrate 1 side.

  According to the semiconductor device having the above configuration, since the junction area between the diffusion layer 14 and the well region 8 is reduced, the parasitic capacitance between the diffusion layer 14 and the well region 8 is reduced, resulting in a low level. Power consumption operation and high-speed operation are possible.

  Next, a semiconductor manufacturing apparatus and a semiconductor manufacturing method for forming the element isolation region 9 in the oblique direction with respect to the surface of the semiconductor substrate 1 in the semiconductor device will be described.

  FIG. 8A is a cross-sectional view showing a schematic structure of a semiconductor manufacturing apparatus. FIG. 8B is a plan view of the vicinity of the lower electrode in FIG. 8A, and FIG. 8C is an explanatory view of oblique etching.

  In the semiconductor manufacturing apparatus of the present invention, the first electrode and the second electrode facing each other and the first electrode so as to generate plasma between the first electrode and the second electrode. A high frequency generating power source 26 which is connected to the first electrode or the second electrode and applies a high frequency power, and an electric field generating means 50 which generates an electric field in a direction perpendicular to the direction connecting the first electrode and the second electrode. With.

  More specifically, the semiconductor manufacturing apparatus includes a vacuum chamber 21 having a gas introduction port 28 and a gas exhaust port 29, and an upper electrode 23 that is a pair of parallel electrodes disposed in the vacuum chamber 21 so as to face each other. And a lower electrode 22, a blocking capacitance 25 connected to the lower electrode 22, and a high frequency generating power source 26. A substrate to be processed 24 is disposed on the lower electrode 22. The upper electrode 23 is grounded to the earth potential. The semiconductor manufacturing apparatus includes a first electric field generating electrode 27a and a second electric field generating electrode 27b so as to sandwich the lower electrode 22 above and in the vicinity of the lower electrode 22, and the lower electrode An electric field parallel to the surface of the substrate to be processed 24 is applied in the vicinity of 22.

  The first and second electric field generating electrodes 27a and 27b constitute the electric field generating means 50, and the lower electrode 22 and the upper electrode 23 are examples of the first electrode and the second electrode. is there.

  Next, the etching process of the substrate 24 to be processed (that is, the semiconductor manufacturing method of the present invention) using the semiconductor manufacturing apparatus will be described.

  First, the substrate to be processed 24 patterned with the resist 10 is disposed on the surface of the lower electrode 22, an etching gas is introduced into the vacuum chamber 21 through the gas introduction port 28, and then the first and first After applying a voltage to the two electric field generating electrodes 27a and 27b so that a constant electric field is applied in the vicinity of the lower electrode 22, high frequency power is applied from the high frequency generating power source 26 to the lower electrode 22.

  Then, a plasma 31 is generated between the upper electrode 23 and the lower electrode 22, and the plasma 31 is changed to a positive potential (Vp) called a plasma potential due to a difference in mass between ions and electrons, and the lower electrode 22. The electrode 22 is charged in a self-aligned manner to a negative potential (Vdc) called a self-bias voltage. Ions are accelerated by an electric field (referred to as E1) perpendicular to the substrate 24 generated by this potential difference (Vp + Vdc), impacting the surface of the substrate 24 on the lower electrode 22; Etching proceeds.

  Here, in addition to the plasma electric field E1 formed perpendicularly to the substrate to be processed 24 by the plasma 31, a voltage is applied to the first and second electric field generating electrodes 27a and 27b, whereby A constant electric field (E2) is applied in a direction parallel to the surface of the processing substrate 24. Then, as shown in FIG. 8C, the ions are accelerated in an oblique direction with respect to the substrate to be processed 24 by the electric field E of the vector sum of E1 and E2, and collide with the substrate to be processed 24.

  By such a method, it has become possible to perform etching in an oblique direction with respect to the substrate to be processed, which has been difficult with a conventional semiconductor manufacturing apparatus. It is possible to perform etching at an arbitrary angle by adjusting the voltage applied to the first and second electric field generating electrodes 27a and 27b.

  In order to obtain the shape of the element isolation region shown in FIG. 1A, the voltages applied to the first and second electric field generating electrodes 27a and 27b in FIG. This can be achieved by reversing the electric field E2 in c) from left to right.

  As shown in FIG. 8, the semiconductor manufacturing apparatus includes a rotating means 70 (such as a motor) that rotates the lower electrode 22 around a direction connecting the upper electrode 23 and the lower electrode 22. Specifically, as shown in FIG. 8B, the lower electrode 22 can freely rotate with respect to an axis that passes through the center of the substrate 24 to be processed and is perpendicular to the surface of the substrate 24 to be processed. It has a structure. Thus, by rotating the substrate to be processed 24 during etching, the element isolation region shape shown in FIG. 1A can be formed.

  Further, as shown in FIG. 8, by adjusting the voltage applied to the first and second electric field generating electrodes 27a and 27b, and gradually changing the electric field E2 in FIG. It is also possible to obtain the element isolation shape shown in FIG.

(Second Embodiment)
FIG. 2 shows a cross-sectional view of a second embodiment of the semiconductor device of the present invention. This semiconductor device is an N-type MOSFET formed on a semiconductor substrate 1, and includes a semiconductor substrate 1, an element isolation region 9, and a first conductivity type (P-type) well provided on the semiconductor substrate 1. A region 8, a gate insulating film 4 formed on the well region 8, a gate electrode 5 formed on the gate insulating film 4, and the well region 8 sandwiching the gate electrode 5. A source region 6a and a drain region 6b of the second conductivity type (N type) and a channel region 3 formed between the source region 6a and the drain region 6b are provided.

  The element isolation region 9 is formed in an oblique direction so as to have an acute angle with respect to the surface of the well region 8 on the gate electrode 5 side in the cross section in the gate length direction.

  According to the semiconductor device (MOSFET) having the above configuration, since the element isolation region 9 is formed in an oblique direction with respect to the surface of the well region 8 on the gate electrode 5 side, the source region 6a 2 and the parasitic capacitance 17b between the drain region 6b and the well region 8, the element isolation region 9 indicated by a virtual line in FIG. Compared with the case where the vertical area is formed, the virtual areas 18a and 18b become smaller. Therefore, also in the MOSFET, the parasitic capacitance in the diffusion layer region is reduced, and high speed operation and low power consumption operation are possible.

  The virtual area 18 a is a junction region between the source region 6 a and the well region 8 that can be reduced by forming the element isolation region 9 obliquely. The virtual area 18b is a junction region between the drain region 6b and the well region 8 that can be reduced by forming the element isolation region 9 obliquely.

  In the second embodiment, the case of an N-type MOSFET has been described. However, it is apparent that the present invention can be similarly applied to a P-type MOSFET by reversing the polarity of the conductivity type.

  Next, a semiconductor manufacturing apparatus and a semiconductor manufacturing method for manufacturing the element isolation region 9 oblique to the surface of the semiconductor substrate 1 in the semiconductor device will be described.

  FIG. 9A is a cross-sectional view showing a schematic structure of a semiconductor manufacturing apparatus. FIG. 9B is a plan view of the vicinity of the lower electrode in FIG. 9A, and FIG. 9C is an explanatory diagram of oblique etching.

  In the semiconductor manufacturing apparatus of the present invention, the first electrode and the second electrode facing each other and the first electrode so as to generate plasma between the first electrode and the second electrode. A high frequency generating power source 26 which is connected to the first electrode or the second electrode and applies a high frequency power, and a magnetic field generating means 60 which generates a magnetic field in a direction perpendicular to the direction connecting the first electrode and the second electrode. With.

  More specifically, the semiconductor manufacturing apparatus includes a vacuum chamber 21 having a gas introduction port 28 and a gas exhaust port 29, and an upper electrode 23 that is a pair of parallel electrodes disposed in the vacuum chamber 21 so as to face each other. And a lower electrode 22, a blocking capacitance 25 connected to the lower electrode 22, and a high frequency generating power source 26. A substrate to be processed 24 is disposed on the lower electrode 22. The upper electrode 23 is grounded to the earth potential. The semiconductor manufacturing apparatus includes a first magnetic field generating coil 30a and a second magnetic field generating coil 30b so as to sandwich the lower electrode 22 above and in the vicinity of the lower electrode 22, and the lower electrode. A magnetic field parallel to the surface of the substrate to be processed 24 is applied in the vicinity of 22.

  The first and second magnetic field generating coils 30a and 30b constitute the magnetic field generating means 60, and the lower electrode 22 and the upper electrode 23 are examples of the first electrode and the second electrode. is there.

  Next, the etching process of the substrate 24 to be processed (that is, the semiconductor manufacturing method of the present invention) using the semiconductor manufacturing apparatus will be described.

  First, the substrate to be processed 24 patterned with the resist 10 is disposed on the surface of the lower electrode 22, an etching gas is introduced into the vacuum chamber 21 through the gas introduction port 28, and then the first and first A current is passed through the two magnetic field generating coils 30 a and 30 b so that a constant magnetic field is applied in the vicinity of the lower electrode 22, and then high frequency power is applied from the high frequency generating power supply 26 to the lower electrode 22.

  Then, a plasma 31 is generated between the upper electrode 23 and the lower electrode 22, a potential difference (Vp + Vdc) is generated between the upper electrode 23 and the lower electrode 22, and ions are supplied to the substrate to be processed. Accelerate towards 24. At this time, ions accelerated by a magnetic field parallel to the substrate to be processed 24 in the vicinity of the lower electrode 22 generated by passing current through the first and second magnetic field generating coils 30a and 30b. Qv × B (q is the amount of elementary charges, v is the velocity of ions, and B is the magnetic flux density) in a direction parallel to the substrate to be processed 24. As a result, ions are applied to the surface of the substrate to be processed 24. On the other hand, it proceeds in an oblique direction.

  As described above, etching in an oblique direction with respect to the surface of the substrate to be processed, which was difficult with a conventional apparatus, can be performed. It is possible to perform etching at an arbitrary angle with respect to the substrate to be processed 24 by adjusting the amount of current flowing through the first and second magnetic field generating coils 30a and 30b. Further, the rotating means 70 allows the lower electrode 22 to freely pass through the center of the substrate to be processed 24 and perpendicular to the surface of the substrate to be processed 24 as shown in FIG. 9B. Therefore, the substrate can be etched in any direction.

  By using the semiconductor manufacturing apparatus and the manufacturing method, the shape of the element isolation region 9 in an oblique direction with respect to the surface of the semiconductor substrate 24 can be obtained as shown in FIG. The magnetic field generating coils 30a and 30b may be magnets.

(Third embodiment)
FIG. 3 shows a cross-sectional view of a third embodiment of the semiconductor device of the present invention. 3A is a plan view of the B-DTMOSFET in this embodiment, and FIG. 3B is a cross-sectional view taken along the cutting line AA ′ in FIG. FIG. 3C is a cross-sectional view taken along the cutting line BB ′ in FIG.

  The semiconductor device is an N-type B-DTMOSFET (Bulk Dynamic Threshold Voltage MOSFET) formed on a semiconductor substrate 1, and includes the semiconductor substrate 1, the element isolation region 9, and the above-described semiconductor device. A second conductivity type (N type) deep well region 7 provided in the semiconductor substrate 1 and a first conductivity type (P type) shallow well region 8 formed in the second conductivity type deep well region 7. A gate insulating film 4 formed on the first conductivity type shallow well region 8, and the first conductivity type shallow well region 7 and well contact portion 11 formed on the gate insulating film 4. A gate electrode 5 electrically connected through the first conductive type shallow well region 8, a second conductive type source region 6a and a drain region 6b formed in the shallow well region 8, and the source region 6a and the drain region 6b. And a channel region 3 formed between the in-area 6b.

  The element isolation region 9 is formed so that the area where the shallow well region 8 and the deep well region 7 are in contact with each other is smaller than the surface area of the shallow well region 8 exposed from the deep well region 7.

  More specifically, the element isolation region 9 is formed in an oblique direction so as to have an acute angle with respect to the surface of the shallow well region 8 on the gate electrode 5 side in the cross section in the gate length direction. The shallow well region 8 is electrically isolated from the adjacent shallow well region 8 ′ by the element isolation region 9. A portion surrounded by the element isolation region 9 formed in the oblique direction is an element region.

  As described above, in the B-DTMOSFET, the shallow well region 8 and the gate electrode 5 are electrically connected. Therefore, in order to operate the element independently, adjacent shallow well regions are electrically separated from each other. Need to be.

  Here, the element isolation region 9 is formed so that its cross section is line symmetric. As a result, even when it is desired to form an element on another adjacent shallow well region 8 ′, it is possible to obtain the element isolation region 9 having an acute angle with respect to the substrate surface on the gate electrode 5 side in the element.

  The gate electrode 5 has a well contact portion 11 which is an opening, and a tungsten plug 13 (which is an example of a plug) is fitted into the well contact portion 11, and the tungsten plug 13 is shallow. It is in contact with a well region diffusion layer 12 formed in the well region 8. Thus, the gate electrode 5 is electrically connected to the shallow well region 8 through the tungsten plug 13.

  According to the semiconductor device having the above configuration, the element isolation region 9 is formed in an oblique direction with an acute angle with respect to the surface of the shallow well region 8 on the gate electrode 5 side, as shown in FIG. The parasitic capacitance 17a between the source region 6a and the shallow well region 8, and the parasitic capacitance 17b between the drain region 6b and the shallow well region 8, the element isolation region 9 is the shallow well region. Compared to the case of the conventional example formed perpendicularly to the eight surfaces (shown by phantom lines in FIG. 7), the imaginary areas 18a and 18b become smaller. Further, the element isolation region 9 is formed in an oblique direction with an acute angle with respect to the surface of the shallow well region 8 on the gate electrode 5 side, so that as shown in FIG. Compared to the case where the parasitic capacitance 15 between the deep well region 7 and the element isolation region 9 is formed perpendicular to the surface of the shallow well region 8 (shown by phantom lines in FIG. 7). The virtual area is reduced by 16 times. For this reason, the parasitic capacitance between them becomes small, and high-speed operation and low power consumption operation become possible.

  The virtual area 18 a is a junction region between the source region 6 a and the well region 8 that can be reduced by forming the element isolation region 9 obliquely. The virtual area 18b is a junction region between the drain region 6b and the well region 8 that can be reduced by forming the element isolation region 9 obliquely. The virtual area 16 is a junction region between the shallow well region 8 and the deep well region 7 that can be reduced by forming the element isolation region 9 obliquely.

  Further, by forming the element isolation region 9 obliquely with respect to the surface of the shallow well region 8, the deep well region 7 (N type), which is a problem in the B-DTMOSFET using a bulk semiconductor substrate, is shallow. Between the deep well region 7 corresponding to the collector and the shallow well region 8 of the NPN type parasitic bipolar element formed of the well region 8 (P type) and the source region 6a or the drain region 6b (N type). The junction area can be reduced, and the parasitic bipolar element current that does not become an effective current for transistor operation can be reduced.

  Here, the junction between the deep well region 7 and the shallow well region 8 is located near the lower end of the element isolation region 9 and above the lower end of the element isolation region 9. Since the junction area with the shallow well region 8 is the smallest, higher speed and lower power consumption operation can be expected.

  Furthermore, since the distance between the gate electrode 5 and the element isolation region 9 is about the same as the conventional example, the stress of the element isolation region 9 does not deteriorate the channel mobility. As described above, in the semiconductor device of the present invention, the junction area between the shallow well region 8 and the deep well region 7 is reduced without reducing the driving force of the element due to the stress of element isolation, so that the parasitic capacitance is reduced. It is possible to reduce the longitudinal bipolar leakage current.

  Next, a specific example of the manufacturing method of the semiconductor device will be described with reference to FIG. In this embodiment, an N-type B-DTMOSFET using a bulk substrate is shown. Here, FIG. 4A shows a plan view of the B-DTMOSFET after completion of this embodiment. 4 (b1), FIG. 4 (c1), FIG. 4 (d1), FIG. 4 (e1), and FIG. 4 (f1) are cut along the cutting line BB ′ shown in FIG. 4 (a). The manufacturing process sectional drawing of is shown. 4 (b2), FIG. 4 (c2), FIG. 4 (d2), FIG. 4 (e2), and FIG. 4 (f2) are cut along the cutting line AA ′ shown in FIG. 4 (a). The manufacturing process sectional drawing of is shown.

  First, as shown in FIGS. 4B1 and 4B2, a pad oxide film 19 of about 5 to 30 nm is formed by thermally oxidizing the semiconductor substrate 1 in an oxygen atmosphere at about 850 ° C. Then, the SiN film 20 is deposited to a thickness of about 100 to 200 nm by the CVD (Chemical Vapor Deposition) method. The pad oxide film 19 serves as a buffer film for preventing the semiconductor substrate 1 and the SiN film 20 from being in direct contact with each other, and serves as a protective film when the SiN film 20 is later removed with phosphoric acid. . Further, the SiN film 20 serves as an etch stopper in a later CMP (Chemical Mechanical Polishing) process, and also serves as a mask when the semiconductor substrate 1 is etched in an oblique direction later.

  Thereafter, as shown in FIGS. 4C1 and 4C2, the SiN film 20 is patterned using a resist, and the SiN film 20 is formed by RIE (Reactive Ion Etching) which is a normal anisotropic etching. The pad oxide film 19 is sequentially etched, and then the resist is removed. Thereafter, etching is performed in an oblique direction with respect to the surface of the semiconductor substrate 1 using the semiconductor manufacturing apparatus shown in FIG. The depth of the element isolation region 9 etched in the oblique direction from the surface of the semiconductor substrate 1 electrically isolates the adjacent shallow well regions 8 and 8, and the deep well region 7 electrically It is desirable that the thickness is about 300 to 700 nm so as not to separate. At this time, the process is performed while rotating the substrate to be processed 24 in FIG. 8 or 9 so that the element isolation region 9 to be formed later is formed as a contrast. As another method of etching in an oblique direction with respect to the surface of the substrate to be processed 24, gallium ions accelerated to about 500 eV are applied to the substrate to be processed 24 set at an angle inclined with respect to the gallium ion beam. Alternatively, a normal physical etching method performed by irradiating the surface may be used.

  Thereafter, as shown in FIGS. 4D1 and 4D2, grooves etched by depositing an oxide film by a CVD method are filled, and the surface is flattened by CMP or the like. Thereafter, the SiN film 20 is removed by wet etching with phosphoric acid, and then the pad oxide film 19 is removed by a wet etching process with hydrofluoric acid, thereby forming the element isolation region 9.

Next, as shown in FIGS. 4 (e1) and 4 (e2), an N-type deep well region 7 is formed by implanting phosphorus ions at an implantation energy of 300 to 600 keV and a dose of about 5e12 to 3e13 cm ^−2. To do. Thereafter, a P-type shallow well region 8 is formed by implanting boron ions at an implantation energy of 50 to 100 keV and a dose of about 1e13 to 5e13 cm ⁻² . Here, the implantation conditions are adjusted so that the junction between the N-type deep well region 7 and the P-type shallow well region 8 is formed near the lower end of the element isolation region 9 and at the upper position. To do. In this way, the parasitic capacitance between the deep well region 7 and the shallow well region 8 is minimized, and the parasitic vertical bipolar device current that causes a problem in the B-DTMOSFET can be reduced.

  Thereafter, the surface of the semiconductor substrate 1 is thermally oxidized at about 800 ° C. in an oxygen atmosphere to form a gate insulating film 4 of about 2 nm. Then, polysilicon is deposited on the entire surface of the wafer by the CVD method to a thickness of about 200 nm. After patterning using a resist, the gate electrode 5 is formed by etching. Here, the gate electrode 5 includes a well contact portion 11 which is an opening window for electrically connecting the gate electrode 5 and the shallow well region 8 later, and the source region 6a and the drain region 6b. It is formed other than on the region sandwiched between the two.

Next, as shown in FIGS. 4 (f1) and 4 (f2), openings are provided in the source region 6a and the drain region 6b using a resist, and arsenic ions are implanted at an energy of about 15 to 30 keV and a dose amount. N @ + regions are formed by implantation at 1e15 to 1e16 cm ^<-2 >. Next, an opening is formed in the well contact portion 11 using a resist, and boron ions are implanted at an implantation energy of about 10 keV and a dose of about 1e15 to 1e16 cm ⁻² to form a P + type well region diffusion layer 12. Here, the P + type well region diffusion layer 12 is formed only in the vicinity of the well contact portion 11 so as not to contact the N + type source region 6a and drain region 6b. This is because a tunnel current flows between the P + region and the N + region. Here, the surface layer of the source region 6a, the drain region 6b, and the gate electrode 5 may be silicided in order to lower the resistance and improve the conductivity with the wiring connected to each. . Examples of the silicide include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, and the like. Thereafter, impurity activation annealing is performed. The activation annealing is performed by RTA (Rapid Thermal Annealing) so that the impurities are sufficiently activated and the impurities do not diffuse excessively at a temperature of about 1000 ° C. and for a time of about 10 seconds.

  Next, after the insulating film 32 is deposited on the entire surface, the insulating film 32 of the well contact portion 11 is removed by a patterning and etching process using a resist. Thereafter, the well contact portion 11 is filled with a tungsten plug 13, and the gate electrode 5 and the shallow well region 8 are electrically connected. Thereafter, a normal metal process is performed to complete a B-DTMOSFET using a bulk substrate.

  In this way, the element isolation region 9 is formed in an oblique direction with respect to the surface of the shallow well region 8 on the gate electrode 5 side, thereby causing a problem in the B-DTMOSFET using a bulk substrate. The parasitic capacitance between the region 6a and the drain region 6b and the shallow well region 8 and the parasitic capacitance between the shallow well region 8 and the deep well region 7 can be greatly reduced, and high speed operation can be achieved. Is possible. Further, a parasitic bipolar element formed of an N-type deep well region 7, a P-type shallow well region 8, an N-type source region 6a or a drain region 6b, which has been a problem in a B-DTMOSFET using a bulk substrate. The leakage current component not related to the transistor operation can be greatly reduced, and the low power consumption operation becomes possible.

  In this embodiment, the case of the N-type B-DTMOSFET has been described. However, it is obvious that the present invention can be similarly applied to the P-type B-DTMOSFET by reversing the polarity of the conductivity type.

  Further, when a portable information terminal device (such as a mobile phone) is configured using the semiconductor device of the present invention, as described above, high-speed operation and low power consumption operation are possible. Can be used.

(Fourth embodiment)
FIG. 5 shows a cross-sectional view of a fourth embodiment of the semiconductor device of the present invention. 5A is a plan view of the B-DTMOSFET in this embodiment, and FIG. 5B is a cross-sectional view taken along the cutting line AA ′ in FIG. FIG. 5C is a cross-sectional view taken along the cutting line BB ′ in FIG.

  The semiconductor device is an N-type B-DTMOSFET (Bulk Dynamic Threshold Voltage MOSFET) formed on a semiconductor substrate 1, and includes the semiconductor substrate 1, the element isolation region 9, and the above-described semiconductor device. A second conductivity type (N type) deep well region 7 provided in the semiconductor substrate 1 and a first conductivity type (P type) shallow well region 8 formed in the second conductivity type deep well region 7. A gate insulating film 4 formed on the first conductivity type shallow well region 8, and the first conductivity type shallow well region 7 and well contact portion 11 formed on the gate insulating film 4. A gate electrode 5 electrically connected through the first conductive type shallow well region 8, a second conductive type source region 6a and a drain region 6b formed in the shallow well region 8, and the source region 6a and the drain region 6b. And a channel region 3 formed between the in-area 6b.

  In particular, as shown in FIG. 5C, the shallow well region extends from one side (right side) of the gate electrode 5 to a direction directly below the gate electrode 5 in the cross section of the channel region 3 in the gate length direction. The element isolation region 9 formed in an oblique direction with respect to the surface 8 and the surface of the shallow well region 8 from the other side (left side) of the gate electrode 5 to the direction directly below the gate electrode 5 The element isolation region 9 formed in an oblique direction is connected directly below the gate electrode 5.

  In particular, as shown in FIG. 5B, in the cross section in the gate length direction near the well contact portion 11, the side from the one side (right side) of the gate electrode 5 to the direction directly below the gate electrode 5 An isolation region 9 formed obliquely with respect to the surface of the shallow well region 8, and the surface of the shallow well region 8 from the other side (left side) of the gate electrode 5 toward the direction directly below the gate electrode 5 The element isolation region 9 formed in an oblique direction is isolated immediately below the gate electrode 5.

  In order to achieve such a configuration, it is preferable to narrow the interval between the element isolation regions 9 in the channel region 3 and widen the interval between the element isolation regions 9 in the vicinity of the well contact portion 11.

  According to the semiconductor device having the above configuration, the element isolation region 9 is formed obliquely with respect to the surface of the shallow well region 8 on the gate electrode 5 side so as to form an acute angle. Similarly, the junction capacitance (parasitic capacitance) between the source region 6a and the drain region 6b and the shallow well region 8 is reduced, and high-speed operation is possible.

  The element isolation region 9 under the channel region 3 is connected, and the shallow well region 8 in the channel region 3 is electrically isolated from the deep well region 7. And the parasitic vertical bipolar element between the shallow well region 8 and the shallow well region 8 are formed only directly below the well contact portion 11. Therefore, since the junction capacitance and the leakage current due to the parasitic vertical bipolar element are remarkably reduced, further high-speed operation and low power consumption operation are possible as compared with the third embodiment.

  The element isolation region 9 in the vicinity of the well contact portion 11 is isolated immediately below the gate electrode 5, so that the shallow well region 8 in the vicinity of the well contact portion 11 is physically connected to the semiconductor substrate 1. And is also physically connected to the channel region 3. Therefore, when the element isolation region 9 in the vicinity of the channel region 3 is formed by etching, the channel region 3 does not fall down.

  In this embodiment, the case of the N-type B-DTMOSFET has been described. However, it is obvious that the present invention can be similarly applied to the P-type B-DTMOSFET by reversing the polarity of the conductivity type.

(Fifth embodiment)
FIG. 6 shows a cross-sectional view of a fifth embodiment of the semiconductor device of the present invention. 6A is a plan view of the B-DTMOSFET in this embodiment, and FIG. 6B is a cross-sectional view taken along the cutting line AA ′ in FIG. 6A. FIG. 6C is a cross-sectional view taken along the cutting line BB ′ in FIG.

  The semiconductor device is an N-type B-DTMOSFET (Bulk Dynamic Threshold Voltage MOSFET) formed on a semiconductor substrate 1, and includes the semiconductor substrate 1, the element isolation region 9, and the above-described semiconductor device. A first conductivity type (P type) (shallow) well region 8 provided on the semiconductor substrate 1, a gate insulating film 4 formed on the well region 8, and a gate insulating film 4 formed on the gate insulating film 4. A gate electrode 5 electrically connected to the well region 8 through the well contact portion 11, a second conductivity type (N-type) source region 6a and a drain region 6b formed in the well region 8, And a channel region 3 formed between the source region 6a and the drain region 6b.

  In the cross section in the gate length direction, an element isolation region 9 formed obliquely with respect to the surface of the well region 8 from one side (right side) of the gate electrode 5 to a direction directly below the gate electrode 5; The element isolation region 9 formed obliquely with respect to the surface of the well region 8 from the other side (left side) of the gate electrode 5 to the direction directly below the gate electrode 5 is the gate electrode 5 The channel region 3 is electrically isolated from the semiconductor substrate 1.

  According to the semiconductor device having the above configuration, the element isolation region 9 is formed obliquely with respect to the surface of the well region 8 on the gate electrode 5 side so as to form the case of the third embodiment. Similarly, the junction capacitance between the source region 6a and drain region 6b and the shallow well region 8 is reduced, and high speed operation is possible.

  Further, since the well region 8 and the semiconductor substrate 1 are electrically separated, the junction between the shallow well region 8 and the deep well region 7 shown in the third embodiment is used. Capacitance and parasitic vertical bipolar elements are not formed. Therefore, in the case of the fifth embodiment, since the leakage current due to the junction capacitance and the parasitic vertical bipolar element is completely eliminated, further higher speed operation and lower consumption than the third and fourth embodiments. Power operation is possible.

  Further, since the well region 8 and the semiconductor substrate 1 are electrically separated, it is not necessary to form the deep well region 7, and the manufacturing process can be simplified.

  In the step of forming the element isolation region 9 by etching, if the etching process is performed at once, the channel region 3 is physically separated from the semiconductor substrate 1. Only one of the element isolation regions 9 is processed by etching and then filled with an oxide film. Thereafter, the other element isolation region 9 is processed by etching and buried with an oxide film, whereby a structure in which the well region 8 is electrically isolated from the semiconductor substrate 1 can be formed.

  In this embodiment, the case of the N-type B-DTMOSFET has been shown. However, it is obvious that the present invention can be similarly applied to the P-type B-DTMOSFET by reversing the polarity of the conductivity type.

It is sectional drawing which shows 1st Embodiment of the semiconductor device of this invention. It is sectional drawing which shows 2nd Embodiment of the semiconductor device of this invention. It is sectional drawing which shows 3rd Embodiment of the semiconductor device of this invention. It is explanatory drawing explaining the manufacturing method of 3rd Embodiment of the semiconductor device of this invention. It is sectional drawing which shows 4th Embodiment of the semiconductor device of this invention. It is sectional drawing in 5th Embodiment of the semiconductor device of this invention. FIG. 4 is an explanatory diagram for explaining a reduction in parasitic capacitance by forming an element isolation region obliquely in the B-DTMOSFET having the structure of FIG. 3. It is a schematic structure figure showing one embodiment of a semiconductor manufacturing device of the present invention. It is a schematic structure figure showing other embodiments of the semiconductor manufacturing device of the present invention. It is a schematic structure diagram showing a semiconductor device which is a conventional diffusion layer wiring. FIG. 6 is a schematic structural diagram showing a semiconductor device in which a conventional diffusion layer wiring is improved by using an element isolation region. It is a schematic structure figure which shows the conventional etching apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3 Channel region 4 Gate insulating film 5 Gate electrode 6a Source region 6b Drain region 7 Deep well region 8 Shallow well region 9 Element isolation region 10 Resist 11 Well contact portion 12 Well region diffusion layer 13 Tungsten plug 14 Diffusion layer 15 Shallow Parasitic capacitance between well region and deep well region 16 Junction region between shallow well region and deep well region which can be reduced by forming element isolation region obliquely 17a Parasitic between source region and shallow well region Capacitance 17b Parasitic capacitance between the drain region and the shallow well region 18a Junction region between the source region and the shallow well region that can be reduced by forming the element isolation region diagonally 18b By forming the element isolation region diagonally Reduced drain region and shallow well 19 Pad oxide film 20 SiN film 21 Vacuum chamber 22 Lower electrode 23 Upper electrode 24 Substrate 25 Blocking capacitance 26 High frequency generating power source 27a First electric field generating electrode 27b Second electric field generating Electrode 28 Gas introduction port 29 Gas exhaust port 30a First magnetic field generating coil 30b Second magnetic field generating coil 31 Plasma 32 Insulating film 50 Electric field generating means 60 Magnetic field generating means 70 Rotating means

Claims (13)

A semiconductor substrate;
An element isolation region;
A first conductivity type well region provided in the semiconductor substrate;
A diffusion layer of a second conductivity type formed in the well region of the first conductivity type,
The element isolation region is formed so that an area where the diffusion layer and the well region are in contact with each other is smaller than a surface area of the diffusion layer exposed from the well region. A semiconductor substrate;
An element isolation region;
A first conductivity type well region provided in the semiconductor substrate;
A gate insulating film formed on the first conductivity type well region;
A gate electrode formed on the gate insulating film;
A second conductivity type source region and drain region formed in the first conductivity type well region;
A channel region formed between the source region and the drain region,
The semiconductor device is characterized in that the element isolation region is formed in an oblique direction so as to form an acute angle with respect to the surface of the well region on the gate electrode side in a cross section in the gate length direction. A semiconductor substrate;
An element isolation region;
A second well-type deep well region provided on the semiconductor substrate;
A first well type shallow well region formed in the second well type deep well region;
A gate insulating film formed on the first conductivity type shallow well region;
A gate electrode formed on the gate insulating film and electrically connected to the shallow well region of the first conductivity type through the well contact portion;
A second conductivity type source region and drain region formed in the first conductivity type shallow well region;
A channel region formed between the source region and the drain region,
The element isolation region is formed so that an area where the shallow well region and the deep well region are in contact with each other is smaller than a surface area of the shallow well region exposed from the deep well region. . The semiconductor device according to claim 3.
The element isolation region is formed in an oblique direction so as to have an acute angle with respect to the surface of the shallow well region on the gate electrode side in the cross section in the gate length direction,
The semiconductor device according to claim 1, wherein a junction between the shallow well region and the deep well region is in the vicinity of the lower end of the element isolation region. The semiconductor device according to claim 4,
In the cross section of the channel region in the gate length direction, an element isolation region formed obliquely with respect to the surface of the shallow well region from one side of the gate electrode toward a direction directly below the gate electrode, and The element isolation region formed in an oblique direction with respect to the surface of the shallow well region from the other side of the gate electrode toward the direction directly below the gate electrode is connected directly below the gate electrode,
An isolation region formed in an oblique direction with respect to the surface of the shallow well region from one side of the gate electrode to a direction directly below the gate electrode in a cross section in the gate length direction near the well contact portion; The element isolation region formed obliquely with respect to the surface of the shallow well region from the other side of the gate electrode toward the direction directly below the gate electrode is isolated immediately below the gate electrode. A semiconductor device. A semiconductor substrate;
An element isolation region;
A first conductivity type well region provided in the semiconductor substrate;
A gate insulating film formed on the first conductivity type well region;
A gate electrode formed on the gate insulating film and electrically connected to the well region of the first conductivity type through the well contact portion;
A second conductivity type source region and drain region formed in the first conductivity type well region;
A channel region formed between the source region and the drain region,
In the cross section in the gate length direction, an element isolation region formed obliquely with respect to the surface of the well region from one side of the gate electrode to a direction directly below the gate electrode, and another gate electrode The element isolation region formed obliquely with respect to the surface of the well region from the side toward the direction directly below the gate electrode is connected directly below the gate electrode,
The semiconductor device, wherein the channel region is electrically isolated from the semiconductor substrate. A pair of opposing first and second electrodes;
A high frequency generating power source that is connected to the first electrode or the second electrode and applies high frequency power so as to generate plasma between the first electrode and the second electrode;
A semiconductor manufacturing apparatus comprising: an electric field generating means for generating an electric field in a direction perpendicular to a direction connecting the first electrode and the second electrode. A pair of opposing first and second electrodes;
A high frequency generating power source that is connected to the first electrode or the second electrode and applies high frequency power so as to generate plasma between the first electrode and the second electrode;
A semiconductor manufacturing apparatus comprising magnetic field generating means for generating a magnetic field in a direction perpendicular to a direction connecting the first electrode and the second electrode. The semiconductor manufacturing apparatus according to claim 7 or 8,
A semiconductor manufacturing apparatus comprising: a rotating means for rotating the first electrode or the second electrode around a direction connecting the first electrode and the second electrode. Arranging a substrate to be processed on an electrode for plasma generation;
And a step of subjecting the substrate to be processed to plasma etching in a state where an electric field parallel to the substrate to be processed is applied in the vicinity of the electrode for generating plasma. Arranging a substrate to be processed on an electrode for plasma generation;
And a step of subjecting the substrate to be processed to plasma etching in a state in which a magnetic field parallel to the substrate to be processed is applied in the vicinity of the electrode for generating plasma.   A semiconductor device manufactured using the semiconductor manufacturing method according to claim 10.   A portable information terminal device comprising the semiconductor device according to any one of claims 1, 2, 3, 4, 5, 6, and 12.

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