CN108206173A - 基底以及具有该基底的电子装置和显示装置 - Google Patents

基底以及具有该基底的电子装置和显示装置 Download PDF

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Publication number
CN108206173A
CN108206173A CN201711349629.7A CN201711349629A CN108206173A CN 108206173 A CN108206173 A CN 108206173A CN 201711349629 A CN201711349629 A CN 201711349629A CN 108206173 A CN108206173 A CN 108206173A
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conductive
conductive layer
layer
convex block
pad
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CN108206173B (zh
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金炳容
李钟赫
黄晸护
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract

提供了一种基底以及具有该基底的电子装置和显示装置。所述基底包括基体基底和位于基体基底的一侧处的垫，其中，垫包括：第一导电图案，位于基体基底上；绝缘层，包括暴露第一导电图案的一部分的多个接触孔；以及第二导电图案，分开位于绝缘层上，并通过所述多个接触孔连接到第一导电图案，其中，第二导电图案的侧表面被暴露。

Description

基底以及具有该基底的电子装置和显示装置
本申请要求于2016年12月16日在韩国知识产权局提交的第10-2016-0172753号韩国专利申请的优先权和权益，该韩国专利申请的全部内容通过引用包含于此。
技术领域
本公开的示例实施例的各方面涉及一种基底、具有该基底的电子装置和显示装置。
背景技术
最近，诸如半导体装置和显示面板的电子装置的高性能和高集成度已经导致在这些电子装置中提供的连接端子的数量显著增加。因此，连接端子的尺寸正在减小，相邻的连接端子之间的距离也在减小。
电子装置可以通过使用诸如各向异性导电膜(ACF)的粘合剂电连接到另一电子装置。然而，当使用ACF连接电子装置时，会在连接端子之间发生短路故障，或者会在电子装置之间发生开路故障。例如，包括在ACF中的导电颗粒可以集中在相邻连接端子(诸如，凸块)的侧表面周围，会在相邻凸块之间发生短路故障。由于ACF中的导电颗粒不接触具有精细尺寸的凸块，因此会在电子装置之间发生开路故障。
发明内容
本公开的示例实施例的各方面涉及一种能够防止由各向异性导电膜的导电颗粒引起的短路故障或开路故障(或者能够减少这样的故障的可能性或程度)的基底以及具有该基底的电子装置和显示装置。
根据本公开的一些示例实施例，基底可以包括基体基底以及设置在基体基底的一侧处的垫，其中，垫包括：第一导电图案，设置在基体基底上；绝缘层，包括暴露第一导电图案的一部分的多个接触孔；以及第二导电图案，分开设置在绝缘层上，并通过所述多个接触孔连接到第一导电图案，其中，第二导电图案的侧表面被暴露。
第二导电图案可以包括顺序堆叠的第一导电层和第二导电层，第一导电层的侧表面可以被暴露。
第二导电层可以包括刚性比包括在第一导电层中的材料的刚性大的材料。
第一导电层可以包括从金(Au)、铝(Al)、铜(Cu)、锡(Sn)和钼(Mo)中选择的至少一种。
第二导电层可以包括从钛(Ti)、钼(Mo)、锡(Sn)、镍(Ni)和导电氧化物中选择的至少一种。
导电氧化物可以包括从氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锑锌(AZO)、氧化铟锡锌(ITZO)、氧化锌(ZnO)和氧化锡(SnO2)中选择的至少一种。
基底还可以包括设置在第一导电层与第一导电图案之间的第三导电层。
第三导电层可以包括从钛(Ti)、钼(Mo)、锡(Sn)、镍(Ni)和导电氧化物中选择的至少一种。第三导电层可以包括与第二导电层的材料相同(例如，基本上相同)的材料。
根据一些实施例，电子装置可以包括：基底，包括基体基底和设置在基体基底上的垫；电子元件，包括连接到垫的凸块，其中，垫包括：第一导电图案，设置在基体基底上；绝缘层，包括暴露第一导电图案的一部分的多个接触孔；以及第二导电图案，分开设置在绝缘层上，并通过所述多个接触孔连接到第一导电图案，其中，第二导电图案中的至少一部分第二导电图案连接到凸块，剩余的第二导电图案的侧表面被暴露。
连接到凸块的第二导电图案可以包括第一导电层。电子装置还可以包括混合导电层，混合导电层设置在第一导电层与凸块之间，并包括第一导电层材料和凸块材料的混合物。
剩余的第二导电图案可以包括第一导电层和设置在第一导电层上的第二导电层，第一导电层的侧表面可以被暴露。
混合导电层可以包括包含第二导电层材料的碎片。
电子装置还可以包括填充与凸块和垫连接的区域不同的区域的非导电膜。
非导电膜可以包括可热流动的聚合物材料。
根据一些实施例，电子装置可以包括：基底，包括基体基底和设置在基体基底上的垫；以及电子元件，包括连接到垫的凸块，其中，垫包括：第一导电图案，设置在基体基底上；绝缘层，包括暴露第一导电图案的一部分的多个接触孔；第二导电图案，分开设置在绝缘层上，并包括通过所述多个接触孔连接到第一导电图案的第一导电层；以及混合导电层，设置在第二导电图案与凸块之间，其中，混合导电层包括第一导电层材料和凸块材料的混合物。
根据一些实施例，显示装置可以包括：显示面板，包括显示区域和非显示区域，其中，显示面板包括设置在非显示区域中的第一垫单元和第二垫单元，第一垫单元包括多个第一垫，第二垫单元包括多个第二垫；第一驱动器，包括连接到第一垫单元的多个第一凸块；柔性印刷电路板，包括连接到第二垫单元的多个第二凸块；以及第二驱动器，连接到柔性印刷电路板的一端，其中，从柔性印刷电路板和第二驱动器中选择的一个包括第三凸块，另一个包括连接到第三凸块的第三垫，其中，第一垫、第二垫和第三垫中的每个包括：第一导电图案；绝缘层，包括暴露第一导电图案的一部分的多个接触孔；以及第二导电图案，分开设置在绝缘层上，并通过所述多个接触孔连接到第一导电图案，其中，第二导电图案中的至少一部分第二导电图案连接到从第一凸块至第三凸块中选择的一者，剩余的第二导电图案的侧表面被暴露。
附图说明
在下文中参照附图对一些示例实施例的各方面进行描述。然而，本系统和方法不应被解释为局限于这些实施例。相反，提供这些实施例以便于被本领域普通技术人员理解。
在附图中，为了清楚，可以夸大附图的尺寸。要理解的是，除非另外指出，否则当元件被称作“在”两个元件“之间”时，该元件可以是所述两个元件之间的唯一的元件，或者也可以存在一个或更多个中间元件。同样的附图标记始终表示同样的元件。
图1是示出根据本公开的实施例的基底的透视图。
图2是图1中示出的垫单元的放大视图。
图3是示出图2中示出的垫中的一个垫的平面图。
图4是沿图3的线I-I'截取的剖视图。
图5是沿图3的线II-II'截取的剖视图。
图6至图7是示出电连接到电子元件的图1至图5中示出的基底的剖视图。
图8是示出图6至图7中示出的混合导电层的概念视图。
图9至图13是示出用于连接图1至图8中示出的基底和电子元件的工艺的剖视图。
图14至图20是示出图1至图5中示出的垫的形状的示例的平面图。
图21是示出根据本公开的实施例的显示装置的透视图。
图22是示出图21中示出的显示面板的平面图。
图23是沿图21的线III-III'截取的剖视图。
图24是图23中示出的区域EA1的放大视图。
图25是沿图21的线IV-IV'截取的剖视图。
图26是图25中示出的区域EA2的放大视图。
图27是沿图21的线V-V'截取的剖视图。
图28是图27中示出的区域EA3的放大视图。
图29是沿图21的线VI-VI'截取的剖视图。
图30是图29中示出的区域EA4的放大视图。
具体实施方式
虽然参照附图描述了本公开的一些示例实施例的各方面，但是将要理解的是，在不脱离本公开的精神和范围的情况下，可以在本公开中做出各种改变和修改。另外，应理解的是，本公开不限于在此公开的实施例，并且在不脱离本公开的精神和范围的情况下，可以做出各种变化、等同物和替代物。
同样的附图标记贯穿附图表示同样的元件。在附图中，为了本公开的清楚，可以夸大元件尺寸。尽管在此使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语限制。这些术语仅用来将一个元件与另一元件区分开。例如，在不脱离本公开的范围的情况下，第一元件可以被指定为第二元件。相似地，第二元件可以被指定为第一元件。另外，除了上下文另外明确地指出，否则单数形式“一个”和“一种”包括复数指代物。
这里，应理解的是，术语“包括”或“具有”是包括特性、数字、步骤、操作、元件、部分或它们的组合，但是不排除一个或更多个不同的特性、数字、步骤、操作、元件、部分或它们的组合。另外，当诸如层、膜、区域或板的元件被称作“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者可以在所述另一元件上且具有一个或更多个中间元件置于其间。另外，当诸如层、膜、区域或板的元件被称作“在”另一元件“下方”时，该元件可以正好在所述另一元件下方，或者在所述另一元件下方且具有一个或更多个中间元件置于其间。在本公开中，术语“基本上”包括完全地、几乎完全地或者在一些情况下并根据本领域的技术人员而达到任何显著程度的含义。另外，“形成在……上”也可以意味着“形成在……上方”。
在此使用的术语仅是为了描述具体实施例的目的，而不意图限制本公开。如这里使用的，除非上下文中另外明确指出，否则单数形式“一个”和“一种”也意图包括复数形式。还将理解的是，当术语“包括”、“包含”用于本说明书中时，说明存在陈述的特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或更多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。如这里使用的，术语“和/或”包括一个或更多个相关所列项的任意组合和所有组合。当诸如“……中的至少一个(种、者)”的表述在一列元件之后时，修饰整列元件，而不是修饰该列的个别元件。
如这里使用的，术语“基本上”、“大约”和相似术语是用作近似术语而不是用作程度术语，并且意图解释可以将被本领域普通技术人员认识的测量值或计算值中的固有偏差。另外，在描述本公开的实施例时“可以”的使用指“本公开的一个或更多个实施例”。如这里所使用的，术语“使用”可以被认为分别与术语“利用”同义。另外，术语“示例性”意图指示例或例证。
在下文中，将参照附图对一些示例实施例的各方面进行更加详细地描述。
图1是示出根据本公开的实施例的基底的透视图。图2是图1中示出的垫单元的放大视图。图3是示出图2中示出的垫中的一个垫的平面图。图4是沿图3的线I-I'截取的剖视图。图5是沿图3的线II-II'截取的剖视图。
参照图1至图5，基底SUB可以包括基体基底BS和设置在基体基底BS的至少一侧上的垫单元PDA。
基体基底BS可以是但不限于从半导体基底、柔性印刷电路板、印刷电路板和显示面板的阵列基底中选择的一种。另外，半导体基底可以是半导体晶圆。然而，半导体基底不限于此。可以改变半导体基底的材料和形状。根据实施例，其上设置有各种合适的电路器件和/或金属线的电路层可以嵌在半导体基底中。
垫单元PDA可以设置在基体基底BS的至少一个表面上。垫单元PDA可以包括多个垫(pad，或称为焊盘)PD。垫PD可以被设置为将基底SUB电连接到另一电子元件。垫PD可以是一种输入/输出端子。
垫PD中的每个可以包括设置在基体基底BS上的第一导电图案CP1、具有暴露第一导电图案CP1的一部分的多个接触孔的垫绝缘层PIL以及设置在垫绝缘层PIL上的第二导电图案CP2。
第一导电图案CP1可以包括从导电金属、导电有机材料和导电氧化物中选择的一种。例如，第一导电图案CP1可以包括从铜(Cu)、银(Ag)、金(Au)、铂(Pt)、钯(Pd)、镍(Ni)、锡(Sn)、铝(Al)、钴(Co)、铑(Rh)、铱(Ir)、铁(Fe)、钌(Ru)、锇(Os)、钼(Mo)、钨(W)、铌(Nb)、钽(Ta)、钛(Ti)、铋(Bi)、锑(Sb)和铅(Pb)中选择的至少一种。另外，第一导电图案CP1可以包括从聚噻吩类化合物、聚吡咯类化合物、聚苯胺类化合物、聚乙炔类化合物、聚亚苯基类化合物和它们的混合物中选择的至少一种。另外，第一导电图案CP1可以包括从氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锑锌(AZO)、氧化铟锡锌(ITZO)、氧化锌(ZnO)和氧化锡(SnO2)中选择的至少一种。以上描述的是第一导电图案CP1包括从导电金属、导电有机材料和导电氧化物中选择的至少一种。然而，本公开不限于此。第一导电图案CP1可以包括除了导电金属、导电有机材料和/或导电氧化物之外的导电材料。
垫绝缘层PIL可以包括从有机绝缘层和无机绝缘层中选择的至少一种。有机绝缘层可以包括透射光的有机绝缘材料(例如，透光有机绝缘材料)。例如，有机绝缘层可以包括从聚丙烯酸酯树脂、环氧树脂、酚醛树脂、聚酰胺树脂、聚酰亚胺树脂、不饱和聚酯树脂、聚苯醚树脂、聚苯硫醚树脂和苯并环丁烯树脂中选择的至少一种。无机绝缘层可以包括从氧化硅(SiOx，其中，1≤x≤2)和氮化硅(SiNx，1≤x≤1.33)中选择的至少一种。例如，无机绝缘层可以包括包含氧化硅的第一层以及设置在第一层上并包括氮化硅的第二层。
垫绝缘层PIL中的接触孔可以暴露第一导电图案CP1。接触孔可以在第一导电图案CP1的长度方向或宽度方向上彼此分离。
第二导电图案CP2可以设置在垫绝缘层PIL上，并在第一导电图案CP1的长度方向或宽度方向上彼此分离。第二导电图案CP2中的每个可以通过接触孔中的每个电连接到第一导电图案CP1。
第二导电图案CP2可以包括设置在垫绝缘层PIL上的第一导电层CL1和设置在第一导电层CL1上的第二导电层CL2。
第一导电层CL1可以具有导电性，并可以包括柔性材料。例如，第一导电层CL1可以包括从金(Au)、铝(Al)、铜(Cu)、锡(Sn)和钼(Mo)中选择的至少一种。另外，由于相邻的第二导电图案CP2彼此分离，因此第一导电层CL1的侧表面可以暴露于外部。
第二导电层CL2可以具有导电性，并可以包含刚性比包括在第一导电层CL1中的材料(在下文中，被称作“第一导电层材料”)的刚性大的材料。另外，包括在第二导电层CL2中的材料(在下文中，被称作“第二导电层材料”)的熔融温度可以高于第一导电层材料的熔融温度。例如，第二导电层CL2可以包括从钛(Ti)、钼(Mo)、锡(Sn)、镍(Ni)和导电氧化物中选择的至少一种。
第二导电层CL2可以具有比第一导电层CL1的厚度小的厚度。例如，第二导电层CL2可以具有10nm至100nm的厚度。
第二导电图案CP2还可以包括设置在第一导电层CL1下方的第三导电层CL3。第三导电层CL3可以设置在垫绝缘层PIL与第一导电层CL1之间以及第一导电图案CP1与第一导电层CL1之间。
第三导电层CL3可以包括刚性比第一导电层材料的刚性大的材料。例如，第三导电层CL3可以包括从钛(Ti)、钼(Mo)、锡(Sn)、镍(Ni)和导电氧化物中选择的至少一种。另外，第三导电层CL3可以包括与第二导电层CL2的材料相同(例如，基本上相同)的材料。
图6至图7是示出电连接到电子元件的图1至图5中示出的基底SUB的剖视图。图8是示出图6至图7中示出的混合导电层的概念视图。图6是连接结构在图3的线I-I'的方向上的剖视图。图7是连接结构在图3的线II-II'的方向上的剖视图。
参照图1至图8，基底SUB可以包括基体基底BS以及设置在基体基底BS的一侧处并包括多个垫PD的垫单元PDA。
垫PD可以分别连接到电子元件ED的凸块BMP。
电子元件ED可以根据基底SUB而变化。当基底SUB是半导体基底时，电子元件ED可以是从显示面板的阵列基底、柔性印刷电路板、印刷电路板中选择的一种。另外，当基底SUB是从显示面板的阵列基底、柔性印刷电路板、印刷电路板中选择的一种时，电子元件ED可以是半导体基底。
凸块BMP可以是用于基底SUB与电子元件ED之间的电连接的输入/输出端子。凸块BMP可以从电子元件ED的一个表面突出。凸块BMP的表面(例如，凸块BMP的与垫PD相对的表面)可以是从平坦表面、凹陷表面和凸出表面中选择的一种。
凸块BMP可以具有导电性，并可以包括柔性比垫PD的第二导电层材料的柔性大的材料。另外，包括在凸块BMP中的材料(在下文中，被称作“凸块材料”)的熔融温度可以低于垫PD的第二导电层材料的熔融温度。例如，凸块BMP可以包括从金(Au)、铝(Al)、铜(Cu)、锡(Sn)和钼(Mo)中选择的至少一种。另外，凸块BMP可以包括与垫PD的第一导电层CL1的材料相同(例如，基本上相同)的材料。另外，凸块BMP可以包括与垫PD的第一导电层CL1的材料不同的材料。
可以通过超声键合工艺来连接凸块BMP和垫PD。可以以这样的方式执行超声键合工艺：凸块BMP和垫PD可以被设置为彼此接触，然后通过对其施加压力和超声波而彼此连接。
凸块BMP中的每个可以连接到垫PD中的每个的一些第二导电图案CP2，并可以不连接到剩余的第二导电图案CP2。
未连接到凸块BMP的第二导电图案CP2中的每个可以包括第一导电层CL1、设置在第一导电层CL1上的第二导电层CL2以及设置在第一导电层CL1与第一导电图案CP1之间并连接到第一导电图案CP1的第三导电层CL3。
连接到凸块BMP的第二导电图案CP2中的每个可以包括第一导电层CL1和第三导电层CL3。换言之，连接到凸块BMP的第二导电图案CP2可以不包括第二导电层CL2。然而，混合导电层CML可以布置在凸块BMP与第二导电图案CP2的结合到凸块BMP的第一导电层CL1之间。另外，混合导电层CML可以填充相邻的第二导电图案CP2之间的区域。
在一些实施例中，在超声键合工艺期间，凸块BMP的一部分(例如，凸块BMP在垫PD方向上的一部分)可以以设定或预定的厚度局部地熔化(或者熔化至设定或预定的厚度)。另外，在超声键合工艺期间，第二导电图案CP2的连接到凸块BMP的第二导电层CL2可能断裂，第一导电层CL1的一部分(例如，第一导电层CL1在凸块BMP方向上(或沿凸块BMP方向)的一部分)可以局部地熔化。熔融的凸块材料和第一导电层材料可以彼此混合。凸块材料和第一导电层材料的混合物可以设置在凸块BMP与垫PD之间以及相邻的第二导电图案CP2之间，并且可以冷却以形成混合导电层CML。
在混合导电层CML中，第一导电层材料与凸块材料的混合比可以是不均匀的。换言之，第一导电层材料与凸块材料的混合比可以在混合导电层CML内变化。
另外，混合导电层CML可以包括第二导电层材料。如图8中所示，由于第二导电层材料的熔融温度高于第一导电层材料和凸块材料的熔融温度，因此混合导电层CML中的第二导电层材料可以作为碎片FRM存在。
可以使用非导电膜NCF来填充凸块BMP与垫PD之间的区域。非导电膜NCF可以包括能够通过加热而流动(例如，当加热时能够流动)的聚合物材料。因此，在凸块BMP与垫PD的超声键合工艺期间，当结合超声波施加热时，热可以导致非导电膜NCF流动。当非导电膜NCF通过加热而移动时，非导电膜NCF可以填充与凸块BMP和垫PD在凸块BMP和垫PD的超声键合工艺期间连接的区域不同的区域。因此，可以通过非导电膜NCF来改善基底SUB与电子元件ED之间的键合力。
图9至图13是示出连接如图1至图8中示出的基底SUB和电子元件ED的工艺的剖视图。
参照图9，首先，可以准备包括基体基底BS和设置在基体基底BS上的垫PD的基底SUB。
基体基底BS可以是从半导体基底、柔性印刷电路板、印刷电路板和显示面板的阵列基底中选择的一种。
垫PD可以包括设置在基体基底BS上的第一导电图案CP1、具有暴露第一导电图案CP1的一部分的多个接触孔的垫绝缘层PIL以及设置在垫绝缘层PIL上的第二导电图案CP2。
第一导电图案CP1可以包括导电材料。
可以在第一导电图案CP1上设置垫绝缘层PIL，其中，第一导电图案CP1可以通过垫绝缘层PIL中的接触孔而被暴露。
第二导电图案CP2可以包括设置在垫绝缘层PIL上的第一导电层CL1、设置在第一导电层CL1上的第二导电层CL2以及设置在第一导电图案CP1与第一导电层CL1之间的第三导电层CL3。
第一导电层材料的熔融温度可以低于第二导电层材料的熔融温度。另外，第二导电层材料可以包括刚性比第一导电层材料的刚性大的材料。包括在第三导电层CL3中的材料可以包括与第二导电层材料相同(例如，基本上相同)的材料。
参照图10，在准备基底SUB之后，可以在基底SUB上设置第一非导电膜NCF1。第一非导电膜NCF1可以包括能够通过加热而流动的聚合物材料。
在设置第一非导电膜NCF1之后，可以在第一非导电膜NCF1上方布置第一电子元件ED1。
可以在第一电子元件ED1的一个表面(例如，第一电子元件ED1的与基底SUB相对的表面)上设置凸块BMP。凸块BMP可以与垫PD相对。每个凸块BMP的表面(例如，每个凸块BMP的与每个垫PD相对的表面)可以是从平坦表面、凹陷表面和凸出表面中选择的一种。
凸块BMP可以具有导电性并可以包括柔性材料。例如，凸块BMP可以包括柔性比第二导电层材料的柔性大的材料。另外，包括在凸块BMP中的材料的熔融温度可以低于第二导电层材料的熔融温度。
在一些实施例中，可以在凸块BMP的表面上设置氧化物层。可以通过将凸块BMP暴露于空气(或包括氧气的任何合适的气体)来形成氧化物层，氧化物层可以包括凸块材料的氧化物。
第二导电图案CP2中的一些第二导电图案CP2可以不连接到凸块BMP，所以当基底SUB与第一电子元件ED1之间发生连接故障时可以执行返工工艺。
参照图11，在将第一电子元件ED1布置在第一非导电膜NCF1上之后，可以通过超声键合工艺来连接凸块BMP和垫PD，以电连接基底SUB和第一电子元件ED1。可以通过供应热、压力和超声波在超声键合工艺期间电连接基底SUB和第一电子元件ED1。
可以通过如下超声键合工艺来将凸块BMP和垫PD彼此连接。
首先，当向第一非导电膜NCF1施加热时，热可以导致第一非导电膜NCF1流动。接着，可以向基底SUB和第一电子元件ED1施加压力，并且可以将超声波供应到凸块BMP和垫PD。
当施加压力时，垫PD和凸块BMP可以彼此直接接触，第一非导电膜NCF1可以移到与垫PD和凸块BMP彼此接触的区域不同的区域。另外，当供应超声波时，垫PD和凸块BMP可以振动。垫PD和凸块BMP的振动方向可以与超声波的振动方向相同(例如，基本上相同)。
当垫PD和凸块BMP振动时，在垫PD与凸块BMP之间的接触区域中可能发生摩擦。该摩擦可能导致第二导电层CL2的断裂。另外，该摩擦也可能导致位于凸块BMP的表面上的氧化物层的断裂。
另外，当氧化物层和第二导电层CL2断裂时，第一导电层CL1和凸块BMP可以彼此接触。当第一导电层CL1和凸块BMP彼此接触时，该摩擦可能导致第一导电层CL1在凸块BMP方向上的一部分和凸块BMP在第一导电层CL1的方向上的一部分熔化。
熔融的部分可以变成位于第一导电层CL1与凸块BMP之间的包括第一导电层材料和凸块材料的混合导电层CML。
另外，由于凸块材料的氧化物和第二导电层材料的熔融温度可以高于第一导电层材料和凸块材料的熔融温度，因此凸块材料的氧化物和第二导电层材料可以作为碎片存在于混合导电层CML中。
可以使用第一非导电膜NCF1来填充凸块BMP与垫PD之间的区域。当第一非导电膜NCF1冷却时，第一非导电膜NCF1可以将基底SUB连接到第一电子元件ED1。因此，第一非导电膜NCF1可以改善基底SUB与第一电子元件ED1之间的键合力。
根据实施例，描述的是在超声键合工艺期间顺序地提供热、压力和超声波。然而，本公开不限于此。例如，在超声键合工艺期间，可以在同一(例如，基本上同一)时间提供热、压力和超声波。
参照图12，在将基底SUB和第一电子元件ED1电连接之后，可以对基底SUB和第一电子元件ED1执行连接故障测试。当检测到连接故障时，可以从基底SUB去除第一电子元件ED1。当去除第一电子元件ED1时，也可以去除混合导电层CML的位于第一导电层CL1上的一部分。
参照图13，在去除第一电子元件ED1之后，可以在基底SUB上设置第二非导电膜NCF2和第二电子元件ED2。第二非导电膜NCF2可以包括与第一非导电膜NCF1的材料相同(例如，基本上相同)的材料。第二电子元件ED2可以是与第一电子元件ED1相同(例如，基本上相同)的电子装置。换言之，与第一电子元件ED1相似，可以在第二电子元件ED2的一个表面上设置凸块BMP。
接着，通过向垫PD和第二电子元件ED2的凸块BMP施加热、压力和超声波，可以将基底SUB和第二电子元件ED2彼此电连接。
第二电子元件ED2的凸块BMP可以连接到第二导电图案CP2之中的未连接到第一电子元件ED1的凸块BMP的第二导电图案CP2。
可以在第二电子元件ED2的凸块BMP与第二导电图案CP2的未连接到第一电子元件ED1的凸块BMP的第一导电层CL1之间产生包括第一导电层材料和凸块材料的混合导电层CML。另外，第二导电层材料可以作为碎片存在于混合导电层CML中。所产生的混合导电层CML可以连接到在将第一电子元件ED1和基底SUB彼此连接时形成的混合导电层CML。
另外，第二电子元件ED2的凸块BMP可以与第二导电图案CP2的连接到第一电子元件ED1的凸块BMP的至少一部分部分地叠置，并可以连接到第二导电图案CP2的连接到第一电子元件ED1的凸块BMP的至少一部分。换言之，第二电子元件ED2的凸块BMP可以与第二导电图案CP2的至少一部分部分地叠置。
可以使用能够通过加热而流动的第二非导电膜NCF2来填充凸块BMP与垫PD之间的区域。当第二非导电膜NCF2冷却时，第二非导电膜NCF2可以将基底SUB连接到第二电子元件ED2。因此，可以通过第二非导电膜NCF2来改善基底SUB与第二电子元件ED2之间的键合力。
图14至图20是示出图1至图5中示出的垫PD的形状的平面图。
参照图1至图5和图14至图20，垫PD可以包括位于基体基底BS上的第一导电图案CP1以及彼此分离并位于垫绝缘层PIL上的第二导电图案CP2，垫绝缘层PIL设置在第一导电图案CP1上并包括接触孔。
第一导电图案CP1可以具有正方形形状，但是本公开不限于此。例如，第一导电图案CP1可以具有诸如圆形、椭圆形、半圆形和半椭圆形的各种合适的形状。
第二导电图案CP2可以具有各种合适的形状。例如，如图3、图14和图15中所示，第二导电图案CP2可以具有矩形形状。如图16中所示，第二导电图案CP2可以相对于第一导电图案CP1的一侧倾斜地延伸。如图17中所示，第二导电图案CP2可以具有菱形或六边形的形状。如图18中所示，第二导电图案CP2可以具有圆形形状。如图19至图20中所示，第二导电图案CP2中的每个可以以这样的椭圆形形状来形成：其主轴与第一导电图案CP1的短边平行(例如，基本上平行)。
如图3、图15、图16、图17和图19中所示，第二导电图案CP2可以布置在与超声波的振动方向(例如，超声振动方向)平行(例如，基本上平行)的方向上。例如，第二导电图案CP2中的相邻的第二导电图案CP2可以沿与超声振动方向(例如，超声振动波传播的方向)平行(例如，基本上平行)的方向彼此分隔开。然而，本公开不限于此。例如，第二导电图案CP2可以以如图14、图18和图20中示出的矩阵形式布置。
图21是示出根据实施例的显示装置的透视图。图22是示出图21中示出的显示面板的平面图。图23是沿图21的线III-III'截取的剖视图。图24是图23的区域EA1的放大视图。
参照图1至图8和图21至图24，显示装置可以包括显示面板PNL、安装在显示面板PNL的一侧上的第一驱动器DVR1、连接到显示面板PNL的一侧的柔性印刷电路板FPC以及连接到柔性印刷电路板FPC的第二驱动器DVR2。
显示面板PNL可以具有各种合适的形状。例如，显示面板PNL可以具有包括直边的闭合多边形形状。另外，显示面板PNL可以具有诸如包括曲面的圆形和椭圆形的形状。另外，显示面板PNL可以具有包括曲边和直边的半圆形或半椭圆形的形状。
显示面板PNL可以包括显示区域DA和设置在显示区域DA周围的非显示区域NDA。
多个像素PX可以设置在显示区域DA中。多条栅极线以及与栅极线交叉的多条数据线可以设置在显示区域DA中。像素PX中的每个可以包括连接到栅极线中的一条和数据线中的一条的至少一个薄膜晶体管TFT以及连接到薄膜晶体管TFT的显示元件OLED。
显示元件OLED可以是从液晶显示(LCD)元件、电泳显示(EPD)元件、电浸润显示(EWD)元件和有机发光显示(OLED)元件中选择的一种。在下文中，为了便于解释，OLED元件作为显示元件OLED的示例来进行描述。
非显示区域NDA可以布置在显示区域DA的周围。例如，非显示区域NDA可以设置在显示区域DA外部，并且可以围绕显示区域DA。另外，包括连接到第一驱动器DVR1的多个第一垫PD1的第一垫单元PDA1以及包括连接到柔性印刷电路板FPC的多个第二垫PD2的第二垫单元PDA2可以设置在非显示区域NDA的一部分上。
在下文中，根据堆叠顺序对显示面板PNL的结构进行描述。
在显示区域DA中，显示面板PNL可以包括阵列基底ARS和设置在阵列基底ARS上的显示层DPL。
阵列基底ARS可以包括绝缘基底DPS和设置在绝缘基底DPS上的驱动层DVL。
绝缘基底DPS可以包括透射光的透明绝缘材料。绝缘基底DPS可以是刚性基底。例如，绝缘基底DPS可以是从玻璃基底、石英基底、玻璃陶瓷基底和结晶玻璃基底中选择的一种。
另外，绝缘基底DPS可以是柔性基底。绝缘基底DPS可以是从包括聚合有机材料和塑料基底的膜基底中选择的一种。例如，绝缘基底DPS可以包括从聚苯乙烯、聚乙烯醇、聚甲基丙烯酸甲酯、聚醚砜、聚丙烯酸酯、聚醚酰亚胺、聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯、聚苯硫醚、聚芳酯、聚酰亚胺、聚碳酸酯、三醋酸纤维素和乙酸丙酸纤维素中选择的一种。然而，绝缘基底DPS的材料可以进行各种改变，并可以包括纤维增强塑料(FRP)。
在像素PX中，驱动层DVL可以包括至少一个薄膜晶体管TFT。
薄膜晶体管TFT可以包括半导体层SCL、与半导体层SCL绝缘的栅电极GE以及连接到半导体层SCL的源电极SE和漏电极DE。
半导体层SCL可以设置在绝缘基底DPS上。半导体层SCL可以包括从非晶硅(a-Si)、多晶硅(p-Si)、氧化物半导体和有机半导体中选择的一种。氧化物半导体可以包括Zn、In、Ga、Sn的氧化物和/或它们的混合物。例如，氧化物半导体可以包括氧化铟镓锌(IGZO)。
在半导体层SCL中，将源电极SE和漏电极DE彼此连接的区域可以是掺杂或注入有杂质的源区和漏区。另外，源区与漏区之间的区域可以是沟道区。
当半导体层SCL包括氧化物半导体时，遮光层可以设置在半导体层SCL上或下方，以阻挡光进入半导体层SCL中。
缓冲层BUL可以布置在绝缘基底DPS与半导体层SCL之间。缓冲层BUL可以防止杂质从绝缘基底DPS扩散并渗透到半导体层SCL中(或者可以减少这样的杂质的扩散和渗透)，使得可以防止(或减少)薄膜晶体管TFT的电特性的劣化。
缓冲层BUL可以包括从有机绝缘层和无机绝缘层中选择的至少一种。有机绝缘层可以包括透射光的有机绝缘材料。例如，有机绝缘层可以包括从聚丙烯酸酯树脂、环氧树脂、酚醛树脂、聚酰胺树脂、聚酰亚胺树脂、不饱和聚酯树脂、聚苯醚树脂、聚苯硫醚树脂和苯并环丁烯树脂中选择的至少一种。无机绝缘层可以包括从氧化硅SiOx(其中，1≤x≤2)和氮化硅SiNx(1≤x≤1.33)中选择的至少一种。例如，无机绝缘层可以包括包含氧化硅的第一层以及设置在第一层上并包括氮化硅的第二层。
另外，缓冲层BUL可以防止(或减少)湿气和氧从外部侵入到显示元件OLED中。缓冲层BUL可以使绝缘基底DPS的表面平坦化。
覆盖半导体层SCL的栅极绝缘层GI可以布置在绝缘基底DPS和半导体层SCL上。栅极绝缘层GI可以使半导体层SCL和栅电极GE绝缘。与缓冲层BUL相似，栅极绝缘层GI可以包括从有机绝缘层和无机绝缘层中选择的至少一种。
栅电极GE可以布置在栅极绝缘层GI上。栅电极GE可以与半导体层SCL部分地叠置。另外，栅电极GE可以包括导电材料。
层间绝缘层ILD可以布置在栅极绝缘层GI和栅电极GE上。换言之，层间绝缘层ILD可以覆盖栅电极GE。与栅极绝缘层GI相似，层间绝缘层ILD可以包括从有机绝缘层和无机绝缘层中选择的至少一种。另外，可以部分地去除层间绝缘层ILD，以暴露半导体层SCL的源区和漏区。
源电极SE和漏电极DE可以布置在层间绝缘层ILD上。源电极SE和漏电极DE可以通过层间绝缘层ILD与栅电极GE绝缘。另外，源电极SE和漏电极DE可以接触源区和漏区。
源电极SE和漏电极DE可以包括设置在层间绝缘层ILD上的第一导电层CL1、设置在第一导电层CL1上的第二导电层CL2以及设置在第一导电层CL1与层间绝缘层ILD之间的第三导电层CL3。
第一导电层CL1可以具有导电性并可以包括柔性材料。例如，第一导电层CL1可以包括从金(Au)、铝(Al)、铜(Cu)、锡(Sn)和钼(Mo)中选择的至少一种。
第二导电层CL2可以具有导电性，并可以包括刚性比第一导电层材料的刚性大的材料。另外，第二导电层材料的熔融温度可以高于第一导电层材料的熔融温度。例如，第二导电层CL2可以包括从钛(Ti)、钼(Mo)、锡(Sn)、镍(Ni)和导电氧化物中选择的至少一种。
第三导电层CL3可以包括刚性比第一导电层材料的刚性大的材料。例如，第三导电层CL3可以包括从钛(Ti)、钼(Mo)、锡(Sn)、镍(Ni)和导电氧化物中选择的至少一种。另外，第三导电层CL3可以包括与第二导电层CL2的材料相同(例如，基本上相同)的材料。
根据实施例，对薄膜晶体管TFT具有顶栅结构的示例进行了描述。然而，本公开不限于此。例如，薄膜晶体管TFT可以具有底栅结构。
驱动层DVL还可以包括覆盖薄膜晶体管TFT的保护层PSV。保护层PSV可以部分地暴露漏电极DE。
保护层PSV可以包括至少一个层。例如，保护层PSV可以包括从无机保护层和有机保护层中选择的至少一个。例如，保护层PSV可以包括覆盖薄膜晶体管TFT的无机保护层和设置在无机保护层上的有机保护层。
显示层DPL可以设置在保护层PSV上。在像素PX中，显示层DPL可以包括连接到薄膜晶体管TFT的显示元件OLED。
显示元件OLED可以包括连接到漏电极DE的第一电极AE、设置在第一电极AE上的有机层OL和设置在有机层OL上的第二电极CE。
从第一电极AE和第二电极CE中选择的一个可以是阳电极，另一个可以是阴电极。例如，第一电极AE可以是阳电极，第二电极CE可以是阴电极。
另外，从第一电极AE和第二电极CE中选择的至少一个可以是透射电极。例如，当显示元件OLED是底发射型(或类型)的有机发光元件时，第一电极AE可以是透射电极，第二电极CE可以是反射电极。当显示元件OLED是顶发射型(或类型)的有机发光元件时，第一电极AE可以是反射电极，第二电极CE可以是透射电极。当显示元件OLED是双发射型(或类型)的有机发光元件时，第一电极AE和第二电极CE都可以是透射电极。在下文中，例如，第一电极AE可以是阳电极，并且显示元件OLED可以是顶发射型(或类型)的显示装置。
第一电极AE可以设置在保护层PSV上。第一电极AE可以包括反射光的反射层和设置在反射层上或下方的透明导电层。从反射层和透明导电层中选择的至少一个可以接触漏电极DE。
反射层可以包括光反射材料。例如，反射层可以包括从金(Au)、银(Ag)、铬(Cr)、钼(Mo)、铂(Pt)、镍(Ni)和它们的合金中选择的至少一种。
透明导电层可以包括透明导电氧化物。例如，透明导电层可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铝锌(AZO)、掺镓氧化锌(GZO)、氧化锌锡(ZTO)、氧化镓锡(GTO)和掺氟氧化锡(FTO)之中的至少一种透明导电氧化物。
像素限定层PDL可以布置在第一电极AE和保护层PSV上。像素限定层PDL可以部分地暴露第一电极AE。像素限定层PDL可以覆盖第一电极AE的边缘和保护层PSV。
像素限定层PDL可以包括有机绝缘材料。例如，像素限定层PDL可以包括聚苯乙烯、聚甲基丙烯酸甲酯(PMMA)、聚丙烯腈(PAN)、聚酰胺(PA)、聚酰亚胺(PI)、聚芳醚(PAE)、杂环聚合物、聚对二甲苯、环氧树脂、苯并环丁烯(BCB)、硅氧烷类树脂和硅烷类树脂。
有机层OL可以包括包含发射层EML的多层薄膜结构。例如，有机层OL可以包括空穴注入层HIL、空穴传输层HTL、发射层、电子传输层ETL和电子注入层EIL，空穴注入层HIL用于注入空穴，空穴传输层HTL具有优异的可传输性并通过防止(或减少)未在发射层中复合的电子的迁移来增加空穴与电子之间的复合，发射层通过注入的电子与空穴之间的复合来发射光，电子传输层ETL将电子顺利地传输到发射层，电子注入层EIL注入电子。空穴注入层、空穴传输层、电子传输层和空穴注入层可以延伸到相邻的像素PX，并可以被像素PX共享。发射层可以产生选自于红色、绿色、蓝色和白色中的一种的光。然而，本公开不限于此。例如，从有机层OL的发射层发射的光的颜色可以是从品红色、青色和黄色中选择的一种。
第二电极CE可以布置在有机层OL上。第二电极CE可以是透反射层。例如，第二电极CE可以是足够透射光的厚(或薄)的薄金属层。第二电极CE可以透射从有机层OL产生的光中的一部分光，并可以反射从(或由)有机层OL产生的光中的剩余部分的光。从第二电极CE反射的光可以通过第一电极AE的反射层来进行反射，并可以通过相长干涉穿过第二电极CE。
第二电极CE可以包括具有比第一电极AE的透明导电层的逸出功低的逸出功的材料。例如，第二电极CE可以包括从钼(Mo)、钨(W)、银(Ag)、镁(Mg)、金(Au)、铂(Pt)、钯(Pd)、铝(Al)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)和它们的合金中选择的至少一种。
密封层ECL可以布置在第二电极CE上。密封层ECL可以使显示元件OLED与外部环境隔离。例如，密封层ECL可以防止(或减少)外部湿气和氧侵入到显示元件OLED中。密封层ECL可以是包括布置在第二电极CE上的多个无机层和多个有机层的薄膜密封层。例如，密封层ECL可以具有彼此交替地堆叠的无机层和有机层。
根据实施例，例如，密封层ECL形成为使显示元件OLED与外部环境隔离。然而，本公开不限于此。可以提供密封基底代替密封层ECL以使显示元件OLED与外部环境隔离。密封基底可以通过密封剂结合到绝缘基底DPS。当使用密封基底以使显示元件OLED与外部环境隔离(例如，基本上隔离)时，可以省略密封层ECL。
在非显示区域NDA中，第一垫PD1和第二垫PD2可以设置在绝缘基底DPS上。第一垫PD1和第二垫PD2可以具有与图1至图8中示出的垫PD的结构相同(例如，基本上相同)的结构。换言之，第一垫PD1和第二垫PD2中的每个可以包括第一导电图案CP1、设置在第一导电图案CP1上的垫绝缘层PIL以及设置在垫绝缘层PIL上并彼此分离的多个第二导电图案CP2。垫绝缘层PIL可以包括暴露第一导电图案CP1的多个接触孔。第二导电图案CP2可以通过接触孔连接到第一导电图案CP1。
第一导电图案CP1和栅电极GE可以包括相同(例如，基本上相同)的材料，并可以通过同一(例如，基本上同一)工艺来形成。垫绝缘层PIL和层间绝缘层ILD可以包括相同(例如，基本上相同)的材料，并可以通过同一(例如，基本上同一)工艺来形成。第二导电图案CP2可以具有与源电极SE和漏电极DE的结构相同(例如，基本上相同)的结构。
第一垫PD1中的每个和第二垫PD2中的每个可以分别连接到栅极线和数据线。例如，第一垫PD1中的每个可以连接到栅极线，第二垫PD2中的每个可以连接到数据线。
第一垫PD1或第二垫PD2(例如，第一垫PD1)可以连接到第一驱动器DVR1。另外，另外一个垫(例如，第二垫PD2)可以连接到柔性印刷电路板FPC。
第一驱动器DVR1可以是图6和图7中示出的电子元件ED。例如，第一驱动器DVR1可以是半导体基底，与第一垫PD1相对的凸块可以设置在第一驱动器DVR1的一个表面上。
第一驱动器DVR1可以将从扫描信号和数据信号中选择的一个供应到显示面板PNL。例如，第一驱动器DVR1可以将扫描信号供应到显示面板PNL。
柔性印刷电路板FPC的一端可以连接到第二垫PD2。另外，柔性印刷电路板FPC的另一端可以连接到第二驱动器DVR2。与第二垫PD2相对的凸块可以设置在柔性印刷电路板FPC的一端上。连接到第二驱动器DVR2的凸块或导电垫可以设置在柔性印刷电路板FPC的另一端上。
第二驱动器DVR2可以连接到柔性印刷电路板FPC。第二驱动器DVR2可以通过柔性印刷电路板FPC和第二垫PD2将数据信号供应到显示面板PNL。
第二驱动器DVR2可以由印刷电路板组成。当第二驱动器DVR2供应数据信号时，第二驱动器DVR2可以由安装有数据驱动芯片的印刷电路板组成。
图25是沿图21的线IV-IV'截取的剖视图。图26是图25的区域EA2的放大视图。
参照图1至图8和图21至图25，显示面板PNL的第一垫PD1可以连接到第一驱动器DVR1。连接到第一垫PD1的第一凸块BMP1可以设置在第一驱动器DVR1的一个表面上。第一凸块BMP1可以具有与图6至图7中示出的凸块BMP的结构相同(例如，基本上相同)的结构。
第一垫PD1可以具有与图1至图8中示出的垫PD的结构相似的结构。换言之，第一垫PD1中的每个可以包括第一导电图案CP1、设置在第一导电图案CP1上的垫绝缘层PIL以及设置在垫绝缘层PIL上并彼此分离的多个第二导电图案CP2。垫绝缘层PIL可以具有暴露第一导电图案CP1的多个接触孔。第二导电图案CP2可以通过接触孔连接到第一导电图案CP1。
第一导电图案CP1和薄膜晶体管TFT的栅电极GE可以包括相同(例如，基本上相同)的材料，并可以通过同一(例如，基本上同一)工艺来形成。垫绝缘层PIL和阵列基底ARS的层间绝缘层ILD可以包括相同(例如，基本上相同)的材料，并可以通过同一(例如，基本上同一)工艺来形成。
第一垫PD1中的每个中的一些第二导电图案CP2可以连接到第一凸块BMP1中的每个，剩余的第二导电图案CP2可以不连接到第一凸块BMP1。
未连接到第一凸块BMP1的第二导电图案CP2中的每个可以包括第一导电层CL1、设置在第一导电层CL1上的第二导电层CL2以及设置在第一导电层CL1与第一导电图案CP1之间并连接到第一导电图案CP1的第三导电层CL3。
连接到第一凸块BMP1的第二导电图案CP2中的每个可以包括第一导电层CL1以及设置在第一导电层CL1与第一导电图案CP1之间并连接到第一导电图案CP1的第三导电层CL3。换言之，连接到第一凸块BMP1的第二导电图案CP2可以不包括第二导电层CL2。然而，混合导电层CML可以设置在第一凸块BMP1与第二导电图案CP2的连接到第一凸块BMP1的第一导电层CL1之间。另外，混合导电层CML可以填充第二导电图案CP2之间的区域。
混合导电层CML可以包括第一导电层材料和凸块材料的混合物。在混合导电层CML中，第一导电层材料与凸块材料之间的混合比可以是不均匀的。换言之，第一导电层材料与凸块材料之间的混合比可以在混合导电层CML内变化。另外，混合导电层CML可以包括第二导电层材料的碎片。
可以使用可将显示面板PNL连接到第一驱动器DVR1的非导电膜NCF来填充第一凸块BMP1与第一垫PD1之间的区域。因此，可以通过非导电膜NCF来改善显示面板PNL与第一驱动器DVR1之间的键合力。
图27是沿图21的线V-V'截取的剖视图。图28是图27的区域EA3的放大视图。
参照图1至图8、图21至图24、图27和图28，显示面板PNL的第二垫PD2可以连接到柔性印刷电路板FPC的一端。第二凸块BMP2可以设置在柔性印刷电路板FPC的一个表面上，使得第二凸块BMP2中的每个可以连接到第二垫PD2中的每个。第二凸块BMP2可以具有与图6至图7中示出的凸块BMP的结构相似的结构。
第二垫PD2可以具有与图1至图8中示出的垫PD的结构相同(例如，基本上相同)的结构。换言之，第二垫PD2中的每个可以包括第一导电图案CP1、设置在第一导电图案CP1上的垫绝缘层PIL以及设置在垫绝缘层PIL上并彼此分离的多个第二导电图案CP2。
第一导电图案CP1和薄膜晶体管TFT的栅电极GE可以包括相同(例如，基本上相同)的材料，并可以通过同一(例如，基本上同一)工艺来形成。垫绝缘层PIL和阵列基底ARS的层间绝缘层ILD可以包括相同(例如，基本上相同)的材料，并可以通过同一(例如，基本上同一)工艺来形成。
第二垫PD2中的每个中的一些第二导电图案CP2可以连接到第二凸块BMP2中的每个，其它的第二导电图案CP2可以不连接到第二凸块BMP2。
未连接到第二凸块BMP2的第二导电图案CP2中的每个可以包括第一导电层CL1、设置在第一导电层CL1上的第二导电层CL2以及设置在第一导电层CL1与第一导电图案CP1之间并连接到第一导电图案CP1的第三导电层CL3。
连接到第二凸块BMP2的第二导电图案CP2中的每个可以包括第一导电层CL1以及设置在第一导电层CL1与第一导电图案CP1之间并连接到第一导电图案CP1的第三导电层CL3。换言之，连接到第二凸块BMP2的第二导电图案CP2可以不包括第二导电层CL2。然而，混合导电层CML可以设置在第二凸块BMP2与第二导电图案CP2的连接到第二凸块BMP2的第一导电层CL1之间。另外，混合导电层CML可以填充相邻的第二导电图案CP2之间的区域。
混合导电层CML可以包括第一导电层材料和凸块材料的混合物。在混合导电层CML中，第一导电层材料与凸块材料之间的混合比可以是不均匀的。换言之，第一导电层材料与凸块材料之间的混合比可以在混合导电层CML内变化。另外，混合导电层CML可以包括第二导电层材料的碎片。
可以使用非导电膜NCF来填充第二凸块BMP2与第二垫PD2之间的区域。非导电膜NCF可以将显示面板PNL连接到柔性印刷电路板FPC。因此，可以通过非导电膜NCF来改善显示面板PNL与柔性印刷电路板FPC之间的键合力。
图29是沿图21的线VI-VI'截取的剖视图。图30是图29的区域EA4的放大视图。
参照图1至图8、图21至图24、图29和图30，柔性印刷电路板FPC的另一端可以连接到第二驱动器DVR2。
第三垫PD3可以设置在选自于柔性印刷电路板FPC和第二驱动器DVR2之一的一个表面(例如，第二驱动器DVR2的一个表面)上。另外，连接到第三垫PD3的第三凸块BMP3可以设置在另一个的一个表面(例如，柔性印刷电路板FPC的一个表面)上。第三凸块BMP3可以具有与图6至图7中示出的凸块BMP的结构相同(例如，基本上相同)的结构。
第三垫PD3可以具有与图1至图8中示出的垫PD的结构相同(例如，基本上相同)的结构。换言之，第三垫PD3中的每个可以包括第一导电图案CP1、设置在第一导电图案CP1上的垫绝缘层PIL以及设置在垫绝缘层PIL上并彼此分离的多个第二导电图案CP2。
每个第三垫PD3中的一些第二导电图案CP2可以连接到每个第三凸块BMP3，其它的第二导电图案CP2可以不连接到第三凸块BMP3。
不连接到第三凸块BMP3的第二导电图案CP2中的每个可以包括第一导电层CL1、设置在第一导电层CL1上的第二导电层CL2以及设置在第一导电层CL1与第一导电图案CP1之间并连接到第一导电图案CP1的第三导电层CL3。
连接到第三凸块BMP3的第二导电图案CP2可以包括第一导电层CL1以及设置在第一导电层CL1与第一导电图案CP1之间并连接到第一导电图案CP1的第三导电层CL3。换言之，连接到第三凸块BMP3的第二导电图案CP2可以不包括第二导电层CL2。然而，混合导电层CML可以设置在第三凸块BMP3与第二导电图案CP2的连接到第三凸块BMP3的第一导电层CL1之间。另外，混合导电层CML可以填充第二导电图案CP2之间的区域。
混合导电层CML可以包括第一导电层材料和凸块材料的混合物。在混合导电层CML中，第一导电层材料与凸块材料之间的混合比可以是不均匀的。换言之，第一导电层材料与凸块材料之间的混合比可以在混合导电层CML内变化。另外，混合导电层CML可以包括第二导电层材料的碎片。
可以使用非导电膜NCF来填充第三凸块BMP3与第三垫PD3之间区域。非导电膜NCF可以将第二驱动器DVR2连接到柔性印刷电路板FPC。因此，可以通过非导电膜NCF来改善第二驱动器DVR2与柔性印刷电路板FPC之间的键合力。
根据实施例，基底上的垫可以通过超声键合工艺连接到电子装置的输入/输出端子(例如，凸块)。因此，由于不在基底与电子装置之间的连接结构中使用各向异性导电膜，因此可以防止短路故障或开路故障(或者可以减少这样的故障的可能性或程度)。
尽管在此公开了示例实施例，但是这些实施例不应被解释为成为限制。本领域普通技术人员将识别的是，在不脱离本公开的精神和范围的情况下，可以做出形式上和细节上的各种改变。另外，各种领域的技术人员将识别的是，在此描述的本公开将启示对其它任务的解决方案和用于其它应用的适应。在都不脱离本公开的精神和范围的情况下，申请人的发明意图通过在此的权利要求来覆盖本公开的主题的所有这样的用途以及针对公开的目的在此选择的可对本公开的示例实施例做出的这些改变和修改。因此，在如由所附权利要求及其等同物限定的本公开的精神和范围内，本公开的示例实施例在所有方面应被认为是示出性的而不是限制性的。

Claims (44)

1.一种基底，所述基底包括：
基体基底；以及
垫，位于所述基体基底的一侧处，
其中，所述垫包括：第一导电图案，位于所述基体基底上；绝缘层，包括暴露所述第一导电图案的一部分的多个接触孔；以及第二导电图案，分开位于所述绝缘层上，并通过所述多个接触孔连接到所述第一导电图案，
其中，所述第二导电图案的侧表面被暴露。
2.根据权利要求1所述的基底，其中，所述第二导电图案包括顺序堆叠的第一导电层和第二导电层，并且所述第一导电层的侧表面被暴露。
3.根据权利要求2所述的基底，其中，所述第二导电层包括刚性比包括在所述第一导电层中的材料的刚性大的材料。
4.根据权利要求3所述的基底，其中，所述第一导电层包括选自于由金、铝、铜、锡和钼组成的组中的至少一种。
5.根据权利要求3所述的基底，其中，所述第二导电层包括选自于由钛、钼、锡、镍和导电氧化物组成的组中的至少一种。
6.根据权利要求5所述的基底，其中，所述导电氧化物包括选自于由氧化铟锡、氧化铟锌、氧化锑锌、氧化铟锡锌、氧化锌和氧化锡组成的组中的至少一种。
7.根据权利要求3所述的基底，所述基底还包括位于所述第一导电层与所述第一导电图案之间的第三导电层。
8.根据权利要求7所述的基底，其中，所述第三导电层包括选自于由钛、钼、锡、镍和导电氧化物组成的组中的至少一种。
9.根据权利要求7所述的基底，其中，所述第三导电层包括与所述第二导电层的材料相同的材料。
10.一种电子装置，所述电子装置包括：
基底，包括基体基底和位于所述基体基底上的垫；以及
电子元件，包括连接到所述垫的凸块，
其中，所述垫包括：第一导电图案，位于所述基体基底上；绝缘层，包括暴露所述第一导电图案的一部分的多个接触孔；以及第二导电图案，分开位于所述绝缘层上，并通过所述多个接触孔连接到所述第一导电图案，
其中，所述第二导电图案中的至少一部分第二导电图案连接到所述凸块，并且
其中，剩余的第二导电图案的侧表面被暴露。
11.根据权利要求10所述的电子装置，其中，连接到所述凸块的所述第二导电图案包括第一导电层，并且
其中，所述电子装置还包括混合导电层，所述混合导电层位于所述第一导电层与所述凸块之间，并包括第一导电层材料和凸块材料的混合物。
12.根据权利要求11所述的电子装置，其中，所述剩余的第二导电图案包括所述第一导电层和位于所述第一导电层上的第二导电层，并且所述第一导电层的侧表面被暴露。
13.根据权利要求12所述的电子装置，其中，所述第二导电层包括刚性比所述第一导电层材料的刚性大的材料。
14.根据权利要求13所述的电子装置，其中，所述第一导电层包括选自于由金、铝、铜、锡和钼组成的组中的至少一种。
15.根据权利要求13所述的电子装置，其中，所述第二导电层包括选自于由钛、钼、锡、镍和导电氧化物组成的组中的至少一种。
16.根据权利要求13所述的电子装置，所述电子装置还包括位于所述第一导电层与所述第一导电图案之间的第三导电层。
17.根据权利要求16所述的电子装置，其中，所述第三导电层包括与所述第二导电层的材料相同的材料。
18.根据权利要求13所述的电子装置，其中，所述凸块包括选自于由金、铝、铜、锡和钼组成的组中的至少一种。
19.根据权利要求13所述的电子装置，其中，所述凸块包括与所述第一导电层的材料相同的材料。
20.根据权利要求13所述的电子装置，其中，所述混合导电层包括包含第二导电层材料的碎片。
21.根据权利要求10所述的电子装置，所述电子装置还包括填充与所述凸块与所述垫连接的区域不同的区域的非导电膜。
22.根据权利要求21所述的电子装置，其中，所述非导电膜包括可热流动的聚合物材料。
23.一种电子装置，所述电子装置包括：
基底，包括基体基底和位于所述基体基底上的垫；以及
电子元件，包括连接到所述垫的凸块，
其中，所述垫包括：第一导电图案，位于所述基体基底上；绝缘层，包括暴露所述第一导电图案的一部分的多个接触孔；第二导电图案，分开位于所述绝缘层上，并包括通过所述多个接触孔连接到所述第一导电图案的第一导电层；以及混合导电层，位于所述第二导电图案与所述凸块之间，
其中，所述混合导电层包括第一导电层材料和凸块材料的混合物。
24.根据权利要求23所述的电子装置，其中，所述第一导电层包括选自于由金、铝、铜、锡和钼组成的组中的至少一种。
25.根据权利要求24所述的电子装置，其中，所述凸块包括选自于由金、铝、铜、锡和钼组成的组中的至少一种。
26.根据权利要求24所述的电子装置，所述电子装置还包括位于所述第一导电层与所述第一导电图案之间的第三导电层。
27.根据权利要求26所述的电子装置，其中，所述混合导电层包括包含第二导电层材料的碎片。
28.根据权利要求26所述的电子装置，其中，所述第二导电层包括刚性比所述第一导电层材料的刚性大的材料。
29.根据权利要求26所述的电子装置，其中，所述第二导电层包括选自于由钛、钼、锡、镍和导电氧化物组成的组中的至少一种。
30.根据权利要求24所述的电子装置，其中，所述第一导电层和所述凸起包括相同的材料。
31.根据权利要求23所述的电子装置，所述电子装置还包括填充与所述凸块和所述垫连接的区域不同的区域的非导电膜。
32.根据权利要求31所述的电子装置，其中，所述非导电膜包括可热流动的聚合物材料。
33.一种显示装置，所述显示装置包括：
显示面板，包括显示区域和非显示区域，其中，所述显示面板包括位于所述非显示区域中的第一垫单元和第二垫单元，所述第一垫单元包括多个第一垫，所述第二垫单元包括多个第二垫；
第一驱动器，包括连接到所述第一垫单元的多个第一凸块；
柔性印刷电路板，包括连接到所述第二垫单元的多个第二凸块；以及
第二驱动器，连接到所述柔性印刷电路板的一端，
其中，从所述柔性印刷电路板和所述第二驱动器中选择的一个包括第三凸块，并且另一个包括连接到所述第三凸块的第三垫，并且
其中，所述第一垫、所述第二垫和所述第三垫中的每个包括：第一导电图案；绝缘层，包括暴露所述第一导电图案的一部分的多个接触孔；以及第二导电图案，分开位于所述绝缘层上，并通过所述多个接触孔连接到所述第一导电图案，
其中，所述第二导电图案中的至少一部分第二导电图案连接到从所述第一凸块至所述第三凸块中选择的一者，并且
剩余的第二导电图案的侧表面被暴露。
34.根据权利要求33所述的显示装置，其中，连接到从所述第一凸块至所述第三凸块中选择的一者的所述第二导电图案包括第一导电层，并且
其中，所述显示装置还包括混合导电层，所述混合导电层位于所述第一导电层与从所述第一凸块至所述第三凸块中选择的所述一者之间并包括第一导电层材料和凸块材料的混合物。
35.根据权利要求34所述的显示装置，其中，所述剩余的第二导电图案包括所述第一导电层和位于所述第一导电层上的第二导电层，并且所述第一导电层的侧表面被暴露。
36.根据权利要求35所述的显示装置，其中，所述第二导电层包括刚性比所述第一导电层材料的刚性大的材料。
37.根据权利要求36所述的显示装置，其中，所述第一导电层包括选自于由金、铝、铜、锡和钼组成的组中的至少一种。
38.根据权利要求36所述的显示装置，其中，所述第二导电层包括选自于由钛、钼、锡、镍和导电氧化物组成的组中的至少一种。
39.根据权利要求36所述的显示装置，所述显示装置还包括位于所述第一导电层与所述第一导电图案之间的第三导电层。
40.根据权利要求39所述的显示装置，其中，所述第三导电层包括与所述第二导电层的材料相同的材料。
41.根据权利要求36所述的显示装置，其中，所述第一凸块至所述第三凸块包括选自于由金、铝、铜、锡和钼组成的组中的至少一种。
42.根据权利要求36所述的显示装置，其中，所述混合导电层包括包含第二导电层材料的碎片。
43.根据权利要求33所述的显示装置，所述显示装置还包括填充与所述第一凸块至所述第三凸块和所述第一垫至所述第三垫连接的区域不同的区域的非导电膜。
44.根据权利要求43所述的显示装置，其中，所述非导电膜包括可热流动的聚合物材料。
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