CN108172174B - 像素阵列基板 - Google Patents

像素阵列基板 Download PDF

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CN108172174B
CN108172174B CN201611112401.1A CN201611112401A CN108172174B CN 108172174 B CN108172174 B CN 108172174B CN 201611112401 A CN201611112401 A CN 201611112401A CN 108172174 B CN108172174 B CN 108172174B
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CN108172174A (zh
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陈筠涵
庄博钧
朱晓彤
黄霈霖
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E Ink Holdings Inc
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Abstract

本发明公开了一种像素阵列基板,包含基板、多条第一信号线、多条第二信号线、多个主动元件、多个像素电极、多条选择线、驱动单元及多条金属线。各选择线与第一信号线交错以形成第一交错处及多个第二交错处,各选择线在第一交错处与第一信号线电性连接,在第二交错处与第一信号线电性绝缘,各选择线具有第一部分及第二部分,第一部分与在第一交错处的第一信号线重叠,且与第二部分相隔有间隙。驱动单元电性连接至第二信号线及选择线的第一部分。各金属线与多个间隙的其中之一重叠。本发明的像素阵列基板能够符合自动光学检查的检测标准,并且可设置于各种显示器中,使显示画面的颜色及亮度均匀,且显示品质良好。

Description

像素阵列基板
技术领域
本发明是关于一种像素阵列基板,特别是关于一种具有不连续选择线的像素阵列基板。
背景技术
随着显示面板被广泛地应用在各式显示器中,例如:电视、笔记本电脑、平板电脑、电子纸(e-paper)书及行动电话等。窄边框(Narrow boarder)设计的显示面板是目前显示器产业的发展趋势。
图1是公知的一种像素阵列的局部示意图,两条第一信号线110a及110b与第二信号线120交错,并也与选择线130交错而形成第一交错处a1及第二交错处a2。第一信号线110a与选择线130在第一交错处a1电性连接,因此外部信号源的信号可通过选择线130传递至第一信号线110a。第一信号线110b与选择线130在第二交错处a2电性绝缘,然而,第一信号线110b可通过其它选择线(未示出)而也连接至外部信号源。上述的布线设计促使当第二信号线120与位于图1的下侧的信号源(未示出)电性连接时,第一信号线110a也可通过选择线130而也与信号源电性连接,而取代了传统上第一信号线110a需由图1的左侧或右侧拉线至信号源的设计,因此,通过图1的像素阵列能够实现窄边框的设计。
然而,在选择线130中,从第一交错处a1延伸出来并超过第二交错处a2的这段选择线130常会导致包含如图1的像素阵列的显示器发生颜色不均(Mura)的问题,而降低显示器的显示性能。
发明内容
本发明的目的在于提供一种像素阵列基板,能够符合自动光学检查的检测标准,并且可设置于各种显示器中,使显示画面的颜色及亮度均匀,且显示品质良好。
为实现上述目的本发明提供一种像素阵列基板,包含基板、多条第一信号线配置于基板上、多条第二信号线配置于基板上,并与这些第一信号线交错且电性绝缘、多个主动元件,各主动元件与这些第一信号线的其中一条及这些第二信号线的其中一条电性连接、多个像素电极,各像素电极与这些主动元件的其中一个电性连接、多条选择线配置于基板上、驱动单元及多条金属线。其中,各选择线与这些第一信号线交错以形成第一交错处及多个第二交错处,各选择线在第一交错处与第一信号线电性连接,在这些第二交错处与这些第一信号线电性绝缘,各选择线具有第一部分及第二部分,第一部分与在第一交错处的第一信号线重叠,且与第二部分相隔有间隙。驱动单元电性连接至这些第二信号线及这些选择线的这些第一部分。各金属线与这些间隙的其中一个重叠。
在本发明一实施方式中,各金属线的长度大于或等于与各金属线重叠的间隙的间隙长度。
在本发明一实施方式中,各金属线与相邻的第一部分重叠。
在本发明一实施方式中,各金属线与相邻的第二部分重叠。
在本发明一实施方式中,间隙位于第一交错处及与第一交错处相邻的第二交错处之间。
在本发明一实施方式中,这些第一信号线与这些金属线位于同一层。
在本发明一实施方式中,这些金属线的材料与这些第一信号线的材料相同。
在本发明一实施方式中,各选择线的第一部分具有线宽,与邻近于第一部分的金属线的线宽相同。
在本发明一实施方式中,各选择线的第二部分具有线宽,与邻近于第二部分的金属线的线宽相同。
在本发明一实施方式中,第一信号线为扫描线,第二信号线为数据线。
本发明的像素阵列基板,与现有技术相比,具有能够符合自动光学检查的检测标准,并且可设置于各种显示器中,使显示画面的颜色及亮度均匀,且显示品质良好的有益效果。
附图说明
本发明上述和其它目的、特征及其它优点参照说明书内容并配合附图得到更清楚的了解,其中:
图1是公知的一种像素阵列的局部示意图;
图2是根据本发明的一实施方式所绘示的像素阵列基板的俯视示意图;
图3是图2中区域R的放大示意图;
图4是图3中剖线A-A’的剖面示意图;
图5A-5D是分别根据本发明的不同实施方式所绘示的图3中剖线B-B’的剖面示意图。
具体实施方式
图2是根据本发明的一实施方式所绘示的像素阵列基板的俯视示意图。图3是图2中区域R的放大示意图。请参照图2及图3,像素阵列基板200包括基板202并在基板202上设置有驱动单元204、多条第一信号线210、多条第二信号线220、多条选择线230、多条金属线240、多个主动元件250及多个像素电极260。像素阵列a包含这些第一信号线210、第二信号线220、选择线230、金属线240、主动元件250及像素电极260。
如图2及图3所示,这些第一信号线210及这些第二信号线220皆配置于基板202上,这些第二信号线220与这些第一信号线210交错且电性绝缘。并且,这些第一信号线210与这些第二信号线220交错以定义出多个像素区P,各主动元件250配置于这些像素区P的其中一个中,且与这些第一信号线210的其中一条及这些第二信号线220的其中一条电性连接。各像素电极260与这些主动元件250的其中一个电性连接。
在一实施方式中,这些第一信号线210沿第一方向D1延伸且沿第二方向D2排列,这些第二信号线220沿第二方向D2延伸且沿第一方向D1排列。在一实施方式中,第一方向D1垂直于第二方向D2,但不限于此。
请参照图2,每条选择线230与这些第一信号线210交错以形成一个第一交错处X1及多个第二交错处X2,选择线230在第一交错处X1与这些第一信号线210电性连接,在第二交错处X2与这些第一信号线210电性绝缘。各选择线230具有第一部分230a及第二部分230b,第一部分230a与在第一交错处X1的第一信号线210重叠,且与第二部分230b相隔有间隙G。换言之,第二部分230b不与第一交错处X1重叠,且与第一部分230a电性绝缘。如图2所示,选择线230为不连续的选择线,第一部分230a与第二部分230b通过间隙G而电性绝缘,由于第二部分230b不与第一部分230a导通而无法接收来自于驱动单元204的信号,因此,当像素阵列基板200被配置于显示器中时,邻近于选择线230的第二部分230b的显示区不会发生颜色不均(Mura)的问题。
此外,从图3来看,间隙G位于第一交错处X1及与第一交错处X1相邻的第二交错处X2之间。换言之,在与选择线230的第二部分230b重叠的所有第二交错处X2之中,此与第一交错处X1相邻的第二交错处X2即为最靠近第一交错处X1的第二交错处X2。当间隙G越靠近第一交错处X1时,将能够使得从第一交错处X1延伸向第二交错处X2的选择线的第一部分230a越短,并使得与第一部分230a电性绝缘的第二部分230b越长,而越能够避免发生颜色不均(Mura)的问题。在其它实施方式中,间隙G也可位于第一交错处X1及与选择线230的第二部分230b重叠的其它第二交错处X2之间。
此外,一般来说,在制作像素阵列基板的过程中,常会利用自动光学检查(Automated Optical Inspection,AOI)从像素阵列的上方进行检测,去比较各交错处附近的线路结构是否一致,若出现不一致的状况,则会被判定为线路结构出现缺陷,而无法进行下一步的工艺。在如图2所示的像素阵列基板200中,间隙G的存在会使得选择线230在俯视时看起来为不连续的。然而,像素阵列基板200同时包含这些金属线240,各金属线240与这些间隙G的其中一个重叠,而会使得各交错处附近的线路结构一致,而能够符合自动光学检查的检测标准。举例来说,由于金属线240与间隙G重叠的缘故,在区域R1中,第一交错处X1附近的线路结构与在区域R2中的第二交错处X2附近的线路结构一致。并且,这些金属线240与这些第一部分230a及这些第二部分230b电性绝缘。虽然在图2的俯视示意图中,金属线240看起来像是与这些第一部分230a及这些第二部分230b连接,但事实上这些金属线240与这些第一部分230a及这些第二部分230b是位于不同层,因此,金属线240不会导通第一部分230a及第二部分230b,金属线240的存在不会造成如先前技术所述的颜色不均(Mura)的问题。
因此,为了要使各交错处附近的线路结构一致,金属线240的形状应该与间隙G的形状相同或是类似。举例来说,金属线240的长度应大于或等于间隙G的间隙长度GL(请参照图5A~5D),金属线240的线宽应等同于选择线230的第一部分230a的线宽及选择线230的第二部分230b的线宽,才能够使得各第一交错处X1及各第二交错处X2附近的线路结构看起来一致。在一实施方式中,各金属线240的长度大于或等于与各金属线240重叠的间隙G的间隙长度GL。在一实施方式中,各选择线230的第一部分230a具有线宽,与邻近于第一部分230a的金属线240的线宽相同。在另一实施方式中,各选择线230的第二部分230b具有线宽,与邻近于第二部分230b的金属线240的线宽相同。
如图2所示,驱动单元204配置于基板202上,电性连接至这些第二信号线220及这些选择线230的这些第一部分230a。由于这些选择线230的第一部分230a是在第一交错处X1与第一信号线210电性连接,这些选择线230可将来自驱动单元204的信号传递至这些第一信号线210。
接下来,请同时参照图3及图4,图4是图3中剖线A-A’的剖面示意图。主动元件250包含栅极GE、主动层AC、源极SE及漏极DE。栅极GE配置于基板202上,主动层AC是位于栅极GE上,源极SE及漏极DE配置于主动层AC上。主动元件250可进一步包含绝缘层410于栅极GE及主动层AC之间,覆盖栅极GE及基板202。主动元件250可进一步包含保护层420,漏极DE可通过保护层420的开口H电性连接像素电极250。在图3中,以连接处C标示出漏极DE与像素电极250的电性连接的位置。
在图3中,第一信号线210与栅极GE电性连接,第二信号线220与源极SE电性连接,因此,第一信号线210是扫描线,第二信号线220是数据线,第一信号线210与选择线230电性连接而将驱动单元204的信号传递至栅极GE。在另一实施方式中,主动元件的栅极与第二信号线220电性连接,主动元件的源极与第一信号线210电性连接,因此,在此实施方式中,第一信号线210是数据线,第二信号线220是扫描线,第一信号线210与选择线230电性连接将驱动单元204的信号传递至源极。
接下来,请参照图5A~5D,图5A~5D分别为根据本发明的不同实施方式所绘示的图3中剖线B-B’的剖面示意图。由于图5A~5D的不同之处在于金属线的长短皆不同,因此为了清楚指明不同图示中的金属线,在此将图5A~5D中的金属线分别重新编号为240a、240b、240c及240d。
如图5A所示,金属线240a的长度L1等于与金属线240重叠的间隙G的间隙长度GL。金属线240a的末端与相邻的第一部分230a的末端对齐,金属线240a的另一末端与相邻的第二部分230b的末端对齐。换言之,金属线240a并不与第一部分230a或第二部分230b重叠。
此外,从图5A可看出第一信号线210与金属线240a位于同一层。在一实施方式中,可于基板202上形成金属层后,再图案化金属层同时形成第一信号线210及金属线240a,因此,金属线240的材料与第一信号线210的材料相同。
在图5B~5D中,金属线240b、240c及240d各具有长度大于与各金属线240重叠的间隙G的间隙长度GL。如图5B所示,金属线240b的长度L2大于间隙长度GL,并且,金属线240b与相邻的选择线230的第一部分230a及第二部分230b重叠。如图5C所示,金属线240c的长度L3大于间隙长度GL,并且与相邻的选择线230的第一部分230a重叠,金属线240c具有末端与相邻的第二部分230b的末端对齐。如图5D所示,金属线240d的长度L4大于间隙长度GL,并且与相邻的选择线230的第二部分230b重叠,金属线240d具有末端与相邻的第一部分230a的末端对齐。
从上述的图5A~5D来看,金属线240a、240b、240c及240d皆位于选择线230下,因此在图3的俯视示意图中,金属线240a、240b、240c及240d通过间隙G而暴露出来的部分会看起来一样长。然而,金属线的位置并不限于本案图5A~5D所示的实施方式,在其它实施方式中,金属线位于选择线230上。
综上所述,本发明的像素阵列基板包含不连续的选择线及金属线,此选择线包含第一部分及第二部分,第一部分与第二部分相隔有间隙,金属线与此间隙重叠,并与第一部分及第二部分电性绝缘。金属线的设置使得像素阵列基板的像素阵列中的各交错处附近的线路结构在俯视下皆一致,而能够符合自动光学检查的检测标准。因此,在制作本发明的像素阵列基板的过程中,不须调整目前的自动光学检测设备或检测参数。
并且,本发明的像素阵列基板可设置于各种显示器中,且能够解决如先前技术中所述的颜色不均(Mura)的问题。显示器例如为电泳显示器,其可包含本发明的像素阵列基板及设置于其上的电泳显示薄膜,可通过像素阵列基板驱动电泳显示薄膜中的显示粒子来获得显示画面。本发明的像素阵列基板中的不连续的选择线能够使显示画面的颜色及亮度均匀,而使得显示品质良好。
虽然本发明已以实施方式公开如上,以上所述仅为本发明的较佳实施例,并非用以限定本发明,任何本领域的一般技术人员,在不脱离本发明的精神和范围内,当可作各种的均等变化与修饰,皆应属本发明的涵盖范围,因此本发明的保护范围当视权利要求所界定的为准。

Claims (10)

1.一种像素阵列基板,其特征在于,包含:
基板;
多条第一信号线,配置于所述基板上;
多条第二信号线,配置于所述基板上,所述多条第二信号线与所述多条第一信号线交错且电性绝缘;
多个主动元件,各所述主动元件与所述多条第一信号线的其中一条及所述多条第二信号线的其中一条电性连接;
多个像素电极,各所述像素电极与所述多个主动元件的其中一个电性连接;
多条选择线,配置于所述基板上,各所述选择线与所述多条第一信号线交错以形成第一交错处及多个第二交错处,各所述选择线在所述第一交错处与所述第一信号线电性连接,在所述多个第二交错处与所述多条第一信号线电性绝缘,各所述选择线具有第一部分及第二部分,所述第一部分与在所述第一交错处的所述第一信号线重叠,且与所述第二部分相隔有间隙;
驱动单元,电性连接至所述多条第二信号线及所述多条选择线的所述多个第一部分;以及
多条金属线,各所述金属线与所述多个间隙的其中一个重叠,所述金属线与所述第一部分及所述第二部分电性绝缘。
2.如权利要求1所述的像素阵列基板,其特征在于,各所述金属线的长度大于或等于与各所述金属线重叠的所述间隙的间隙长度。
3.如权利要求1所述的像素阵列基板,其特征在于,各所述金属线与相邻的所述第一部分重叠。
4.如权利要求1所述的像素阵列基板,其特征在于,各所述金属线与相邻的所述第二部分重叠。
5.如权利要求1所述的像素阵列基板,其特征在于,所述间隙位于所述第一交错处及与所述第一交错处相邻的所述第二交错处之间。
6.如权利要求1所述的像素阵列基板,其特征在于,所述多条第一信号线与所述多条金属线位于同一层。
7.如权利要求1所述的像素阵列基板,其特征在于,所述多条金属线的材料与所述多条第一信号线的材料相同。
8.如权利要求1所述的像素阵列基板,其特征在于,各所述选择线的所述第一部分具有线宽,所述线宽与邻近于所述第一部分的所述金属线的线宽相同。
9.如权利要求1所述的像素阵列基板,其特征在于,各所述选择线的所述第二部分具有线宽,所述线宽与邻近于所述第二部分的所述金属线的线宽相同。
10.如权利要求1所述的像素阵列基板,其特征在于,所述第一信号线为扫描线,所述第二信号线为数据线。
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