WO2020211256A1 - 超窄边框液晶显示器及电子装置 - Google Patents

超窄边框液晶显示器及电子装置 Download PDF

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Publication number
WO2020211256A1
WO2020211256A1 PCT/CN2019/103722 CN2019103722W WO2020211256A1 WO 2020211256 A1 WO2020211256 A1 WO 2020211256A1 CN 2019103722 W CN2019103722 W CN 2019103722W WO 2020211256 A1 WO2020211256 A1 WO 2020211256A1
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WIPO (PCT)
Prior art keywords
substrate
insulating layer
scan lines
ultra
lines
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PCT/CN2019/103722
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English (en)
French (fr)
Inventor
李柱辉
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020211256A1 publication Critical patent/WO2020211256A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to a liquid crystal display, in particular to an ultra-narrow frame liquid crystal display and an electronic device.
  • TFT-LCD displays are gradually moving towards trends such as flexibility, high screen-to-body ratio, drop resistance, long life, ultra-narrow bezels or no bezels. Examples of existing solutions for ultra-narrow bezel displays are as follows.
  • GOA Gate Driver on Array
  • TFT Thin Field Transistor
  • the gate driver IC Gate driver IC
  • the GOA circuit can be used.
  • the area of the border area is greatly reduced, for example, the border can be reduced to less than 0.6 millimeters (mm).
  • GOA circuit technology is prone to shortcomings such as circuit corrosion, low reliability, short life, and low yield, resulting in limited application fields. Currently, it is only used in consumer electronic products.
  • the other is to use the Twisted Gate line Placed in Pixel (TGPP) technology, but the disadvantage of this technology is that the capacitance of the display area is inconsistent, which affects the overall display effect and makes wiring difficult.
  • TGPP Twisted Gate line Placed in Pixel
  • TGP Tracking Gate line in Pixel
  • WAA Wire on Array
  • the present invention provides an ultra-narrow bezel liquid crystal display and an electronic device, which hides the gate line in the border area of the display under the data line of the pixel to solve the problem that the border area cannot be reduced in the prior art.
  • An aspect of the present invention provides an ultra-narrow bezel liquid crystal display, including: a substrate, a surface of the substrate includes a display area and a bezel area, the bezel area surrounds the display area; a plurality of horizontal scanning lines, Are arranged above the substrate and located in the display area; a plurality of vertical data lines are arranged above the substrate and located in the display area, and the plurality of vertical data lines are interlaced with a plurality of horizontal scanning lines and electrically Electrical insulation to define a plurality of pixel regions; and a plurality of vertical scan lines are arranged in the projection range of the plurality of vertical data lines, the plurality of vertical scan lines and the plurality of horizontal scan lines are interlaced and electrically Connection; wherein the plurality of vertical scan lines and the plurality of horizontal scan lines are staggered in a plurality of places, and each stagger is electrically connected by a conductor in a via; and the plurality of longitudinal scan lines are arranged in the Between the substrate and the plurality of horizontal scan lines.
  • the substrate is electrically connected to a substrate trace, and the substrate trace is disposed in an external circuit outside the substrate.
  • a width of the longitudinal scan line is less than or equal to a width of the longitudinal data line.
  • one of the plurality of longitudinal scan lines is disposed on the substrate, and the substrate is covered by a first insulating layer, so The first insulating layer covers the plurality of vertical scan lines on the substrate, one of the plurality of horizontal scan lines is disposed on the first insulating layer, and one of the plurality of horizontal scan lines passes through A first via is electrically connected to one of the plurality of vertical scan lines, one of the plurality of horizontal scan lines is covered by a second insulating layer, and a semiconductor material is disposed in the second insulating layer, so A part of the semiconductor material exposes the second insulating layer, and one of the plurality of vertical data lines, a source and a drain are disposed on the second insulating layer, and the source and the drain are located On both sides of the semiconductor material, one of the plurality of vertical data lines, the source electrode, the drain electrode, and the second insulating layer are covered by a third insulating layer, and on the third insulating layer, and on the third insulating layer, and on the third
  • a sealed frame is provided around the display area.
  • a first chip is disposed in the frame area, and the first chip is electrically connected to the plurality of vertical data lines.
  • a second chip is disposed in the frame area, and the second chip is electrically connected to the plurality of vertical scan lines.
  • an ultra-narrow bezel liquid crystal display including: a substrate, a surface of the substrate includes a display area and a bezel area, the bezel area surrounds the display area; a plurality of horizontal scanning lines , Arranged above the substrate and located in the display area; a plurality of longitudinal data lines are arranged above the substrate and located in the display area, the plurality of longitudinal data lines and the plurality of horizontal scanning lines are staggered and Are electrically insulated to define a plurality of pixel regions; and a plurality of vertical scan lines are arranged in the projection range of the plurality of vertical data lines, the plurality of vertical scan lines and the plurality of horizontal scan lines are interlaced and electrically Sexual connection.
  • the substrate is electrically connected to a substrate trace, and the substrate trace is disposed in an external circuit outside the substrate.
  • the plurality of vertical scan lines and the plurality of horizontal scan lines are staggered in a plurality of places, and each staggered place is electrically connected by a conductor in a via hole.
  • the plurality of vertical scan lines are arranged between the substrate and the plurality of horizontal scan lines.
  • a width of the longitudinal scan line is less than or equal to a width of the longitudinal data line.
  • one of the plurality of longitudinal scan lines is disposed on the substrate, and the substrate is covered by a first insulating layer, so The first insulating layer covers the plurality of vertical scan lines on the substrate, one of the plurality of horizontal scan lines is disposed on the first insulating layer, and one of the plurality of horizontal scan lines passes through A first via is electrically connected to one of the plurality of vertical scan lines, one of the plurality of horizontal scan lines is covered by a second insulating layer, and a semiconductor material is disposed in the second insulating layer, so A part of the semiconductor material exposes the second insulating layer, and one of the plurality of vertical data lines, a source and a drain are disposed on the second insulating layer, and the source and the drain are located On both sides of the semiconductor material, one of the plurality of vertical data lines, the source electrode, the drain electrode, and the second insulating layer are covered by a third insulating layer, and on the third insulating layer, and on the third insulating layer, and on the third
  • a sealed frame is provided around the display area.
  • a first chip is disposed in the frame area, and the first chip is electrically connected to the plurality of vertical data lines.
  • a second chip is disposed in the frame area, and the second chip is electrically connected to the plurality of vertical scan lines.
  • Another aspect of the present invention provides an electronic device including the ultra-narrow bezel liquid crystal display as described above.
  • the above-mentioned ultra-narrow bezel liquid crystal display and electronic device of the present invention by arranging the plurality of longitudinal scan lines within the projection range of the plurality of longitudinal data lines, the plurality of longitudinal scan lines and The multiple horizontal scan lines are staggered and electrically connected, and there is no need to provide gate traces in the frame area.
  • the frame area can be reduced without reducing the pixel aperture ratio; in addition, the substrate can be moved
  • the wires are arranged in the external circuit outside the substrate to further reduce the frame area. Therefore, the frame area can be greatly narrowed, so as to achieve a true ultra-narrow frame and increase the screen ratio.
  • FIG. 1 is a schematic top view of an ultra-narrow bezel liquid crystal display according to an embodiment of the invention.
  • FIG. 2 is a schematic cross-sectional view of a pixel area of an ultra-narrow bezel liquid crystal display according to an embodiment of the invention.
  • the ultra-narrow bezel liquid crystal display in one aspect of the present invention may include a substrate 1, a plurality of horizontal scanning lines 2, a plurality of vertical data lines 3, and a plurality of vertical scanning lines 4.
  • a surface of the substrate 1 includes a display area 1a and a frame area 1b.
  • the frame area 1b surrounds the display area 1a; the plurality of horizontal scan lines 2 are arranged above the substrate 1 and located on the display In the area 1a; the plurality of vertical data lines 3 are disposed above the substrate 1 and located in the display area 1a, and the plurality of vertical data lines 3 and the plurality of horizontal scan lines 2 are staggered and electrically insulated to A plurality of pixel regions are defined; the plurality of vertical scan lines 4 are arranged within the projection range of the plurality of vertical data lines 3, and the plurality of vertical scan lines 4 and the plurality of horizontal scan lines 2 are interlaced and electrically connection.
  • the horizontal scan line 2, the vertical data line 3, and the vertical scan line 4 may be composed of multiple metal layers insulated from each other.
  • the following examples illustrate the implementation of the above-mentioned ultra-narrow bezel liquid crystal display, but it is not limited thereto.
  • the substrate 1 is electrically connected to a substrate trace (WOA) 5, and the substrate trace 5 may be disposed in an external circuit outside the substrate 1, so that: The frame area 1b can be further reduced.
  • WA substrate trace
  • the plurality of vertical scan lines 4 and the plurality of horizontal scan lines 2 are staggered at a plurality of places, and a via hole (V1 as shown in FIG. 1
  • the conductor in the via hole V1 can be electrically connected to the material of the vertical scan line 4 or the horizontal scan line 2.
  • the conductor in the via hole V1 can be connected to the horizontal
  • the material of scan line 2 is the same, but not limited to this.
  • the plurality of vertical scan lines 4 may be arranged between the substrate 1 and the plurality of horizontal scan lines 2, so that the vertical scan lines 4 may be far away from the
  • the thin film transistor structure above the horizontal scan line 2 is used to reduce the mutual interference between signals, but not limited to this; the vertical scan line 4 may also be arranged between the substrate 1 and the vertical data line 3, In order to adapt to different needs.
  • a width of the vertical scanning line 4 is less than or equal to a width of the vertical data line 3.
  • the vertical scan line 4 can be moved from the frame area 1b to the display area 1a, and hidden under the vertical data line 3, so as to reduce the frame area 1b. And there is no need to reduce the pixel aperture ratio.
  • the following examples illustrate the pixel area structure of the above embodiment of the present invention, but it is not limited thereto.
  • one of the plurality of longitudinal scanning lines 4 may be provided on the substrate 1, and an appropriate
  • the substrate 1 is covered by a first insulating layer 6a, and the first insulating layer 6a can cover the plurality of vertical scanning lines on the substrate 1.
  • one of the plurality of horizontal scan lines 2 is provided on the first insulating layer 6a, and one of the plurality of horizontal scan lines 2 is electrically connected to the plurality of lines through the first via V1
  • One of the vertical scan lines 4, one of the plurality of horizontal scan lines 2 may be covered by a second insulating layer 6b, and a semiconductor material 71 is disposed in the second insulating layer 6b, a part of the semiconductor material 71 The second insulating layer 6b is exposed, and one of the plurality of vertical data lines 3, a source 72 and a drain 73 can be disposed on the second insulating layer 6b.
  • the source 72 and the drain Electrodes 73 are located on both sides of the semiconductor material 71 to form the thin film transistor 7, one of the plurality of longitudinal data lines 3, the source electrode 72, the drain electrode 73 and the second insulating
  • the layer 6b can be covered by a third insulating layer 6c.
  • a pixel electrode 8 is disposed on the third insulating layer 6c.
  • the pixel electrode 8 can be electrically connected to the drain 73 through a second via V2 for Control the light transmission or light color state of the pixel area.
  • a sealing frame A may be further provided around the display area 1a to seal the liquid crystal material in the display area 1a.
  • the traces in the frame area 1b at the periphery of the display area 1a of the present invention have been removed, and the frame area 1b can be greatly narrowed, for example: less than 0.3 millimeters (mm) to facilitate Realize a true ultra-narrow frame and increase the screen-to-body ratio.
  • a first chip C1 may be further disposed in the frame area 1b, and the first chip C1 is electrically connected to the plurality of vertical data lines 3, for example:
  • a chip C1 can be a chip for (chip on film, COF) control function, and can be arranged above the display area 1a to facilitate the realization of functions required for the operation of the liquid crystal display.
  • a second chip C2 is disposed in the frame area 1b, and the second chip C2 is electrically connected to the plurality of vertical scan lines 4, for example: the second chip C2 can be a chip for COF control function, and can be arranged under the display area 1a to facilitate the realization of functions required for the operation of the liquid crystal display.
  • the electronic device in another aspect of the present invention may include the ultra-narrow bezel liquid crystal display as described above.
  • the electronic device may be configured as a smart watch, a smart phone, a tablet computer, or a notebook computer as required, but not Limit this.
  • the plurality of longitudinal scan lines are arranged within the projection range of the plurality of longitudinal data lines, and the plurality of longitudinal scan lines and the plurality of The horizontal scan lines are staggered and electrically connected.
  • the frame area can be reduced, and the pixel aperture ratio can be reduced; in addition, the substrate traces can also be arranged at all In the external circuit outside the substrate, the frame area is further reduced. Therefore, the frame area can be greatly narrowed, so as to achieve a true ultra-narrow frame and increase the screen ratio.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种超窄边框液晶显示器及电子装置，所述超窄边框液晶显示器包括：一基板，所述基板的一表面包括一显示区域与一边框区域，所述边框区域包围所述显示区域；多条横向扫描线，设置于所述基板上方且位于所述显示区域内；多条纵向数据线，设置于所述基板上方且位于所述显示区域内，所述多条纵向数据线与多条横向扫描线交错且电性绝缘，以定义多个像素区；及多条纵向扫描线，设置于所述多条纵向数据线的投影范围内，所述多条纵向扫描线与所述多条横向扫描线交错且电性连接。

Description

超窄边框液晶显示器及电子装置 技术领域
本发明是有关于一种液晶显示器，特别是有关于一种超窄边框液晶显示器及电子装置。
 背景技术
随着TFT-LCD显示屏技术的演进，TFT-LCD显示屏逐渐朝向可挠、高屏幕占比、抗摔、寿命高、超窄边框或无边框等趋势发展。关于超窄边框显示屏的现有解决方案，举例说明如下。
举例来说，一种是采用Gate Driver on Array(GOA)技术，在Thin Field Transistor(TFT)制程中直接将栅极驱动器集成电路(Gate driver IC)集成在面板(Panel)上，采用GOA电路可以大大缩减边界(Border)区域的面积，例如：边界可以缩至0.6毫米(mm)以下。但GOA电路技术容易出现电路腐蚀、可靠性低、寿命短、良率低等缺点，导致应用领域受限，目前仅用于消费类电子产品。
另一种是采用Twisted Gate line Placed in Pixel(TGPP)技术，但此技术的缺点在于显示区域电容不一致，影响整体显示效果且布线困难。
另一种是采用Tracking Gate line in Pixel(TGP)技术，但此技术的缺点是边界区域会有Wire on array(WOA)走线，导致边界区域很难进一步缩小，且对切割精度要求很高。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明提供一种超窄边框液晶显示器及电子装置，将显示器边界区域的栅极线隐藏到像素的数据线下方，以解决现有技术所存在的边界区域无法缩小的问题。
 技术解决方案
本发明的一方面提供一种超窄边框液晶显示器，包括：一基板，所述基板的一表面包括一显示区域与一边框区域，所述边框区域包围所述显示区域；多条横向扫描线，设置于所述基板上方且位于所述显示区域内；多条纵向数据线，设置于所述基板上方且位于所述显示区域内，所述多条纵向数据线与多条横向扫描线交错且电性绝缘，以定义多个像素区；及多条纵向扫描线，设置于所述多条纵向数据线的投影范围内，所述多条纵向扫描线与所述多条横向扫描线交错且电性连接；其中所述多条纵向扫描线与所述多条横向扫描线在多处交错且在每个交错处以一过孔内的导体电性连接；及所述多条纵向扫描线设置于所述基板与所述多条横向扫描线之间。
在本发明的一实施例中，所述基板电性连接一基板走线，所述基板走线设置于所述基板外的一外部电路中。
在本发明的一实施例中，所述纵向扫描线的一宽度小于或等于所述纵向数据线的一宽度。
在本发明的一实施例中，在所述多个像素区中的一个内，所述多条纵向扫描线中的一条设置在所述基板上，所述基板被一第一绝缘层覆盖，所述第一绝缘层包覆所述基板上的所述多条纵向扫描线，所述第一绝缘层上设置所述多条横向扫描线中的一条，所述多条横向扫描线中的一条经由一第一过孔电性连接所述多条纵向扫描线中的一条，所述多条横向扫描线中的一条被一第二绝缘层覆盖，所述第二绝缘层中设置一半导体材料，所述半导体材料的一部分露出所述第二绝缘层，所述第二绝缘层上设置所述多条纵向数据线中的一条、一源极及一漏极，所述源极与所述漏极位于所述半导体材料的两侧，所述多条纵向数据线中的一条、所述源极、所述漏极及所述第二绝缘层被一第三绝缘层覆盖，所述第三绝缘层上设置一像素电极，所述像素电极经由一第二过孔电性连接所述漏极。
在本发明的一实施例中，所述显示区域的周围设置一密封框体。
在本发明的一实施例中，所述边框区域内设置一第一芯片，所述第一芯片电性连接所述多条纵向数据线。
在本发明的一实施例中，所述边框区域内设置一第二芯片，所述第二芯片电性连接所述多条纵向扫描线。
本发明的另一方面提供一种超窄边框液晶显示器，包括：一基板，所述基板的一表面包括一显示区域与一边框区域，所述边框区域包围所述显示区域；多条横向扫描线，设置于所述基板上方且位于所述显示区域内；多条纵向数据线，设置于所述基板上方且位于所述显示区域内，所述多条纵向数据线与多条横向扫描线交错且电性绝缘，以定义多个像素区；及多条纵向扫描线，设置于所述多条纵向数据线的投影范围内，所述多条纵向扫描线与所述多条横向扫描线交错且电性连接。
在本发明的一实施例中，所述基板电性连接一基板走线，所述基板走线设置于所述基板外的一外部电路中。
在本发明的一实施例中，所述多条纵向扫描线与所述多条横向扫描线在多处交错且在每个交错处以一过孔内的导体电性连接。
在本发明的一实施例中，所述多条纵向扫描线设置于所述基板与所述多条横向扫描线之间。
在本发明的一实施例中，所述纵向扫描线的一宽度小于或等于所述纵向数据线的一宽度。
在本发明的一实施例中，在所述多个像素区中的一个内，所述多条纵向扫描线中的一条设置在所述基板上，所述基板被一第一绝缘层覆盖，所述第一绝缘层包覆所述基板上的所述多条纵向扫描线，所述第一绝缘层上设置所述多条横向扫描线中的一条，所述多条横向扫描线中的一条经由一第一过孔电性连接所述多条纵向扫描线中的一条，所述多条横向扫描线中的一条被一第二绝缘层覆盖，所述第二绝缘层中设置一半导体材料，所述半导体材料的一部分露出所述第二绝缘层，所述第二绝缘层上设置所述多条纵向数据线中的一条、一源极及一漏极，所述源极与所述漏极位于所述半导体材料的两侧，所述多条纵向数据线中的一条、所述源极、所述漏极及所述第二绝缘层被一第三绝缘层覆盖，所述第三绝缘层上设置一像素电极，所述像素电极经由一第二过孔电性连接所述漏极。
在本发明的一实施例中，所述显示区域的周围设置一密封框体。
在本发明的一实施例中，所述边框区域内设置一第一芯片，所述第一芯片电性连接所述多条纵向数据线。
在本发明的一实施例中，所述边框区域内设置一第二芯片，所述第二芯片电性连接所述多条纵向扫描线。
本发明的另一方面提供一种电子装置，包括如上所述的超窄边框液晶显示器。
 有益效果
与现有技术相比较，本发明上述超窄边框液晶显示器及电子装置，通过将所述多条纵向扫描线设置于所述多条纵向数据线的投影范围内，所述多条纵向扫描线与所述多条横向扫描线交错且电性连接，无须在所述边框区域设置栅极走线，可缩小所述边框区域，且无需减小像素开口率；此外，还可通过将所述基板走线设置于所述基板外的外部电路中，进一步缩小所述边框区域。从而，所述边框区域可以大幅窄化，以利实现真正的超窄边框，以及提高屏幕占比。
 附图说明
图1是本发明一实施例的超窄边框液晶显示器的上视示意图。
图2是本发明一实施例的超窄边框液晶显示器的像素区的截面示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图1所示，本发明的一方面的超窄边框液晶显示器可包括一基板1、多条横向扫描线2、多条纵向数据线3及多条纵向扫描线4。所述基板1的一表面包括一显示区域1a与一边框区域1b，所述边框区域1b包围所述显示区域1a；所述多条横向扫描线2设置于所述基板1上方且位于所述显示区域1a内；所述多条纵向数据线3设置于所述基板1上方且位于所述显示区域1a内，所述多条纵向数据线3与多条横向扫描线2交错且电性绝缘，以定义多个像素区；所述多条纵向扫描线4设置于所述多条纵向数据线3的投影范围内，所述多条纵向扫描线4与所述多条横向扫描线2交错且电性连接。其中，所述横向扫描线2、纵向数据线3及纵向扫描线4可由相互绝缘的多层金属层构成。以下举例说明上述超窄边框液晶显示器的实施方式，但不以此为限。
在一实施例中，如图1所示，所述基板1电性连接一基板走线(WOA)5，所述基板走线5可设置于所述基板1外的一外部电路中，从而，可以进一步缩小所述边框区域1b。
在一实施例中，如图1所示，所述多条纵向扫描线4与所述多条横向扫描线2在多处交错且在每个交错处以一过孔(如图1所示的V1)内的导体电性连接，所述过孔V1内的导体可以与所述纵向扫描线4或所述横向扫描线2的材料相同，例如：所述过孔V1内的导体可以与所述横向扫描线2的材料相同，但不以此为限。
在一实施例中，如图2所示，所述多条纵向扫描线4可设置于所述基板1与所述多条横向扫描线2之间，使得所述纵向扫描线4可以远离所述横向扫描线2上方的薄膜电晶体构造，以减少信号间的相互干扰，但不以此为限；所述纵向扫描线4也可设置于所述基板1与所述纵向数据线3之间，以利适应不同需求。
在本发明的一实施例中，如图1所示，所述纵向扫描线4的一宽度小于或等于所述纵向数据线3的一宽度。相较于现有技术，可将所述纵向扫描线4从所述边框区域1b移到所述显示区域1a内，并且隐藏在所述纵向数据线3下方，以利缩小所述边框区域1b，且无需减小像素开口率。以下举例说明本发明上述实施例的像素区构造，但不以此为限。
举例来说，如图2所示，在所述多个像素区中的一个内，所述多条纵向扫描线4中的一条可设置在所述基板1上，所述基板1上方可设置适当的绝缘构造，以利设置一薄膜电晶体7，例如：所述基板1被一第一绝缘层6a覆盖，所述第一绝缘层6a可包覆所述基板1上的所述多条纵向扫描线4，所述第一绝缘层6a上设置所述多条横向扫描线2中的一条，所述多条横向扫描线2中的一条经由所述第一过孔V1电性连接所述多条纵向扫描线4中的一条，所述多条横向扫描线2中的一条可被一第二绝缘层6b覆盖，所述第二绝缘层6b中设置一半导体材料71，所述半导体材料71的一部分露出所述第二绝缘层6b，所述第二绝缘层6b上可设置所述多条纵向数据线3中的一条、一源极72及一漏极73，所述源极72与所述漏极73位于所述半导体材料71的两侧，以形成所述薄膜电晶体7，所述多条纵向数据线3中的一条、所述源极72、所述漏极73及所述第二绝缘层6b可被一第三绝缘层6c覆盖，所述第三绝缘层6c上设置一像素电极8，所述像素电极8可经由一第二过孔V2电性连接所述漏极73，用以控制所述像素区的透光或光色状态。
在一实施例中，如图1所示，所述显示区域1a的周围还可设置一密封框体A，用以密封在所述显示区域1a内的液晶材料。与现有技术相较，本发明的所述显示区域1a外围的边框区域1b中走线已被移出，所述边框区域1b可以大幅窄化，例如：做到0.3毫米(mm)以下，以利实现真正的超窄边框，以及提高屏幕占比。
在一实施例中，如图1所示，所述边框区域1b内还可设置一第一芯片C1，所述第一芯片C1电性连接所述多条纵向数据线3，例如：所述第一芯片C1可为用于(chip on film，COF)控制功能的芯片，可设置于所述显示区域1a上方，以利实现液晶显示器的运作所需功能。
在一实施例中，如图1所示，所述边框区域1b内设置一第二芯片C2，所述第二芯片C2电性连接所述多条纵向扫描线4，例如：所述第二芯片C2可为用于COF控制功能的芯片，可设置于所述显示区域1a下方，以利实现液晶显示器的运作所需功能。
此外，本发明的另一方面的电子装置可包括如上所述的超窄边框液晶显示器，例如：所述电子装置可依需求被配置成智能手表、智能手机、平板电脑或笔记本电脑等，但不以此为限。
本发明上述实施例的超窄边框液晶显示器及电子装置，通过将所述多条纵向扫描线设置于所述多条纵向数据线的投影范围内，所述多条纵向扫描线与所述多条横向扫描线交错且电性连接，无须在所述边框区域设置栅极走线，可缩小所述边框区域，且无需减小像素开口率；此外，还可通过将所述基板走线设置于所述基板外的外部电路中，进一步缩小所述边框区域。从而，所述边框区域可以大幅窄化，以利实现真正的超窄边框，以及提高屏幕占比。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (17)

  1. 一种超窄边框液晶显示器，其包括：
    一基板，所述基板的一表面包括一显示区域与一边框区域，所述边框区域包围所述显示区域；
    多条横向扫描线，设置于所述基板上方且位于所述显示区域内；
    多条纵向数据线，设置于所述基板上方且位于所述显示区域内，所述多条纵向数据线与多条横向扫描线交错且电性绝缘，以定义多个像素区；及
    多条纵向扫描线，设置于所述多条纵向数据线的投影范围内，所述多条纵向扫描线与所述多条横向扫描线交错且电性连接；
    其中所述多条纵向扫描线与所述多条横向扫描线在多处交错且在每个交错处以一过孔内的导体电性连接；及
    其中所述多条纵向扫描线设置于所述基板与所述多条横向扫描线之间。
  2. 如权利要求1所述的超窄边框液晶显示器，其中所述基板电性连接一基板走线，所述基板走线设置于所述基板外的一外部电路中。
  3. 如权利要求1所述的超窄边框液晶显示器，其中所述纵向扫描线的一宽度小于或等于所述纵向数据线的一宽度。
  4. 如权利要求1所述的超窄边框液晶显示器，其中在所述多个像素区中的一个内，所述多条纵向扫描线中的一条设置在所述基板上，所述基板被一第一绝缘层覆盖，所述第一绝缘层包覆所述基板上的所述多条纵向扫描线，所述第一绝缘层上设置所述多条横向扫描线中的一条，所述多条横向扫描线中的一条经由一第一过孔电性连接所述多条纵向扫描线中的一条，所述多条横向扫描线中的一条被一第二绝缘层覆盖，所述第二绝缘层中设置一半导体材料，所述半导体材料的一部分露出所述第二绝缘层，所述第二绝缘层上设置所述多条纵向数据线中的一条、一源极及一漏极，所述源极与所述漏极位于所述半导体材料的两侧，所述多条纵向数据线中的一条、所述源极、所述漏极及所述第二绝缘层被一第三绝缘层覆盖，所述第三绝缘层上设置一像素电极，所述像素电极经由一第二过孔电性连接所述漏极。
  5. 如权利要求1所述的超窄边框液晶显示器，其中所述显示区域的周围设置一密封框体。
  6. 如权利要求1所述的超窄边框液晶显示器，其中所述边框区域内设置一第一芯片，所述第一芯片电性连接所述多条纵向数据线。
  7. 如权利要求1所述的超窄边框液晶显示器，其中所述边框区域内设置一第二芯片，所述第二芯片电性连接所述多条纵向扫描线。
  8. 一种超窄边框液晶显示器，其包括：
    一基板，所述基板的一表面包括一显示区域与一边框区域，所述边框区域包围所述显示区域；
    多条横向扫描线，设置于所述基板上方且位于所述显示区域内；
    多条纵向数据线，设置于所述基板上方且位于所述显示区域内，所述多条纵向数据线与多条横向扫描线交错且电性绝缘，以定义多个像素区；及
    多条纵向扫描线，设置于所述多条纵向数据线的投影范围内，所述多条纵向扫描线与所述多条横向扫描线交错且电性连接。
  9. 如权利要求8所述的超窄边框液晶显示器，其中所述基板电性连接一基板走线，所述基板走线设置于所述基板外的一外部电路中。
  10. 如权利要求8所述的超窄边框液晶显示器，其中所述多条纵向扫描线与所述多条横向扫描线在多处交错且在每个交错处以一过孔内的导体电性连接。
  11. 如权利要求8所述的超窄边框液晶显示器，其中所述多条纵向扫描线设置于所述基板与所述多条横向扫描线之间。
  12. 如权利要求8所述的超窄边框液晶显示器，其中所述纵向扫描线的一宽度小于或等于所述纵向数据线的一宽度。
  13. 如权利要求8所述的超窄边框液晶显示器，其中在所述多个像素区中的一个内，所述多条纵向扫描线中的一条设置在所述基板上，所述基板被一第一绝缘层覆盖，所述第一绝缘层包覆所述基板上的所述多条纵向扫描线，所述第一绝缘层上设置所述多条横向扫描线中的一条，所述多条横向扫描线中的一条经由一第一过孔电性连接所述多条纵向扫描线中的一条，所述多条横向扫描线中的一条被一第二绝缘层覆盖，所述第二绝缘层中设置一半导体材料，所述半导体材料的一部分露出所述第二绝缘层，所述第二绝缘层上设置所述多条纵向数据线中的一条、一源极及一漏极，所述源极与所述漏极位于所述半导体材料的两侧，所述多条纵向数据线中的一条、所述源极、所述漏极及所述第二绝缘层被一第三绝缘层覆盖，所述第三绝缘层上设置一像素电极，所述像素电极经由一第二过孔电性连接所述漏极。
  14. 如权利要求8所述的超窄边框液晶显示器，其中所述显示区域的周围设置一密封框体。
  15. 如权利要求8所述的超窄边框液晶显示器，其中所述边框区域内设置一第一芯片，所述第一芯片电性连接所述多条纵向数据线。
  16. 如权利要求8所述的超窄边框液晶显示器，其中所述边框区域内设置一第二芯片，所述第二芯片电性连接所述多条纵向扫描线。
  17. 一种电子装置，其包括如权利要求8所述的超窄边框液晶显示器。
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CN110488546A (zh) * 2019-08-21 2019-11-22 深圳市华星光电半导体显示技术有限公司 阵列基板、液晶显示面板及液晶显示器
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102103293A (zh) * 2009-12-18 2011-06-22 胜华科技股份有限公司 窄边框显示面板与应用其的电子装置
CN104808356A (zh) * 2014-01-28 2015-07-29 元太科技工业股份有限公司 像素阵列
CN104809954A (zh) * 2014-01-23 2015-07-29 元太科技工业股份有限公司 像素阵列
CN109976058A (zh) * 2019-04-17 2019-07-05 深圳市华星光电半导体显示技术有限公司 超窄边框液晶显示器及电子装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005165051A (ja) * 2003-12-03 2005-06-23 Seiko Epson Corp 電気光学装置及び電子機器
CN101114087A (zh) * 2006-07-25 2008-01-30 奇美电子股份有限公司 薄膜晶体管基板及其制造方法以及在液晶显示面板中的应用
JP5223418B2 (ja) * 2008-04-01 2013-06-26 セイコーエプソン株式会社 電気光学装置及び電子機器
CN101738799B (zh) * 2008-11-06 2011-09-07 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN101527306B (zh) * 2009-04-14 2011-01-05 深圳华映显示科技有限公司 主动组件数组基板及液晶显示面板
CN103744239A (zh) * 2013-12-26 2014-04-23 深圳市华星光电技术有限公司 一种内嵌式触控阵列基板结构
CN104035257B (zh) * 2014-06-26 2017-02-15 南京中电熊猫液晶显示科技有限公司 像素阵列及其制作方法、显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102103293A (zh) * 2009-12-18 2011-06-22 胜华科技股份有限公司 窄边框显示面板与应用其的电子装置
CN104809954A (zh) * 2014-01-23 2015-07-29 元太科技工业股份有限公司 像素阵列
CN104808356A (zh) * 2014-01-28 2015-07-29 元太科技工业股份有限公司 像素阵列
CN109976058A (zh) * 2019-04-17 2019-07-05 深圳市华星光电半导体显示技术有限公司 超窄边框液晶显示器及电子装置

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