CN108122902A - 平面型的或非平面型的基于fet的静电放电保护器件 - Google Patents
平面型的或非平面型的基于fet的静电放电保护器件 Download PDFInfo
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- CN108122902A CN108122902A CN201710733120.6A CN201710733120A CN108122902A CN 108122902 A CN108122902 A CN 108122902A CN 201710733120 A CN201710733120 A CN 201710733120A CN 108122902 A CN108122902 A CN 108122902A
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- protective device
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Classifications
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- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
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- H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract
本发明的实施例涉及一种静电放电(ESD)保护器件,具有连接至第一电节点的源极区、连接至与第一电节点不同的第二电极的第一漏极区,以及位于源极区和第一漏极区之间的扩展漏极区。扩展漏极区包括N个电浮动掺杂区和连接至第二电极的M个栅极区,其中,N和M是大于1的整数并且N等于M。N个电浮动掺杂区的每一个电浮动掺杂区与M个栅极区的每一个栅极区相间布置。本发明的实施例还涉及一种集成电路(IC)。
Description
技术领域
本发明的实施例总体涉及半导体领域,更具体地,涉及静电放电保护器件。
背景技术
本发明通常涉及集成电路(IC)的静电放电保护器件。
静电放电(ESD)事件能够严重损坏包括IC在内的电子组件。在ESD事件期间,在狭小区域内产生大量的热,这就需要快速去除热量以防止对IC产生任何的损害。ESD事件是大量电势瞬间积聚的结果,通常导致ESD事件的原因是与静电场直接或间接接触。能够导致损害IC的ESD事件的各种因素包括与人体或机器(诸如,不当接地的测试设备或其他电气组件)的接触。ESD保护器件容纳在各种电子装置中以防止或降低对IC的损害。
倾向于更小的且更快的电路的这种趋势已经增强了集成电路对ESD事件的敏感度并且增大了设计有效的ESD保护器件的复杂度。
发明内容
根据本发明的一个方面,提供了一种静电放电(ESD)保护器件,包括:源极区,连接至第一电节点;第一漏极区,连接至不同于所述第一电节点的第二电节点;以及扩展漏极区,位于所述源极区和所述第一漏极区之间,所述扩展漏极区包括:N个电浮动掺杂区;和M个栅极区,连接至所述第二电节点,其中,N和M是大于1的整数,并且其中,所述N个电浮动掺杂区中的一个或多个浮动掺杂区与所述M个栅极区中的一个或多个栅极区相间布置。
根据本发明的另一个方面,提供了一种静电放电(ESD)保护器件,包括:第一阱区,具有第一导电类型;源极区,具有与所述第一导电类型不同的第二导电类型,所述源极区位于所述第一阱区内;第一漏极区,具有所述第二导电类型;以及扩展漏极区,具有电浮动掺杂区和栅极区,其中,所述扩展漏极区的第一部分位于所述第一阱区内。
根据本发明的又一个方面,提供了一种集成电路(IC),包括:I/O焊盘;电源轨;静电放电(ESD)保护器件,连接至所述I/O焊盘和所述电源轨,所述ESD保护器件包括:源极区,连接至所述电源轨;漏极区,连接至所述I/O焊盘;和扩展漏极区,位于所述源极区和所述漏极区之间的,所述扩展漏极区包括:电浮动掺杂区,和栅极区,连接至所述I/O焊盘,其中,所述电浮动掺杂区中的每一个与所述栅极区中的每一个相间布置;以及ESD保护电路,与所述ESD保护器件并联。
附图说明
当结合附图进行阅读时,通过下列详细的描述,可以更好地理解本发明的各方面。应该强调的是,根据工业中的标准实践,没有按比例绘制各种部件。实际上,为了清楚地讨论,可以任意地增加或减小各种部件的数量和尺寸。
图1和图2是示例性的ESD保护器件的平面图和截面图。
图3是图1和图2中的示例性的ESD保护器件的等效电路图。
图4是一种示例性的基于PMOS的ESD保护器件的电路图。
图5和图6是示例性的基于finFET的ESD保护器件的平面图。
图7和图8是示例性的基于NMOS漏极扩展的ESD保护器件的平面图和截面图。
图9是示例性的基于PMOS漏极扩展的ESD保护器件的截面图。
图10是一种示例性的基于finFET漏极扩展的ESD保护器件。
图11和图12是示例性的基于堆叠NMOS漏极扩展的ESD保护器件的平面图和截面图。
图13是图11和图12中的示例性的ESD保护器件的等效电路图。
图14是示例性的基于堆叠finFET漏极扩展的ESD保护器件的平面图。
图15和图16是示例性的漏极扩展的NMOS ESD保护器件的平面图和截面图。
图17和图18是示例性的漏极扩展堆叠的NMOS ESD保护器件的平面图和截面图。
图19是示例性的基于finFET漏极扩展的ESD保护器件的平面图。
图20是示例性的基于PMOS漏极扩展的ESD保护器件的截面图。
图21是示例性的基于NMOS的ESD保护器件的电路图。
图22是示例性的具有镇流电阻器的基于NMOS的ESD保护器件的电路图。
图23是图22中的示例性的基于NMOS的ESD保护器件的平面图。
现将参照附图描述示出的实施例。在附图中,相同的参考符号通常表示相同的、功能相似的、和/或结构相似的元件。
具体实施方式
下列发明提供了多种不同实施例或实例,用于实现所供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不旨在限制本发明。例如,在以下描述中,在第二部件上方形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。如本文所用,在第二部件上形成第一部件表明第一部件与第二部件直接接触。另外,本发明可以在多个实例中重复参考符号和/或字符。这种重复其本身不表示所述多个实施例和/或配置之间的关系。
此文中可使用诸如“在…之下”、“在…下面”、“下面的”、“在…上面”、以及“上面的”等的空间关系术语,以容易地描述如图中所示的一个元件或部件与另一元件(多个元件)或部件(多个部件)的关系。除图中所示的方位之外,空间关系术语将包括使用或操作中的装置的各种不同的方位。装置可以以其他方式定位(旋转90度或在其他方位),并且通过在此使用的空间关系描述符进行相应地解释。
应该注意,说明书中的参照“一个实施例”、“实施例”、“一个实例实施例”、“示例性的”等表示所述实施例可包括特定的部件、结构或特征,但是不是每一个实施例必须包括特定的部件、结构或特征。此外,这样的短语不一定参照相同的实施例。并且,当描述关于一个实施例的特定部件、结构或特征时,不管是否有明确描述,本领域的技术人员会实现关于其他实施例的这种部件、结构或特征的作用。
应该理解,本文的语法或术语是用于描述的目的而非限制的目的,使得在本文的教导下,本领域的技术人员能够理解本说明书的语法或术语。
如本文使用的术语“大约”表示给定量的值随着值的±10%的变化而变化,除非另有说明。
如本文所使用的术语“衬底”,其描述了一种在其上增加后续材料层的材料。衬底本身可被图案化,并且在其顶部增加的材料也可以被图案化,或不被图案化仍保留原样。此外,“衬底”可以是诸如硅、锗、砷化镓、磷化铟等的各种半导体材料中的任意一种。可选地,衬底可以是非导电的材料,诸如玻璃或蓝宝石晶圆。
如本文中所使用的术语“垂直的”,其表示标称地垂直于衬底的表面。
除非另有描述,否则本文公开的P阱可通过将衬底掺杂p型掺杂剂而形成。
除非另有描述,否则本文公开的N阱可通过将衬底掺杂n型掺杂剂而形成。
概述
本发明提供了比当前的FET基ESD保护器件具有提高的性能的平面和非平面的FET基ESD保护器件的各种示例性配置。例如,与当前的ESD器件相比,本文公开的ESD保护器件提供了较高的导通一致性、较高的驱动电流、适于ESD事件期间较快散热的更大体积、以及在ESD保护器件的断开状态期间的较低泄漏电流。此外,本文公开的finFET基ESD器件包括扩展漏极区,其满足半导体制造工艺中限制性设计规则(RDR)的最小多晶硅-多晶硅间距要求。
示例性的ESD保护器件
图1是一种示例性的IC中的n沟道金属氧化物半导体(NMOS)基保护器件100的顶视图。图2是图1的ESD保护器件100的截面图。
ESD保护器件100包括p型衬底102上的P阱104、浅沟槽隔离(STI)区106、彼此并联连接的NMOS晶体管M1和M2、寄生NPN晶体管Q1和Q2、以及寄生电阻R1和R2。晶体管M1包括在P阱104中形成的N+掺杂区108和110以及在P阱104上形成的栅极112。在一些实施例中,P阱104是可选的并且N+掺杂区108和110形成在P衬底102中。N+掺杂区108可被配置为源极区且连接至电源轨VSS,以及N+掺杂区110可被配置为漏极区且连接至IC的焊盘。在一些实施例中,IC的焊盘是附接至ESD保护电路的一个或多个I/O焊盘或引脚的接合焊盘。栅极112可连接至电压源或电源轨VSS。在一些实施例中,电源轨VSS处于地电势。
寄生NPN晶体管Q1包括作为集电极的N+掺杂区110、作为基极的P阱104和作为发射极的N+掺杂区108。NPN晶体管Q1的基极通过寄生电阻器R1连接至P+掺杂区114,R1表示在M1形成在P衬底102中时P阱104或P衬底102的固有电阻。P+掺杂区114可连接至电源轨VSS。ESD保护器件100还包括被电隔离的伪栅极116。
晶体管M2,Q2和电阻器R2在结构和功能方面可分别与晶体管M1,Q1和电阻器R1相似,并且可形成晶体管M1,Q1和电阻器R1布置的镜像。晶体管M2包括形成在P阱104中的N+掺杂区118和120以及形成在P阱104中的栅极122。N+掺杂区118可被配置为源极区且连接至电源轨VSS以及N+掺杂区120可被配置为漏极区且连接至IC的焊盘。栅极122可连接至电压源或电源轨VSS。寄生NPN晶体管Q2包括作为集电极的N+掺杂区120、作为基极的P阱104和作为发射极的N+掺杂区118。NPN晶体管Q2的基极通过寄生电阻器R2连接至P+掺杂区124,R2表示在M2形成在P衬底102中时P阱104或P衬底102的固有电阻。P+掺杂区124可连接至电源轨VSS。在一些实施例中,晶体管M1和M2被栅极125间隔开,栅极125以与N+掺杂区110和120相同的电势(例如,焊盘的电势)连接。
晶体管M1,M2,Q1,Q2和电阻器R1和R2连同STI区106、P+掺杂区114,124以及伪栅极116的排列可根据ESD保护器件100所需的电流容量多次重复。应该注意,ESD保护器件100可基于晶体管M1,Q1和电阻器R1的单一排列。
P衬底102和p阱104包括半导体材料,诸如但不限于,硅、锗、包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟的复合半导体、包括碳化硅锗、硅锗、磷化镓砷、磷化镓铟、砷化镓铟的合金或它们的组合。此外,p衬底102和p阱104掺杂有诸如硼、铟、铝或镓的p型掺杂剂。在一些实施例中,p衬底102可包括与p阱104的材料和掺杂浓度相似或不同的材料和掺杂浓度。STI区106由介电材料制成。在一些实施例中,STI区106包括氧化硅、氮化硅、氮氧化硅、氟掺杂硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料。N+掺杂区108,110,118和120可掺杂有诸如磷、砷或它们的组合的n型掺杂剂并且可具有大于每立方厘米1×1019个原子的掺杂浓度。P+掺杂区114和124可掺杂有诸如硼、铟、铝、镓或它们的组合的p型掺杂剂并且可具有大于每立方厘米1×1019个原子的掺杂浓度。
栅极112和122分别包括栅电极和介电层(未示出)。在一些实施例中,介电层包括氧化硅、氮化硅、氮氧化硅或高k介电材料(诸如氧化铪(HfO2)、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2)或它们的组合的一个层或多个层。可选地,高k介电材料可包括金属氧化物。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物和/或它们的混合物。可通过化学汽相沉积(CVD)、原子层沉积(ALD)、物理汽相沉积(PVD)、电子束蒸发或其他合适的工艺形成介电层。
栅电极可包括栅极功函数金属层和栅极金属填充层。在一些实施例中,栅极功函数金属层包括任何合适的材料,诸如铝(Al)、铜(Cu)、钨(W)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、硅化镍(NiSi)、硅化钴(CoSi)、银(Ag)、碳化钽(TaC)、氮化钽硅(TaSiN)、氮碳化钽(TaCN)、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钨(WN)、金属合金和/或它们的组合。可使用诸如ALD、CVD、PVD、电镀的合适工艺或它们的组合可形成栅极功函数金属层。在一些实施例中,栅极金属填充层包括任意合适的导电材料,诸如,Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、WN、Cu、W、Co、Ni、TiC、TiAlC、TaAlC、金属合金和/或它们的组合。可通过ALD、PVD、CVD或其他合适的导电材料沉积工艺形成栅极金属填充层124。
在一些实施例中,栅极125和伪栅极116包括与栅极112和122相似的栅电极和介电层。在一些实施例中,栅极125和/或伪栅极116包括多晶硅结构。
图3示出了示例性的连接至ESD保护电路的ESD保护器件100的等效电路图。NMOS晶体管M1和M2并联,其中,它们的漏极区和源极区分别连接至焊盘和电源轨VSS。NPN晶体管Q1和Q2并联,其中,它们的集电极和发射极分别连接至焊盘和电源轨VSS,并且它们的基极分别通过寄生电阻器R1和R2连接至电源轨VSS。
ESD保护器件100在导通状态和截止状态的两种模式下进行工作,下文将参照图1至图3对其进行讨论。导通状态是在ESD事件期间,而ESD事件可以是大量电势在焊盘处的瞬间积聚,其通常由与静电场的直接或间接接触导致的。在ESD事件期间,ESD保护器件100在不损坏ESD保护电路的情况下向要被放电的ESD充电电流提供低阻抗放电路径326和328(图3)。放电路径326在图1和图2中被表示为从N+掺杂区110至P阱104的路径a以及从P阱104至N+掺杂区108的路径b。同样地,放电路径328在图1和图2中被表示为从N+掺杂区120至P阱104的路径c以及从P阱104至N+掺杂区118的路径d。
在ESD事件期间,为N+掺杂区110/P阱104结的路径a被反向偏置且可包括泄漏电流,以及为P阱104/N+掺杂区108结的路径b为正向偏置。因此,寄生晶体管Q1为导通状态且ESD充电电流的至少部分通过路径a(图1至图2)从焊盘流至电源轨VSS,即,等效的放电路径326(图3)而不穿过受ESD保护的电路。当寄生晶体管Q2在ESD事件期间以与寄生晶体管Q1相似的方式导通时,ESD充电电流的另一部分流穿路径b(图1至图2),即,等效的放电路径328(图3)。
截止状态是在受ESD保护的电路的正常工作期间,即,没有发生ESD事件。在正常工作期间,ESD保护器件100相较于受ESD保护的电路提供了高阻抗以不影响电流流向受ESD保护的电路。
图4示出了一种示例性的IC的连接至受ESD保护的电路的ESD保护器件100*的电路图。ESD保护器件100*在布置上与ESD保护器件100相似,但是ESD保护器件100*基于p型晶体管。ESD保护器件100*包括并联连接的PMOS晶体管M1*和M2*,晶体管M1*和M2*的源极区和漏极区分别连接至电源轨VDD和IC的焊盘。PNP晶体管Q1*和Q2*并联连接,它们的集电极和发射极分别连接至电源轨VDD和焊盘,以及它们的基极通过寄生电阻器R1*和R2*分别连接至电源轨VDD。寄生电阻器R1*和R2*表示其内形成有晶体管Q1*和Q2*的N阱(未示出)的固有电阻。寄生PNP晶体管Q1*和Q2*包括作为集电极的晶体管M1*和M2*的漏极区、作为基极的形成在p衬底上的N阱、以及作为发射极的晶体管M1*和M2*的源极区。ESD保护器件100*可以以与ESD保护器件100相似的方式进行操作,但是极性相反。在ESD事件期间,ESD充电电流通过放电路径326*和328*从电源轨VDD至焊盘放电。
图5是一种示例性ESD保护器件500的平面图,该ESD保护器件500在结构和功能上可与ESD保护器件100相似。下文将对ESD保护器件100和500之间的区别进行讨论。使用多鳍n型finFET FF1和FF2而不是使用ESD保护器件100的平面型的NMOS晶体管M1和M2实现ESD保护器件500。FinFET FF1和FF2可包括一个或多个鳍件并且不限于图5中所示的四个鳍。FinFET FF1和FF2并联。FinFET FF1和FF2包括栅极512和522、分别配置为源极区的N+掺杂区508和518、以及分别配置为源极区的N+掺杂区510和520。FinFET FF1和FF2以类似于ESD保护器件100的晶体管M1和M2的方式分别连接至焊盘和电源轨VSS。ESD保护器件500还包括作为ESD保护器件100的寄生NPN晶体管Q1和Q2的形成在finFET FF1和FF2的N+掺杂区与P阱104之间的寄生NPN晶体管。例如,由作为集电极的N+掺杂区510、作为发射极的N+掺杂区508和作为基极的P阱104形成寄生晶体管,其中,基极通过寄生电阻器连接至P+掺杂区514,寄生电阻器表示P阱104的固有电阻或当finFET FF1形成在P衬底102中时P衬底102的固有电阻。与ESD保护器件100相似,ESD保护器件的寄生NPN晶体管在ESD事件期间提供放电路径。
在功能和材料组成方面与伪栅极116和栅极125相似的伪栅极516和栅极525也包含在ESD保护器件500中。N+掺杂区508,510,518,520、P+掺杂区514,524和栅极512,522的材料组成分别与N+掺杂区108,110,118,120、P+掺杂区114,124和栅极112,122的材料组成相似。
N+掺杂区508,510,518,520是finFET FF1和FF2的外延鳍区,外延鳍区包括外延生长在P衬底102或P阱104上的半导体材料。外延生长的半导体材料可包括:诸如锗或硅的半导体材料;或诸如砷化镓、砷化铝镓的化合物半导体材料;或诸如硅锗或磷砷化镓的半导体合金。在一些实施例中,通过CVD(例如,低压CVD(LPCVD)、原子层CVD(ALCVD)、超高真空CVD(UHVCVD)、减压CVD(RPCVD)、任意合适的CVD)、分子束外延(MBE)工艺、任意合适的外延工艺、或任意它们的组合生长出finFET FF1和FF2的外延鳍区。在一些实施例中,通过外延沉积/局部蚀刻工艺生长出外延鳍区,至少重复进行外延沉积/局部蚀刻工艺一次。这种重复的沉积/局部蚀刻工艺还被称为循环沉积蚀刻(CDE)工艺。在外延生长工艺期间FinFET FF1和FF2的外延鳍区可原位掺杂。在各种实施例中,外延区可掺杂有n型掺杂剂,诸如磷或砷和/或它们的组合;可使用诸如但不限于三氢化磷(PH3)、砷化氢(AsH3)的n型掺杂前体和/或使用其他n型掺杂前体。通过使用原位掺杂工艺,能够最佳地控制和实现外延生长的半导体材料的掺杂浓度。在一些实施例中,外延鳍区不是原位掺杂,并且实施离子注入工艺以掺杂finFET FF1和FF2的外延鳍区。N+掺杂区508,510,518,520的掺杂浓度可大于每立方厘米1×1019个原子。
图6是一种示例性的ESD保护器件600的平面图,其除了finFET FF1*和FF2*的扩展N+漏极区510*和520*以外可与ESD保护器件500相似。扩展N+漏极区510*和520*可有助于降低正常操作期间的泄漏电流以及由此降低功耗,这在例如finFET技术或亚微米技术节点方面很重要。然而,与诸如510(图5)的非扩展漏极区相比,通过形成较长的漏极区来形成诸如510*的扩展漏极区增大了诸如栅极512和525的相邻栅极之间的间距,这样超出了半导体制造工艺中限制性设计规则(RDR)的多晶硅至多晶硅间距要求。多晶硅至多晶硅间距可被定义为根据RDR设定的相邻栅极结构之间的最小间距。例如,相邻的栅极512和525之间的间距可被称为多晶硅至多晶硅间距。
下文将讨论具有扩展漏极区的ESD保护器件的各种实施例,该ESD保护器件满足半导体制造工艺中RDR的多晶硅至多晶硅间距要求。
具有扩展漏极区的示例性ESD保护器件
图7是一种示例性的IC中的基于漏极扩展NMOS的ESD保护器件700的平面图。图8是图7的ESD保护器件700的示例性截面图。ESD保护器件700在结构、组成和功能方面与ESD保护器件100相似。下文将讨论ESD保护器件100和700之间的区别。
ESD保护器件700包括漏极扩展NMOS晶体管M3和M4,这些晶体管具有被配置为源极区的N+掺杂区108,118、被配置为漏极区的N+掺杂区110和120、栅极112和122、以及分别位于区108和110之间和区118和120之间的扩展漏极区。扩展漏极区包括浮动N+掺杂区730和734以及连接至与N+掺杂区110和120相同电势(例如,焊盘的电势)的三个栅极732和三个栅极736。三个栅极732中相邻栅极之间的间距和三个栅极736中相邻栅极之间的间距满足RDR的多晶硅至多晶硅间距要求。因此,通过增加成对的具有与漏极区110和120相似的掺杂的掺杂区和增加连接至与漏极区110和120相同的电势的栅极来扩展晶体管M3和M4的漏极区110和120有助于增加NMOS晶体管M3和M4的漏极电阻,同时满足RDR的多晶硅至多晶硅间距要求。增加漏极电阻可有助于提高ESD保护器件700的一致性,这样会有助于同时导通ESD保护器件700的所有放电路径。晶体管M3和M4的扩展漏极区可分别包括一个或多个浮动N+掺杂区730和734以及一个或多个栅极732和736,但不限于图7至图8中的浮动N+掺杂区730和734以及栅极732和736的数量。N+掺杂区730和734可以以与N+掺杂区110相似的方式形成并且栅极732和736可以以与栅极112或伪栅极116相似的方式形成。
ESD保护器件700可选择性地包括附加的N+掺杂区740和742,它们分别被配置为晶体管M3和M4的漏极区并且连接至焊盘。这些附加的漏极区740和742彼此间隔开并且通过连接至与漏极区110和120相同的电势的栅极744而临近N+掺杂区。栅极744可以以与栅极112或伪栅极116相似的方式形成。除了晶体管M3的放电路径a和b以及晶体管M4的放电路径c和d以外,这些附加的漏极区740和742在ESD保护器件700中提供了附加的放电路径。ESD充电电流通过路径a,b,c和d的放电与上述参照图2至图3的放电相似。从N+掺杂区740至P阱104(路径a*)和从P阱104至N+掺杂区108(路径b)可形成晶体管M3的附加的放电路径。并且,从N+掺杂区742至P阱104(路径c*)和从P阱104至N+掺杂区118(路径d)可形成晶体管M4的附加的放电路径。附加的放电路径有助于在ESD事件期间增大散热量,并由此提高ESD保护器件的放电电流处理能力。例如,在ESD事件期间,具有一个多漏极晶体管(即,具有一个附加的放电路径)的ESD保护器件在处理电流强度上可以是没有任何多漏极晶体管的ESD保护器件的两倍。在另一个实例中,在ESD事件期间,具有两个多漏极晶体管(即,具有两个附加的放电路径)的ESD保护器件在处理电流强度上可以是没有任何多漏极晶体管的ESD保护器件的2.5倍。
图9是一种基于PMOS漏极扩展的ESD保护器件900的示例性截面图。图9表明ESD保护器件700不限于NMOS晶体管并且可基于PMOS晶体管M5和M6实现。下文将讨论ESD保护器件700和ESD保护器件900之间的区别。
ESD保护器件900包括漏极扩展PMOS晶体管M5和M6,它们具有被配置作为源极区的P+掺杂区908,918、被配置作为漏极区的P+掺杂区910和920、栅极912和922、以及区908与区910之间、区918与区920之间的扩展漏极区。扩展漏极区包括浮动P+掺杂区930和934以及连接至与P+掺杂区910和920相同的电势(例如,焊盘的电势)的三个栅极732和三个栅极736。
寄生PNP晶体管Q5和Q6也包含在ESD保护器件900内。寄生PNP晶体管Q5和Q6包括作为集电极的晶体管M5和M6的漏极区、作为基极的形成在p衬底102上的N阱904、以及作为发射极的晶体管M5和M6的源极区。晶体管Q5和Q6的基极分别通过N+掺杂区914和924以及寄生电阻器R5和R6连接至电源轨VDD。寄生电阻器R5和R6表示N阱904的固有电阻。ESD保护器件900可以与ESD保护器件700相似的方式进行操作,但极性相反。例如,在ESD事件期间,晶体管Q5的通过放电路径e和f的充电电流和晶体管Q6的通过放电路径g和h的充电电流在分别与流经放电路径a和b以及放电路径c和d的充电电流相反的方向上流动。从P+掺杂区908至N阱904和从N阱904至P+掺杂区910可形成晶体管Q5的放电路径e和f。并且,从P+掺杂区918至N阱904以及从N阱904至P+掺杂区920可形成晶体管Q6的放电路径g和h。
ESD保护器件900可选择性地包括分别被配置作为晶体管M5和M6的漏极区且连接至焊盘的附加P+掺杂区740和742。与ESD保护器件700相似,除了晶体管M5的放电路径e和f以及晶体管M6的放电路径g和h以外,这些附加的漏极区在ESD保护器件900中提供了附加的放电路径。从P+掺杂区908至N阱904(路径e)和从N阱904至P+掺杂区740(路径f*)可形成晶体管M5的附加的放电路径。并且,从P+掺杂区918至N阱904(路径g)和从N阱904至P+掺杂区742(路径h*)可形成晶体管M6的附加的放电路径。
图10是一种示例性的IC中基于finFET漏极扩展的ESD保护器件1000的平面图。下文将讨论ESD保护器件500,700和1000之间的区别。ESD保护器件1000与ESD保护器件500相似,但区508与510之间以及区518与520之间分别具有FF3和FF4的附加扩展漏极区。扩展漏极区包括浮动N+掺杂外延鳍区1030和1040,以及连接至与N+掺杂区510和520相同的电势(例如,焊盘的电势)的栅极1032和1036。三个栅极1032中的相邻栅极之间的和三个栅极1036中的相邻栅极之间的间距满足RDR的多晶硅至多晶硅间距要求。因此,通过增加成对的具有与漏极区510和520相似的掺杂的掺杂区和增加连接至与漏极区510和520相同的电势的栅极来扩展晶体管FF3和FF4的漏极区510和520有助于增加NMOS晶体管M3和M4的漏极电阻同时满足RDR的多晶硅至多晶硅间距要求。设计在多晶硅至多晶硅间距要求内的基于finFET漏极扩展的ESD保护器件1000也有助于在finFET FF3和FF4的扩展漏极区中实现高质量的外延鳍区。ESD保护器件1000在材料组成和功能方面与ESD保护器件700相似。本领域的技术人员应该明白,使用p型finFET可实现ESD保护器件1000而不背离本发明的范围的情况。
ESD保护器件1000可选择性地包括分别被配置作为finFET FF3和FF4的漏极区且连接至焊盘的附加N+掺杂区1040和1042。与ESD保护器件700相似,除了通过finFET FF3(例如,N+掺杂区510至P阱104至N+掺杂区508)和FF4(例如,N+掺杂区520至P阱104至N+掺杂区518)的放电路径外,这些附加的漏极区在ESD保护器件1000中提供了附加的放电路径。从N+掺杂区1040至P阱104以及从P阱104至N+掺杂区508可形成finFET FF3的附加放电路径。并且,从N+掺杂区1042至P阱104以及从P阱104至N+掺杂区518可形成finFET FF4的附加放电路径。
图11是一种示例性的IC中基于堆叠NMOS晶体管的漏极扩展的ESD保护器件1100的平面图。图12是图11的ESD保护器件1100的截面图。图13是一种ESD保护器件1100的示例性的等效电路图。下文将讨论ESD保护器件700和1100之间的区别。ESD保护器件1100在结构、组成和功能方面与ESD保护器件700相似,但是ESD保护器件1100具有附加的N+掺杂区1146和栅极1148组成的对以及N+掺杂区1150和栅极1152组成的对。由N+掺杂区1146和栅极1148组成的这对与源极区108和漏极区110共同形成图13中所示的堆叠NMOS晶体管M7和M8。同样地,由N+掺杂区1150和栅极1152组成的对与源极区118和漏极区120共同形成图13中所示的堆叠NMOS晶体管M9和M10。可将N+掺杂区1146和1150与栅极1148和1152连接至电势。ESD保护器件1100可包括彼此堆叠在一起的两个或多个晶体管。寄生NPN晶体管Q1和Q2如在ESD保护器件700中一样也包含在ESD保护器件1100中且位于源极区108和漏极区110之间以及位于源极区118和漏极区120之间。
图14是一种示例性的IC中基于finFET的漏极扩展的ESD保护器件1100的平面图。下文将讨论ESD保护器件1000和1400之间的区别。ESD保护器件1400在结构、组成和功能方面与ESD保护器件1000相似,但是ESD保护器件1400具有附加的由N+掺杂外延鳍区1446和栅极1448组成的对以及由N+掺杂外延鳍区1450和栅极1452组成的对。由区1446和栅极1448组成的对连同源极区508和漏极区510共同形成如图13中的晶体管M7和M8的堆叠finFET。同样地,由区1150和栅极1152组成的对连同源极区518和漏极区520共同形成如图13中的晶体管M9和M10的堆叠finFET。
图15是一种示例性的IC中基于NMOS的漏极扩展的ESD保护器件1500的平面图。图16是图15的ESD保护器件1500的截面图。下文将讨论ESD保护器件700和1500之间的区别。ESD保护器件1500与ESD保护器件700相似,但ESD保护器件1500具有形成在N阱1504中的漏极区110和120、附加的漏极区740和742,以及具有晶体管M3和M4的N+掺杂区730和734的扩展漏极区。在一些实施例中,N+掺杂区730和734完全地或部分地形成在N阱1504内。即,区730和734的N+掺杂区中的一个或多个可形成在P阱104中。在一些实施例中,P阱104是P衬底102。
图17是一种示例性的IC中基于堆叠NNMOS晶体管的ESD保护器件1700的平面图。图18是图17的ESD保护器件1700的截面图。ESD保护器件1700与ESD保护器件1100相似,但是具有形成在N阱1504中的漏极区110和120、附加的漏极区740和742以及具有N+掺杂区730和734的扩展漏极区。在一些实施例中,N+掺杂区730和734完全地或部分地形成在N阱1504内。即,N+掺杂区730和734中的一个或多个可形成在P阱104中。在一些实施例中,P阱104是P衬底102。
图19是一种示例性的IC中基于finFET的漏极扩展的ESD保护器件1900。ESD保护器件1900与ESD保护器件1000相似,但是ESD保护器件1900具有形成在N阱1504中的漏极区510和520、附加的漏极区1040和1042、以及具有N+掺杂区1030和1034的扩展漏极区。在一些实施例中,N+掺杂区1030和1034完全地或部分地形成在N阱1504上方。即,N+掺杂区1030和1034中的一个或多个可形成在N阱104上方。在一些实施例中,P阱104是P衬底102。
图20是一种示例性的IC中基于PMOS的漏极扩展的ESD保护器件2000的平面图。ESD保护器件2000与ESD保护器件900相似,但是ESD保护器件2000具有形成在P衬底102上的深N阱2005。并且,漏极区910和920连同附加的漏极区740和742以及具有P+掺杂区930和934的扩展漏极区形成在深N阱2005上形成的P阱104中。在一些实施例中,P+掺杂区930和934完全地或部分地形成在P阱104上方。即,P+掺杂区930和934中的一个或多个可形成在深N阱2005上形成的N阱1504中。ESD保护器件2000还包含形成在P衬底102和阱104,1504之间的深N阱2005。
上文中描述的在N阱中形成ESD保护器件1500,1700和1900的N+掺杂扩展漏极区和在P阱中形成ESD保护器件2000的P+掺杂扩展漏极区可有助于进一步增大漏极电阻,并由此提高这些ESD保护器件的导通一致性。
图21是一种基于NMOS的ESD保护器件2100的示例性电路图,ESD保护器件2100的结构可与上文参照图1,2,5,7,8,10至12和14至19描述的ESD保护器件中的任何一个的结构相似。与上文讨论的ESD保护器件的各个实施例的操作相似,在ESD事件期间,ESD充电电流可通过寄生NPN晶体管Q11至Q14中的一个或多个从焊盘放电至电源轨VSS。为了ESD保护器件2200的有效性能,最好同时导通所有的NPN晶体管Q11至Q14。然而,由于寄生电阻器R11至R14的不同值和在晶体管M11至M14的金属布线中存在寄生电阻RP,所以晶体管Q11至Q12可经受导通电压V1,该电压与可被晶体管Q13至Q14经受的导通电压V2不同。并且,如果V1>V2,那么晶体管Q13至Q14可在ESD事件期间早于晶体管Q11至Q12导通并且ESD充电电流可仅通过晶体管Q13至Q14放电。这样会导致ESD保护器件2200的不良性能。
图22是一种示例性的具有镇流电阻器R15至R16的基于NMOS的ESD保护器件2200的电路图。镇流电阻器R15至R16有助于增大晶体管M11至M14的漏极电阻和降低寄生电阻RP对导通电压V1和V2的影响,由此减小电压V1和V2之差以用于导通一致性。
图23是一种示例性的图22的ESD保护器件2200的平面图。通过重复ESD保护器件700的结构和将其如图22的等效电路图所示并联在焊盘和电源轨VSS之间可实现ESD保护器件2200。每一对晶体管M11-M12和M13-M14可与ESD保护器件700的晶体管M3-M4相似。为了简明,在ESD保护器件2200中未示出附加的漏极区740和742,但是这些区可包含在器件2200中。通过增大漏极区110和120与焊盘之间的金属布线距离(例如,距离2254,2256)可在ESD保护器件2200中实现镇流电阻器R15-R16。
尽管示出的ESD保护器件2200具有与ESD保护器件700相似的结构,但是ESD保护器件2200的结构可与上文参照图7-8,10-12和14-19描述的ESD保护器件中的任意一个的结构相似。在不背离本发明的范围的情况下,还可基于PMOS晶体管实现ESD保护器件2200。
实例实施例和益处
在一个实施例中,ESD保护器件包括连接至第一电势的源极区、连接至不同于第一电势的第二电势的第一漏极区,以及位于源极区和第一漏极区之间的扩展漏极区。扩展漏极区包括N个浮动掺杂区和连接至第二电势的M个栅极区,其中,N和M是大于1的整数并且N等于M。N个浮动掺杂区中的每个浮动掺杂区与M个栅极区中的每个栅极区相间布置。
在一些实施例中,该ESD保护器件还包括:具有第一导电类型的阱区;以及其中,所述源极区、所述第一漏极区和所述N个浮动掺杂区位于所述阱区内并且具有不同于所述第一导电类型的第二导电类型。
在一些实施例中,该ESD保护器件还包括:第一阱区,具有第一导电类型;第二阱区,具有不同于所述第一导电类型的第二导电类型;以及其中,所述源极区、所述第一漏极区和所述N个浮动掺杂区具有所述第二导电类型,其中,所述源极区位于所述第一阱区,以及其中,所述第一漏极区和所述N个浮动掺杂区中的浮动掺杂区位于所述第二阱区内。
在一些实施例中,该ESD保护器件还包括:第一阱区,具有第一导电类型;以及第二阱区,具有不同于所述第一导电类型的第二导电类型;其中,所述N个浮动掺杂区具有所述第二导电类型,并且其中,所述N个浮动掺杂区中的浮动掺杂区部分地位于所述第一阱区内且部分地位于所述第二阱区内。
5.根据权利要求1所述的ESD保护器件,其中,所述源极区、所述第一漏极区和所述N个浮动掺杂区是外延鳍区。
6.根据权利要求1所述的ESD保护器件,还包括:栅电极,连接至位于所述源极区和所述扩展漏极区之间的所述第一电节点。
在一些实施例中,所述M个栅极区中的相邻栅极区之间的间距为标称相等。
在一些实施例中,所述M个栅极区的相邻栅极区之间的间距满足限制性设计规则(RDR)的要求。
在一些实施例中,该ESD保护器件还包括:第二漏极区,连接至所述第二电节点。
在一些实施例中,该ESD保护器件还包括:寄生晶体管,连接至所述源极区和所述第一漏极区。
在一些实施例中,该ESD保护器件还包括:掺杂区,连接至所述第一电节点,所述掺杂区具有不同于所述源极区和所述第一漏极区的导电类型;以及寄生电阻器,连接至所述寄生晶体管和所述掺杂区。
在一些实施例中,该ESD保护器件还包括:阱区,位于衬底上;以及放电路径,包括:第一路径,从所述第一漏极区至所述阱区;和第二路径,从所述阱区至所述源极区。
在一些实施例中,该ESD保护器件还包括:阱区,位于衬底上;第二漏极区,连接至所述第二电节点;第一放电路径,包括:第一路径,从所述第一漏极区至所述阱区,和第二路径,从所述阱区至所述源极区;以及第二放电路径,包括:第三路径,从所述第二漏极区至所述阱区,和第四路径,从所述阱区至所述源极区。
在一些实施例中,该ESD保护器件还包括:电浮动栅极区;以及隔离区,其中,所述源极区通过所述电浮动栅极区与所述隔离区间隔开。
在进一步的实施例中,ESD保护器件包括具有第一导电类型的第一阱区和具有不同于第一导电类型的第二导电类型的源极区。源极区位于第一阱区内。ESD保护器件还包括具有第二导电类型的第一漏极区和具有电浮动的掺杂区和栅极区的扩展漏极区。扩展漏极区的第一部分位于第一阱区内。
在一些实施例中,该ESD保护器件还包括:第二阱区,具有所述第二导电类型;其中,所述漏极区位于所述第二阱区内,并且其中,所述扩展漏极区的第二部分位于所述第二阱内。
在一些实施例中,电浮动掺杂区的数量等于栅极区的数量;所述电浮动掺杂区的每一个与所述栅极区的每一个相间布置;以及
在一些实施例中,电浮动掺杂区的数量等于栅极区的数量;所述电浮动掺杂区的每一个与所述栅极区的每一个相间布置;以及所述栅极区和所述第一漏极区连接至相同的电节点。
在一些实施例中,该ESD保护器件还包括:第二漏极区,连接至与所述第一漏极区相同的电节点;第一放电路径,包括:第一路径,从所述第一漏极区至所述第一阱区,和第二路径,从所述第一阱区至所述源极区;以及第二放电路径,包括:第三路径,从所述第二漏极区至所述第一阱区;和第四路径,从所述第一阱区至所述源极区。在进一步的实施例中,集成电路包括I/O焊盘、电源轨、连接至I/O焊盘和电源轨的ESD保护器件,以及并联至ESD保护器件的ESD保护电路。ESD保护器件包括连接至电源轨的源极区、连接至I/O焊盘的漏极区,以及位于源极区和漏极区之间的扩展漏极区。扩展漏极区包括电浮动掺杂区和连接至I/O焊盘的栅极区。电浮动掺杂区中的每一个与栅极区中的每一个相间布置。
在一些实施例中,所述源极区、所述漏极区和所述电浮动掺杂区是外延鳍区。
上述发明论述了若干实施例的部件,使得本领域的普通技术人员可以更好地理解本发明的各个方面。本领域的普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域的普通技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离增补权利要求的精神和范围的情况下,可以进行多种变化、更换以及改变。
Claims (10)
1.一种静电放电ESD保护器件,包括:
源极区,连接至第一电节点;
第一漏极区,连接至不同于所述第一电节点的第二电节点;以及
扩展漏极区,位于所述源极区和所述第一漏极区之间,所述扩展漏极区包括:
N个电浮动掺杂区;和
M个栅极区,连接至所述第二电节点,
其中,N和M是大于1的整数,并且
其中,所述N个电浮动掺杂区中的一个或多个浮动掺杂区与所述M个栅极区中的一个或多个栅极区相间布置。
2.根据权利要求1所述的ESD保护器件,还包括:具有第一导电类型的阱区;以及
其中,所述源极区、所述第一漏极区和所述N个浮动掺杂区位于所述阱区内并且具有不同于所述第一导电类型的第二导电类型。
3.根据权利要求1所述的ESD保护器件,还包括:
第一阱区,具有第一导电类型;
第二阱区,具有不同于所述第一导电类型的第二导电类型;以及
其中,所述源极区、所述第一漏极区和所述N个浮动掺杂区具有所述第二导电类型,
其中,所述源极区位于所述第一阱区,以及
其中,所述第一漏极区和所述N个浮动掺杂区中的浮动掺杂区位于所述第二阱区内。
4.根据权利要求1所述的ESD保护器件,还包括:
第一阱区,具有第一导电类型;以及
第二阱区,具有不同于所述第一导电类型的第二导电类型;
其中,所述N个浮动掺杂区具有所述第二导电类型,并且
其中,所述N个浮动掺杂区中的浮动掺杂区部分地位于所述第一阱区内且部分地位于所述第二阱区内。
5.根据权利要求1所述的ESD保护器件,其中,所述源极区、所述第一漏极区和所述N个浮动掺杂区是外延鳍区。
6.根据权利要求1所述的ESD保护器件,还包括:栅电极,连接至位于所述源极区和所述扩展漏极区之间的所述第一电节点。
7.一种静电放电ESD保护器件,包括:
第一阱区,具有第一导电类型;
源极区,具有与所述第一导电类型不同的第二导电类型,所述源极区位于所述第一阱区内;
第一漏极区,具有所述第二导电类型;以及
扩展漏极区,具有电浮动掺杂区和栅极区,
其中,所述扩展漏极区的第一部分位于所述第一阱区内。
8.根据权利要求7所述的ESD保护器件,还包括:
第二阱区,具有所述第二导电类型;
其中,所述漏极区位于所述第二阱区内,并且
其中,所述扩展漏极区的第二部分位于所述第二阱内。
9.一种集成电路IC,包括:
I/O焊盘;
电源轨;
静电放电ESD保护器件,连接至所述I/O焊盘和所述电源轨,所述ESD保护器件包括:
源极区,连接至所述电源轨;
漏极区,连接至所述I/O焊盘;和
扩展漏极区,位于所述源极区和所述漏极区之间的,所述扩展漏极区包括:
电浮动掺杂区,和
栅极区,连接至所述I/O焊盘,
其中,所述电浮动掺杂区中的每一个与所述栅极区中的每一个相间布置;以及
ESD保护电路,与所述ESD保护器件并联。
10.根据权利要求9所述的IC,其中,所述源极区、所述漏极区和所述电浮动掺杂区是外延鳍区。
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KR20180062342A (ko) | 2018-06-08 |
DE102017118563B4 (de) | 2020-09-24 |
US20200411506A1 (en) | 2020-12-31 |
KR20190086425A (ko) | 2019-07-22 |
TWI655743B (zh) | 2019-04-01 |
CN108122902B (zh) | 2020-12-08 |
DE102017118563A1 (de) | 2018-05-30 |
US10777546B2 (en) | 2020-09-15 |
US20180151554A1 (en) | 2018-05-31 |
TW201830651A (zh) | 2018-08-16 |
KR102124887B1 (ko) | 2020-06-22 |
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